JPH0529155U - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH0529155U JPH0529155U JP085816U JP8581691U JPH0529155U JP H0529155 U JPH0529155 U JP H0529155U JP 085816 U JP085816 U JP 085816U JP 8581691 U JP8581691 U JP 8581691U JP H0529155 U JPH0529155 U JP H0529155U
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor chip
- metal base
- semiconductor device
- lead terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】 （修正有）
【目的】 金属ベ−ス又はリ−ド端子をプリント配線板
等の基板にろう付けにより表面実装する樹脂封止型半導
体装置の耐湿信頼性を向上するものである。
【構成】 半導体チップ４、金属ベ−ス３及びリ−ド端
子２の封止樹脂と接する表面の一部又は全部に、少なく
とも銅材と接する部分にはニッケルメッキ層６を介し、
ポリイミド系樹脂を被着したことを特徴とする。
(57) [Summary] (Corrected) [Purpose] Improving the humidity resistance reliability of resin-sealed semiconductor devices in which metal bases or lead terminals are surface-mounted on a substrate such as a printed wiring board by brazing. Is. A nickel plating layer 6 is provided on a part or all of the surfaces of the semiconductor chip 4, the metal base 3 and the lead terminal 2 which are in contact with the sealing resin, and at least the portions which are in contact with the copper material.
It is characterized in that a polyimide resin is applied.
Description
【０００１】[0001]
本考案は、樹脂封止型半導体装置の構造、特に、表面実装用に適した樹脂封 止型半導体装置に関するものである。 The present invention relates to a structure of a resin-sealed semiconductor device, and more particularly to a resin-sealed semiconductor device suitable for surface mounting.
【０００２】[0002]
樹脂封止型半導体装置の一般的な形状として、図１の断面構造図に示すごと きものが知られている。図１の１は封止樹脂、２はリ−ド端子、３は金属ベ −スであり、平滑な金属ベ−ス３上に、ダイオ−ド、トランジスタ、サイリ スタなどの半導体チップ４を直接又は金属板を介して、固着し、リ−ド端子 ２と半導体チップ４を内部ワイヤ−５で配線し、次いで、エポキシ樹脂など の封止樹脂１でモ−ルドしている。通常、金属ベ−ス３やリ−ド端子２はリ −ドフレ−ムによって形成される。又、内部ワイヤ−５は板状の接続片を用 いることもある。なお、パワ−用半導体装置においては、金属ベ−ス３やリ −ド端子２は銅材を用い、又、太線アルミワイヤ−の使用の関係等により、 銅材の表面にニッケルメッキ層６を形成するのが一般的である。 As a general shape of a resin-encapsulated semiconductor device, one having a cross-sectional structure shown in FIG. 1 is known. In FIG. 1, 1 is a sealing resin, 2 is a lead terminal, 3 is a metal base, and a semiconductor chip 4 such as a diode, a transistor or a thyristor is directly mounted on a smooth metal base 3. Alternatively, the lead terminal 2 and the semiconductor chip 4 are fixed to each other via a metal plate, and are wired by an internal wire-5, and then are molded with a sealing resin 1 such as an epoxy resin. Usually, the metal base 3 and the lead terminal 2 are formed by a lead frame. The inner wire-5 may be a plate-shaped connecting piece. In the power semiconductor device, the metal base 3 and the lead terminal 2 are made of a copper material, and the nickel plating layer 6 is formed on the surface of the copper material due to the use of a thick aluminum wire. It is generally formed.
【０００３】 図１において、金属ベ−ス３の下面、即ち、半導体チップ４の固着面と反対 （２） の面は樹脂被覆されず、露出して、表面実装におけるろう付け部７を形成す る。このような半導体装置をプリント配線板等の基板８に表面実装する場合、 基板８上に前記せるろう付け部７をろう材９により固着する。In FIG. 1, the lower surface of the metal base 3, that is, the surface (2) opposite to the fixing surface of the semiconductor chip 4 is not covered with resin and is exposed to form a brazing portion 7 for surface mounting. It When such a semiconductor device is surface-mounted on a substrate 8 such as a printed wiring board, the brazing portion 7 is fixed on the substrate 8 with a brazing material 9.
【０００４】 従って、半導体装置はろう付け時に２００℃以上の高温にさらされるため、 封止樹脂１と、リ−ド端子２、金属ベ−ス３又は半導体チップ４の接する面 が熱膨張係数の違いによる熱ストレスにより剥離し、１、２間、１、３間、 又は１、４間にすき間が発生する。そのため、実装前、即ち、高温にさらさ れる前に比して耐湿信頼性が大幅に低下する欠点があった。（図４の「従来 品サンプル」を参照のこと。）Therefore, since the semiconductor device is exposed to a high temperature of 200 ° C. or higher during brazing, the contact surface of the sealing resin 1, the lead terminal 2, the metal base 3 or the semiconductor chip 4 has a coefficient of thermal expansion. Peeling occurs due to heat stress due to the difference, and a gap is generated between 1, 2, 1, 3, or 1, 4. Therefore, there is a drawback that the moisture resistance reliability is significantly reduced as compared with before mounting, that is, before being exposed to high temperature. (See "Conventional sample" in Figure 4.)
【０００５】[0005]
解決しようとする問題点は、樹脂封止型半導体装置を基板上にろう付けする ことに起因して発生する樹脂と、金属ベ−ス、半導体チップ又はリ−ド端子 間の剥離等による耐湿信頼性の低下する点である。 The problem to be solved is moisture resistance reliability due to peeling between resin and metal base, semiconductor chip or lead terminal caused by brazing resin-sealed semiconductor device on the substrate. This is the point where sex is lowered.
【０００６】[0006]
本考案は封止樹脂と接する半導体チップ、金属ベ−ス及びリ−ド端子の表面 の一部又は全部にポリイミド系樹脂を被着するものであり、その被着におい て、銅材部分にはニッケルメッキ層を介在させることを特徴とする。これに より耐湿信頼性向上の目的を簡単な構造により実現した。 In the present invention, a polyimide resin is adhered to a part or all of the surface of the semiconductor chip, the metal base and the lead terminal which are in contact with the encapsulating resin. It is characterized by interposing a nickel plating layer. With this, the purpose of improving the humidity resistance reliability was realized by a simple structure.
【０００７】[0007]
図２は本考案の実施例を示す断面構造図であり、図１と同一符号は同一部分 をあらわしている。 2 is a sectional structural view showing an embodiment of the present invention, in which the same reference numerals as those in FIG. 1 represent the same parts.
【０００８】 図２において、ニッケルメッキ層６を表面に形成した銅材から成る金属ベ− ス３及び半導体チップ４の封止樹脂１と接触する表面にポリイミド系樹脂１ （３） ０を被着介在させた。実施例では、ポリイミド系樹脂１０を厚さ数μｍから １０μｍ程度、塗布により被着した。In FIG. 2, a polyimide resin 1 (3) 0 is adhered to the metal base 3 made of a copper material on the surface of which a nickel plating layer 6 is formed and the surface of the semiconductor chip 4 in contact with the sealing resin 1. Intervened. In the example, the polyimide-based resin 10 was applied to a thickness of several μm to 10 μm by coating.
【０００９】 図３はポリイミド系樹脂の塗布と接着強度の関係を実験により求めたもので 、リ−ドフレ−ム状に形成した金属ベ−ス３を銅材のままのものと、ニッケ ルメッキ層６をもつものとに区分して測定した。 図３から本考案構造のＮｉメッキ処理をしたリ−ドフレ−ムにポリイミド系 樹脂を塗布したものは接着強度が８０Ｋｇ／ｃｍ2を超えて、測定用リ−ド が破断し、測定不能となる程であった。又、銅材のままのリ−ドフレ−ムの もの、及びＮｉメッキ処理したリ−ドフレ−ムでもポリイミド系樹脂の無い ものはいずれも４０Ｋｇ／ｃｍ2以下となった。なお、銅材のままのリ−ド フレ−ムにポリイミド系樹脂を塗布しても接着強度が低下する原因は、ポリ イミド系樹脂硬化時に大気中で熱処理された酸素により銅材の表面に強度の 弱い酸化膜が成長したためと考えられる。FIG. 3 shows the relationship between the application of the polyimide-based resin and the adhesive strength obtained by experiments. The metal base 3 formed in the lead frame shape is the copper material as it is, and the nickel plating layer. The measurement was carried out by classifying into those having 6 and those having 6. From FIG. 3, the Ni-plated lead frame of the present invention coated with polyimide resin has an adhesive strength of more than 80 kg / cm @ 2, and the measurement lead breaks and the measurement becomes impossible. Met. Further, the lead frame of the copper material as it is and the lead frame of the Ni-plated lead frame without the polyimide resin were all below 40 kg / cm @ 2. The reason why the adhesive strength is reduced even when the polyimide resin is applied to the lead frame of the copper material as it is is that the strength of the strength of the copper material surface is increased by the oxygen heat-treated in the atmosphere when the polyimide resin is cured. It is thought that this is because the weak oxide film has grown.
【００１０】 又、図４に従来品と本考案品の耐湿性試験結果図を示す。図４は熱処理（２ ６０℃、１０秒）後のプレッシャ−クッカ−試験（１２１℃、１００％、２ 気圧）の試験時間に対する不良率を示しており、本考案品が従来品に比し、 優れていることがわかる。Further, FIG. 4 shows the results of the moisture resistance test of the conventional product and the device of the present invention. FIG. 4 shows the defective rate with respect to the test time of the pressure cooker test (121 ° C., 100%, 2 atm) after the heat treatment (260 ° C., 10 seconds). It turns out to be excellent.
【００１１】 図２の実施例において、ポリイミド系樹脂の被着は金属ベ−ス３及び半導体 チップ４の表面に形成したが、必要に応じ、リ−ド端子２の表面に形成して もよく、又、半導体チップの上には被着しないようにしてもよい。しかして、 表面実装におけるはんだ侵漬等のろう付時に高温にさらされる金属部分には 特に、被着することが望ましい。In the embodiment of FIG. 2, the polyimide resin is formed on the surface of the metal base 3 and the semiconductor chip 4, but it may be formed on the surface of the lead terminal 2 if necessary. Alternatively, it may not be deposited on the semiconductor chip. Therefore, it is particularly desirable to adhere to metal parts exposed to high temperature during brazing such as solder immersion in surface mounting.
【００１２】 本考案装置はその他、実施例の形状に限定するものではなく、例えば、半導 体チップの複数固着、他部品との混成固着、リ−ド端子の増減や引出し方向 （４） の変更、金属ベ−スや樹脂の形状変更など、本考案の要旨の範囲で種々の選 択をなし得る。The device of the present invention is not limited to the shapes of the other embodiments. For example, a plurality of semiconductor chips may be fixedly bonded, other semiconductor chips may be mixedly fixed, lead terminals may be increased or decreased, and the lead-out direction (4) may be changed. Various selections can be made within the scope of the present invention, such as changes and changes in the shape of the metal base and resin.
【００１３】[0013]
以上、説明したように本考案の樹脂封止型半導体装置は、表面実装時のろう 付けによる高温処理を行っても耐湿信頼性を低下させないため、プリント配 線板等の基板へのろう付けに適したものであり、電子機器等に利用して、産 業上の効果大なるものである。 As described above, the resin-encapsulated semiconductor device of the present invention does not deteriorate the moisture resistance reliability even when subjected to high temperature treatment by brazing during surface mounting, so that it is suitable for brazing to a printed wiring board or other substrate. It is suitable for use in electronic equipment, etc., and has great industrial effects.
【図１】従来装置の断面構造図である。FIG. 1 is a sectional structural view of a conventional device.
【図２】本考案の実施例を示す断面構造図である。FIG. 2 is a sectional structural view showing an embodiment of the present invention.
【図３】接着強度試験結果図である。FIG. 3 is a result diagram of an adhesive strength test.
【図４】耐湿性試験結果図である。FIG. 4 is a diagram showing results of a moisture resistance test.
１ 封止樹脂 ２ リ−ド端子 ３ 金属ベ−ス ４ 半導体チップ ５ 内部ワイヤ− ６ ニッケルメッキ層 ７ ろう付け部 ８ 基板 ９ ろう材 １０ ポリイミド系樹脂 1 Sealing Resin 2 Lead Terminal 3 Metal Base 4 Semiconductor Chip 5 Internal Wire 6 Nickel Plating Layer 7 Brazing Section 8 Substrate 9 Brazing Material 10 Polyimide Resin
Claims (1)
を介して半導体チップを固着し他面にろう付け部を有す
る金属ベ−スと、リ−ド端子と、封止樹脂とから成る樹
脂封止型半導体装置において、前記の半導体チップ、金
属ベ−ス及びリ−ド端子の封止樹脂と接する表面の一部
又は全部に、少なくとも銅材と接する部分にはニッケル
メッキ層を介し、ポリイミド系樹脂を被着したことを特
徴とする樹脂封止型半導体装置。1. A resin comprising a semiconductor chip, a metal base having a semiconductor chip fixed to one surface directly or via a metal plate and having a brazing portion on the other surface, a lead terminal, and a sealing resin. In the sealed semiconductor device, a nickel plating layer is provided on a part or all of the surfaces of the semiconductor chip, the metal base and the lead terminal which are in contact with the sealing resin, and a nickel plating layer is provided at least in a portion in contact with the copper material. A resin-encapsulated semiconductor device, which is coated with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991085816U JP2555519Y2 (en) | 1991-09-25 | 1991-09-25 | Surface-mount resin-encapsulated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991085816U JP2555519Y2 (en) | 1991-09-25 | 1991-09-25 | Surface-mount resin-encapsulated semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0529155U true JPH0529155U (en) | 1993-04-16 |
| JP2555519Y2 JP2555519Y2 (en) | 1997-11-26 |
Family
ID=13869385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1991085816U Expired - Fee Related JP2555519Y2 (en) | 1991-09-25 | 1991-09-25 | Surface-mount resin-encapsulated semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2555519Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01145840A (en) * | 1987-12-01 | 1989-06-07 | Nec Corp | Resin-sealed semiconductor device |
-
1991
- 1991-09-25 JP JP1991085816U patent/JP2555519Y2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01145840A (en) * | 1987-12-01 | 1989-06-07 | Nec Corp | Resin-sealed semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2555519Y2 (en) | 1997-11-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |