JPH05291163A - Substrate heat treatment method - Google Patents

Substrate heat treatment method

Info

Publication number
JPH05291163A
JPH05291163A JP11409592A JP11409592A JPH05291163A JP H05291163 A JPH05291163 A JP H05291163A JP 11409592 A JP11409592 A JP 11409592A JP 11409592 A JP11409592 A JP 11409592A JP H05291163 A JPH05291163 A JP H05291163A
Authority
JP
Japan
Prior art keywords
heat treatment
substrate
heat
wafer
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11409592A
Other languages
Japanese (ja)
Other versions
JP3158307B2 (en
Inventor
Kikuo Kaise
喜久夫 貝瀬
Takuo Sato
拓生 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP11409592A priority Critical patent/JP3158307B2/en
Publication of JPH05291163A publication Critical patent/JPH05291163A/en
Application granted granted Critical
Publication of JP3158307B2 publication Critical patent/JP3158307B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To suppress thermal deformation of a substrate when a vertical type heat treatment device is used. CONSTITUTION:Substrates or wafers 1 are heat-treated at least two times in a vertical type heat treatment device wherein the wafers 1 are heat-treated by inserting a boat 3 horizontally holding the substrates or wafers 1 into a reaction tube. During the first preceding heat treatment step, the wafers 1 are heat-treated in the attitude with the heat-treated surface or the surface 1f turned upward while during the second following heat-treatment step, the wafers 1 are heat-treated in the attitude with the surface if turned downward. Through these procedures, the thermal deformation caused during both steps can be offset with each other thereby enabling the net warping amount to be decreased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はアクティブマトリクス型
液晶表示装置やラインセンサ等に用いられる薄膜素子基
板の製造方法に関する。より詳しくは、製造工程中にお
ける縦型熱処理装置を用いた基板の熱処理方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film element substrate used in an active matrix type liquid crystal display device, a line sensor or the like. More specifically, the present invention relates to a heat treatment method for a substrate using a vertical heat treatment apparatus during a manufacturing process.

【0002】[0002]

【従来の技術】薄膜トランジスタ等の薄膜素子が集積的
に形成された基板(以下薄膜素子基板と称する)は、従
来からアクティブマトリクス型液晶表示装置、プラズマ
ディスプレイ、ELディスプレイあるいはラインセンサ
等の構成部材として広く用いられている。薄膜素子は基
板表面に成膜された多結晶シリコンや非晶質シリコン等
からなる薄膜を半導体活性層としLSI製造プロセスを
適用して集積的に形成される。LSI製造プロセスには
不純物拡散工程、ゲート絶縁膜形成工程あるいはアニー
ル工程といった高温熱処理が含まれており、基板は製造
工程中における最高処理温度に耐える事のできる優れた
耐熱性を備えていなければならない。この最高処理温度
は薄膜材料や適用されるLSI製造プロセスの内容によ
って異なっている。基板としてガラス材料を採用する場
合にも最高処理温度によって適切なものが選択される。
例えば、非晶質シリコン薄膜トランジスタ素子を形成す
る場合には最高処理温度は一般に500℃程度になる。
この場合には約600℃程度の歪点を有するバリウム硼
硅酸ガラス(例えばコーニング7059)が使われる。
なお、歪点は材料の粘度が約1013.5Pa・sになる温
度をもって定義され耐熱性の尺度となる。又多結晶シリ
コン薄膜を用いてトランジスタ素子を形成する場合に
は、ゲート絶縁膜の形成方法としてCVDを用いた時、
最高処理温度は600℃程度に達する。この場合には、
基板材料として約640℃の歪点を有するアルミナ硼硅
酸ガラス(例えばコーニング1733)が使われる。ゲ
ート絶縁膜の形成方法としてCVDに代え熱酸化処理を
用いた場合には基板処理温度が1000℃程度に達す
る。この時には、約1060℃の歪点を有する石英ガラ
スが基板材料として用いられる。この他にもLSI製造
工程中の最高処理温度に応じて様々な種類のガラス材料
が用いられている。
2. Description of the Related Art A substrate on which thin film elements such as thin film transistors are integrally formed (hereinafter referred to as a thin film element substrate) has been conventionally used as a constituent member of an active matrix type liquid crystal display device, a plasma display, an EL display or a line sensor. Widely used. The thin film element is formed in an integrated manner by applying an LSI manufacturing process using a thin film of polycrystalline silicon or amorphous silicon formed on the surface of the substrate as a semiconductor active layer. The LSI manufacturing process includes high temperature heat treatment such as an impurity diffusion process, a gate insulating film forming process or an annealing process, and the substrate must have excellent heat resistance capable of withstanding the maximum processing temperature during the manufacturing process. .. This maximum processing temperature differs depending on the thin film material and the content of the applied LSI manufacturing process. Even when a glass material is used as the substrate, an appropriate one is selected depending on the maximum processing temperature.
For example, the maximum processing temperature is generally about 500 ° C. when forming an amorphous silicon thin film transistor element.
In this case, barium borosilicate glass (for example, Corning 7059) having a strain point of about 600 ° C. is used.
The strain point is defined as the temperature at which the viscosity of the material becomes about 10 13.5 Pa · s and is a measure of heat resistance. When a transistor element is formed using a polycrystalline silicon thin film, when CVD is used as a method for forming a gate insulating film,
The maximum processing temperature reaches about 600 ° C. In this case,
Alumina borosilicate glass (eg Corning 1733) having a strain point of about 640 ° C. is used as the substrate material. When thermal oxidation is used instead of CVD as the method for forming the gate insulating film, the substrate processing temperature reaches about 1000 ° C. At this time, quartz glass having a strain point of about 1060 ° C. is used as a substrate material. In addition to this, various kinds of glass materials are used according to the maximum processing temperature in the LSI manufacturing process.

【0003】しかしながら基板は歪点以下であっても高
温になるに従って粘度は低下していく。特にガラス材料
は非晶質である為その粘度は温度の上昇に伴なって略単
調に低下する。この為歪点より100℃程度低い温度で
熱処理を加えても若干変形する性質がある。
However, even if the temperature of the substrate is below the strain point, the viscosity decreases as the temperature rises. In particular, since the glass material is amorphous, its viscosity decreases almost monotonically as the temperature rises. Therefore, even if a heat treatment is applied at a temperature about 100 ° C. lower than the strain point, it has a property of being slightly deformed.

【0004】[0004]

【発明が解決しようとする課題】従来半導体製造プロセ
スに用いられる熱処理装置としては横型のものが用いら
れていた。横型は熱処理の対象となる基板あるいはウェ
ハを複数枚ボートに立て掛けた状態で炉内に配置する構
造となっており、ウェハ搬送時における空気の逆流が少
ない点に特徴がある。しかしながら、近年ではウェハの
大径化が進み且つ高集積化に伴ない高品質での処理能力
が求められている。そこで、省スペースと熱処理の均一
性の観点から、横型に代えて縦型の熱処理装置が主流に
なってきている。この熱処理装置には例えば拡散/酸化
炉やLP−CVD炉等が含まれる。縦型の熱処理装置に
ついては例えば特開平3−235329号公報に開示が
ある。
Conventionally, a horizontal type heat treatment apparatus has been used for a semiconductor manufacturing process. The horizontal type has a structure in which a plurality of substrates or wafers to be heat treated are placed in a furnace while leaning against a boat, and is characterized in that there is little backflow of air during wafer transfer. However, in recent years, as the diameter of wafers has increased, and with high integration, high-quality processing capability has been demanded. Therefore, from the viewpoint of space saving and uniformity of heat treatment, a vertical type heat treatment apparatus has become the mainstream instead of the horizontal type. This heat treatment apparatus includes, for example, a diffusion / oxidation furnace and an LP-CVD furnace. A vertical heat treatment apparatus is disclosed in, for example, Japanese Patent Laid-Open No. 3-235329.

【0005】この縦型ではボートによりウェハの端部の
みを支持して水平に保持する構造となっている。従っ
て、基本的にウェハの自重による熱変形が起り易い支持
構造である。この為、縦型の熱処理装置を用いると、例
え歪点より100℃程度低い温度で熱処理を施しても自
重によりウェハの反り変形が発生するという課題あるい
は問題点があった。特に、薄膜素子製造プロセスでは不
純物拡散工程、熱酸化によるゲート絶縁膜形成工程、ア
ニール工程等複数回の熱処理が繰り返し行なわれる。1
回の熱処理で発生する反り量が小さくても熱履歴を繰り
返す毎に変形が累積され、最終的には大きな反り量とな
ってしまう。基板に反りが生じると、後工程でウェハの
搬送トラブルや露光装置のステージ吸着不良による露光
欠陥等の故障が発生する。又、基板変形に伴ない薄膜内
部のストレスが増大し薄膜素子の電気特性不良が発生す
る。ウェハが大径化すると反りの絶対量が益々増大する
為様々な不良、故障あるいは欠陥が多発する。薄膜素子
基板の大径化が進んでいる現在、反り等の熱変形を避け
る為には歪点の高い耐熱性の優れた高価な基板材料例え
ば石英ガラスを使わざるを得ず、製造コストの上昇を招
いていた。又、石英ガラスを用いた場合であっても、歪
点近傍で熱処理を行なった場合には熱変形を避ける事が
できない。一般に、熱処理温度が高い程機能的に安定し
た薄膜素子が得られる。しかしながら、現実には熱変形
を抑える観点から処理温度を高く設定できないという問
題点がある。
This vertical type has a structure in which only the end portion of the wafer is supported by a boat and held horizontally. Therefore, the support structure is basically susceptible to thermal deformation due to the weight of the wafer. Therefore, when the vertical heat treatment apparatus is used, there is a problem or a problem that the warp deformation of the wafer occurs due to its own weight even if the heat treatment is performed at a temperature about 100 ° C. lower than the strain point. Particularly, in the thin film element manufacturing process, a plurality of heat treatments such as an impurity diffusion step, a gate insulating film forming step by thermal oxidation, and an annealing step are repeatedly performed. 1
Even if the amount of warpage generated by one heat treatment is small, the deformation is accumulated each time the thermal history is repeated, and finally the amount of warpage becomes large. When the substrate is warped, a trouble such as a wafer transfer trouble or an exposure defect due to a stage suction failure of the exposure device occurs in a subsequent process. In addition, the stress inside the thin film increases as the substrate is deformed, and the electrical characteristics of the thin film element are deteriorated. As the diameter of the wafer increases, the absolute amount of warpage increases, and various defects, failures, or defects frequently occur. At present, as the diameter of thin film element substrates is increasing, in order to avoid thermal deformation such as warpage, it is necessary to use expensive substrate materials with high strain point and excellent heat resistance, such as quartz glass, which increases manufacturing costs. Was invited. Even if quartz glass is used, thermal deformation cannot be avoided when heat treatment is performed near the strain point. Generally, the higher the heat treatment temperature, the more functionally stable thin film device can be obtained. However, in reality, there is a problem that the processing temperature cannot be set high from the viewpoint of suppressing thermal deformation.

【0006】[0006]

【課題を解決するための手段】上述した従来の技術の課
題あるいは問題点に鑑み、本発明は縦型の熱処理装置を
用いて基板の歪点近傍で熱処理を施してもウェハの熱変
形を抑制する事のできる基板熱処理方法を提供する事を
目的とする。又、熱変形を抑制する事により通常の耐熱
性を有する安価な基板を用いても高収率の生産が可能と
なる様な基板熱処理方法を提供する事を目的とする。か
かる目的を達成する為に、基板を所定のピッチで水平に
保持したボートを反応管の内部に挿入して熱処理を行な
う縦型の熱処理装置で基板を少なくとも2回以上熱処理
する基板熱処理方法において、前記基板の熱処理面を上
に向けて処理する第1の熱処理工程と前記熱処理面を下
に向けて処理する第2の熱処理工程とを行なうという手
段を講じた。
In view of the above-mentioned problems and problems of the conventional technique, the present invention suppresses thermal deformation of a wafer even when heat treatment is performed near the strain point of a substrate using a vertical heat treatment apparatus. It is an object of the present invention to provide a substrate heat treatment method that can be performed. Another object of the present invention is to provide a substrate heat treatment method that suppresses thermal deformation and enables high-yield production even when using an inexpensive substrate having ordinary heat resistance. In order to achieve such an object, in a substrate heat treatment method in which a boat holding a substrate horizontally at a predetermined pitch is inserted into a reaction tube to perform heat treatment, the substrate is heat-treated at least twice or more in a vertical heat treatment apparatus. Measures were taken to perform a first heat treatment step of treating the substrate with the heat treatment surface facing upward and a second heat treatment step of treating the substrate with the heat treatment surface facing downward.

【0007】[0007]

【作用】本発明によれば、縦型の熱処理装置を使用して
熱処理を複数回行なう場合、先の熱処理では基板の熱処
理面即ち表側を上に向けた姿勢でボートにセットし、後
の熱処理では基板の裏側を上に向けた姿勢でボートにセ
ットする様にした。この為、先の熱処理の場合と後の熱
処理の場合とで、自重による基板の反り変形の方向が逆
となり、お互いの反りが相殺もしくは補償され熱変形が
累積されない。つまり本発明にあっては、熱処理を複数
回繰り返しても反り変形が累積されず大きな熱変形を回
避する事ができる。これにより、歪点の高い高価な基板
材料を使う必要がなく、ウェハを大径化した場合にも反
り変形を有効に防止する事ができる為高収率な薄膜素子
基板の生産が可能になる。
According to the present invention, when the vertical heat treatment apparatus is used to perform the heat treatment a plurality of times, the heat treatment of the substrate is set in the boat in a posture with the heat treatment surface, that is, the front side facing upward, and the heat treatment of the subsequent heat treatment is performed. Then, I set it on the boat with the back side of the board facing up. Therefore, the warp deformation direction of the substrate due to its own weight is opposite between the case of the first heat treatment and the case of the latter heat treatment, the mutual warp is offset or compensated, and the heat deformation is not accumulated. That is, in the present invention, even if the heat treatment is repeated a plurality of times, the warp deformation is not accumulated, and large heat deformation can be avoided. As a result, it is not necessary to use an expensive substrate material having a high strain point, and it is possible to effectively prevent warp deformation even when the diameter of the wafer is increased, so that it is possible to produce a high yield thin film element substrate. ..

【0008】[0008]

【実施例】以下図面を参照して本発明の好適な実施例を
詳細に説明する。図1は本発明にかかる基板熱処理方法
の基本的な概念を説明する為の工程図である。熱処理の
対象となる基板あるいはウェハ1は例えば直径150mm
の大径丸型石英ガラス板からなる。このウェハ1は薄膜
素子が形成される熱処理面あるいは表面1fと反対側の
裏面1rを有する。熱処理を行なうに当って個々のウェ
ハ1は溝2が形成された縦型配置のボート3に水平にセ
ットされる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a process diagram for explaining the basic concept of the substrate heat treatment method according to the present invention. The substrate or wafer 1 to be heat-treated has a diameter of 150 mm, for example.
It consists of a large diameter round quartz glass plate. The wafer 1 has a heat treatment surface on which thin film elements are formed or a back surface 1r opposite to the front surface 1f. In performing the heat treatment, the individual wafers 1 are horizontally set on the boat 3 in the vertical arrangement in which the grooves 2 are formed.

【0009】先行する第1の熱処理工程では個々のウェ
ハ1の表面1fを上に向けた姿勢でボート3にセットす
る。一方、後続の第2の熱処理工程では個々のウェハ1
は反転された状態で搬送され裏面1rが上に向いた姿勢
でボート3にセットされる。第1の熱処理工程で生じる
熱変形によりウェハ1は裏面1r側が凸形状になる。こ
の凸形状になった裏面を上にして第2の熱処理工程を行
なうと重力の作用により凸形状が平坦形状に戻される。
In the preceding first heat treatment step, the front surface 1f of each wafer 1 is set on the boat 3 with its posture facing upward. On the other hand, in the subsequent second heat treatment step, the individual wafers 1
Is transported in the inverted state and is set on the boat 3 with the back surface 1r facing upward. Due to the thermal deformation generated in the first heat treatment step, the back surface 1r side of the wafer 1 has a convex shape. When the second heat treatment step is performed with the convex back surface facing upward, the convex shape is returned to the flat shape by the action of gravity.

【0010】図2は本発明の実施に用いられるボートの
一例を示す外観斜視図である。ボート3は所定の間隔を
介して上下に離間配置された一対の円板4,5と、両者
の間に連結された複数本(本例の場合4本)のポスト6
とから構成されている。材料としては例えば耐熱性に優
れ且つ高純度の石英ガラスが用いられる。個々のポスト
6の側壁部には所定のピッチをおいて溝が形成されてい
る。同一レベルの溝に対して個々のウェハの端部が係合
し水平に支持される。かかる構造を有するボートに保持
された個々のウェハを反転する場合には例えば単にボー
トを倒立させれば良い。
FIG. 2 is an external perspective view showing an example of a boat used for implementing the present invention. The boat 3 includes a pair of discs 4 and 5 vertically spaced apart from each other with a predetermined gap, and a plurality of posts (4 in this example) 6 connected between the discs.
It consists of and. As the material, for example, quartz glass having excellent heat resistance and high purity is used. Grooves are formed on the side wall of each post 6 at a predetermined pitch. The edges of the individual wafers are engaged with and horizontally supported by the grooves of the same level. When reversing the individual wafers held in the boat having such a structure, the boat may be simply inverted.

【0011】図3は図2に示したボートの平面形状を示
す。複数本のポスト6は円板4の周方向に沿って所定の
間隔を介して配置されている。但し、一方向側において
隣り合うポストの間隔が拡大しておりウェハ1の装着を
可能にしている。ウェハ1の端部は個々のポスト6に形
成された溝2によって点支持されている。
FIG. 3 shows a plan view of the boat shown in FIG. The plurality of posts 6 are arranged along the circumferential direction of the disc 4 with a predetermined interval. However, the interval between the posts that are adjacent to each other on one side is enlarged, so that the wafer 1 can be mounted. The ends of the wafer 1 are point-supported by the grooves 2 formed in the individual posts 6.

【0012】図4に本発明の実施に使用される縦型熱処
理装置の一例を示す。下端を開口し上方に伸びる有底筒
状の石英反応管7にはガス供給管8が設けられている。
個々のウェハ1はボート3に所定ピッチで離間した状態
で水平保持され、保温筒9を介して搬送される。反応管
7の開口部は、ボート3が内部に完全に挿入された時、
保温筒9に固着したキャップ10で密封される様になっ
ている。反応管7の周囲にはヒータ11が設けられてお
り雰囲気温度を高温に維持する。この熱処理装置を用い
て例えば熱酸化処理を行なう場合には、反応管7の内部
を例えば1000℃の高温雰囲気に保ったままガス供給
管8からプロセスガスを導入して所定の反応時間だけ保
持する。
FIG. 4 shows an example of a vertical heat treatment apparatus used for carrying out the present invention. A gas supply pipe 8 is provided in a bottomed cylindrical quartz reaction tube 7 that opens at the lower end and extends upward.
The individual wafers 1 are horizontally held on the boat 3 in a state of being separated from each other at a predetermined pitch, and are conveyed through the heat retaining cylinder 9. When the boat 3 is completely inserted inside, the opening of the reaction tube 7 is
It is adapted to be sealed by a cap 10 fixed to the heat retaining cylinder 9. A heater 11 is provided around the reaction tube 7 to maintain the ambient temperature at a high temperature. For example, when performing thermal oxidation treatment using this heat treatment apparatus, the process gas is introduced from the gas supply pipe 8 while maintaining the inside of the reaction tube 7 at a high temperature atmosphere of, for example, 1000 ° C. and maintained for a predetermined reaction time. ..

【0013】再び図1に戻って本発明にかかる基板熱処
理方法の具体例を説明する。この例では直径150mmの
丸型石英ガラスウェハの表面に形成された多結晶シリコ
ン薄膜に対してトランジスタを形成した。特に、トラン
ジスタのゲート絶縁膜として耐圧性に優れた二酸化シリ
コン/窒化シリコン/二酸化シリコンのONO積層構造
を形成した。この工程で第1の熱処理及び第2の熱処理
を施した。第1の熱処理はウェハ1の表面1fを上に向
けた姿勢で行なわれ、多結晶シリコン薄膜の表面を熱酸
化し3層構造ゲート絶縁膜の第1層目を形成した。この
熱酸化処理は1000℃の温度で60分間行なった。こ
の後ゲート絶縁膜の第2層目を形成する為に窒化シリコ
ンをLP−CVDで成膜積層した。
Referring back to FIG. 1, a specific example of the substrate heat treatment method according to the present invention will be described. In this example, a transistor was formed on a polycrystalline silicon thin film formed on the surface of a round quartz glass wafer having a diameter of 150 mm. In particular, an ONO laminated structure of silicon dioxide / silicon nitride / silicon dioxide having excellent pressure resistance was formed as a gate insulating film of a transistor. In this step, the first heat treatment and the second heat treatment were performed. The first heat treatment was performed with the surface 1f of the wafer 1 facing upward, and the surface of the polycrystalline silicon thin film was thermally oxidized to form the first layer of the three-layer structure gate insulating film. This thermal oxidation treatment was performed at a temperature of 1000 ° C. for 60 minutes. Thereafter, silicon nitride was deposited and laminated by LP-CVD to form a second layer of the gate insulating film.

【0014】続いて第2の熱処理を行ない窒化シリコン
の表面を熱酸化しゲート絶縁膜の第3層目とした。第2
の熱処理はウェハ1の裏面1rを上に向けた姿勢で行な
われ、1000℃で60分間加熱した。不純物のドーピ
ング、ゲート電極の形成等その他の工程は全て1000
℃以下の処理温度で行ない多結晶シリコンの薄膜トラン
ジスタを基板上に形成した。
Subsequently, a second heat treatment was performed to thermally oxidize the surface of silicon nitride to form a third layer of the gate insulating film. Second
The heat treatment was performed with the back surface 1r of the wafer 1 facing upward, and the wafer 1 was heated at 1000 ° C. for 60 minutes. All other processes such as impurity doping and gate electrode formation are 1000
A thin film transistor of polycrystalline silicon was formed on the substrate by performing the treatment at a processing temperature of ℃ or less.

【0015】本発明の評価を行なう為に、上述の方法に
より製造された薄膜素子基板の反り量を測定した。図5
に示す様に、この測定は触針法により行ない130mmの
スパンに渡ってウェハ1の表面をスキャニングした時の
高さの差を反り量として検出した。この測定結果によれ
ば、第1の熱処理工程前でウェハ反り量は約12μmで
あった。第1の熱処理工程後には反り量は約40μmに
増大した。さらに、第2の熱処理工程後では反り量が約
15μmに減少しウェハは略初期状態に復帰した。この
場合、工程中における搬送トラブルもなく、作成した薄
膜トランジスタのVth特性も同一ウェハ面内において
約1V以内のばらつきに納まり素子の電気特性不良も発
生しなかった。
In order to evaluate the present invention, the amount of warpage of the thin film element substrate manufactured by the above method was measured. Figure 5
As shown in, the measurement was performed by the stylus method, and the difference in height when the surface of the wafer 1 was scanned over a span of 130 mm was detected as the amount of warpage. According to this measurement result, the wafer warp amount was about 12 μm before the first heat treatment step. After the first heat treatment step, the warp amount increased to about 40 μm. Further, after the second heat treatment step, the amount of warp was reduced to about 15 μm, and the wafer returned to the initial state. In this case, there was no transportation trouble during the process, and the Vth characteristics of the thin film transistor thus produced were within a range of about 1 V within the same wafer surface, and no defective electrical characteristics of the element occurred.

【0016】一方、比較例としてウェハの反転を行なわ
ずに第1の熱処理工程及び第2の熱処理工程を行ない薄
膜素子基板を作成した。即ち、この比較例では第1の熱
処理工程及び第2の熱処理工程のいずれにおいてもウェ
ハ1の表面1fを上に向けた姿勢でボート3にセットさ
れている。その他の加工条件及び処理条件については先
に説明した本発明の具体例と同様である。ウェハの熱変
形の程度を測定したところ、第1の熱処理工程前で反り
量は約12μmであり、第1の熱処理工程後反り量は約
40μmに増大し、第2の熱処理工程後ではさらに約8
0μmまで増大し且つ個々のウェハによりばらつきが顕
著であった。第2の熱処理工程後では石英ガラスウェハ
の反り量のばらつきにより、約10枚に1枚の割合で搬
送トラブルが発生し、作成した薄膜トランジスタのVt
h特性も同一ウェハ面内において約3V程度のばらつき
が発生した。
On the other hand, as a comparative example, a thin film element substrate was prepared by performing the first heat treatment step and the second heat treatment step without inverting the wafer. That is, in this comparative example, in both the first heat treatment step and the second heat treatment step, the wafer 1 is set on the boat 3 with the surface 1f facing upward. Other processing conditions and processing conditions are the same as those of the specific example of the present invention described above. When the degree of thermal deformation of the wafer was measured, the amount of warpage was about 12 μm before the first heat treatment process, the amount of warpage after the first heat treatment process was increased to about 40 μm, and it was further increased after the second heat treatment process. 8
It increased to 0 μm and the variation was significant depending on the individual wafer. After the second heat treatment step, due to the variation in the amount of warpage of the quartz glass wafer, a transport trouble occurred at a rate of about 1 in 10, and the Vt of the formed thin film transistor was reduced.
As for the h characteristic, a variation of about 3 V occurred within the same wafer surface.

【0017】本発明にかかる基板熱処理方法の他の具体
例を説明する。この具体例では第1の熱処理工程で多結
晶シリコン薄膜の表面を熱酸化し単層のゲート絶縁膜を
形成した。この熱酸化処理は1000℃で60分間行な
った。第1の熱処理工程ではウェハ1の表面1fが上に
向いた姿勢でボートにセットされている。この後、成膜
されたゲート絶縁膜を介して多結晶シリコン薄膜に不純
物を注入した。
Another specific example of the substrate heat treatment method according to the present invention will be described. In this specific example, the surface of the polycrystalline silicon thin film was thermally oxidized in the first heat treatment step to form a single-layer gate insulating film. This thermal oxidation treatment was performed at 1000 ° C. for 60 minutes. In the first heat treatment step, the front surface 1f of the wafer 1 is set on the boat with its posture facing upward. After that, impurities were injected into the polycrystalline silicon thin film through the formed gate insulating film.

【0018】続いて、第2の熱処理工程では1000℃
で30分間のアニールを行ない注入された不純物を活性
化した。第2の熱処理工程では石英ガラスウェハ1の裏
面1rを上に向けた姿勢でボート3にセットした。ゲー
ト絶縁膜形成工程及び不純物活性化工程の他は全て10
00℃以下の処理温度で加工を行ない、ゲート構造が酸
化シリコン膜単層の多結晶シリコン薄膜トランジスタを
形成した。
Subsequently, in the second heat treatment step, 1000 ° C.
The implanted impurities were activated by annealing for 30 minutes. In the second heat treatment step, the back surface 1r of the quartz glass wafer 1 was set on the boat 3 with its posture facing upward. 10 except for the gate insulating film forming step and the impurity activating step
Processing was performed at a processing temperature of 00 ° C. or lower to form a polycrystalline silicon thin film transistor having a gate oxide silicon oxide film single layer.

【0019】前記と同様にウェハの熱変形量を測定した
ところ、第1の熱処理工程前では反りは約12μmであ
った。第1の熱処理工程後反り量は約40μmまで増大
した。第2の熱処理工程後においては反り量は約15μ
mまで減少しウェハは略初期状態に復帰した。この場
合、工程中における搬送トラブルもなく、作成した薄膜
トランジスタのVth特性も同一ウェハ面内において約
1V以内のばらつきで納まり素子特性不良も発生しなか
った。
When the amount of thermal deformation of the wafer was measured in the same manner as above, the warpage was about 12 μm before the first heat treatment step. The warp amount after the first heat treatment step increased to about 40 μm. After the second heat treatment step, the warp amount is about 15 μ
The wafer was returned to a substantially initial state after the reduction to m. In this case, there was no transportation trouble during the process, and the Vth characteristics of the thin film transistor thus produced were within 1 V within the same wafer surface, and the device characteristic failure did not occur.

【0020】さらに比較例として、ウェハの反転を行な
う事なく上述した第1の熱処理工程及び第2の熱処理工
程を施し多結晶シリコン薄膜トランジスタを作成した。
その他の加工処理条件については上述した具体例と同様
である。石英ガラスウェハの熱変形程度を測定したとこ
ろ、第1の熱処理工程前では約12μmであった。第1
の熱処理工程後反り量は約40μmまで増大し、さらに
第2の熱処理工程後では約80μmまで増大し且つ個々
のウェハでばらつきが顕著であった。第2の熱処理工程
後では、石英ガラスウェハの反り量のばらつきにより約
10枚に1枚の割合で搬送トラブルが発生し、作成した
薄膜トランジスタのVth特性も同一ウェハ面内におい
て約3V程度ばらつきが生じた。
Further, as a comparative example, a polycrystalline silicon thin film transistor was produced by performing the above-mentioned first heat treatment step and second heat treatment step without performing wafer inversion.
Other processing conditions are the same as those of the above-described specific example. When the degree of thermal deformation of the quartz glass wafer was measured, it was about 12 μm before the first heat treatment step. First
After the heat treatment step, the amount of warp increased to about 40 μm, and after the second heat treatment step, it increased to about 80 μm, and the variation was remarkable among individual wafers. After the second heat treatment step, a transport trouble occurs at a rate of about 1 in 10 due to variations in the amount of warpage of the quartz glass wafer, and the Vth characteristics of the created thin film transistors also vary by about 3 V within the same wafer surface. It was

【0021】なお、上述した各具体例において、第1の
熱処理工程と第2の熱処理工程との間でウェハを裏返す
場合、同時に基板の平面方向姿勢を回転変化させても良
い。これにより、平面姿勢に依存する熱反り変形も相殺
もしくは補償する事が可能になる。
In each of the specific examples described above, when the wafer is turned over between the first heat treatment step and the second heat treatment step, the plane orientation of the substrate may be simultaneously changed by rotation. Thereby, it becomes possible to cancel or compensate the thermal warp deformation depending on the plane posture.

【0022】又、上述した具体例においてはウェハとし
て石英ガラス材料を用いたが本発明はこれに限られるも
のではなく、熱処理温度に併せて様々な種類のガラス板
材料を用いる事ができる。さらにはガラス材料に限ら
ず、他のセラミック等の絶縁基板や金属基板等の加工に
ついても、縦型熱処理装置を用いた場合には基板の自重
による反りの抑制に効果的である事は明らかである。
Further, although the quartz glass material is used as the wafer in the above-mentioned specific examples, the present invention is not limited to this, and various kinds of glass plate materials can be used depending on the heat treatment temperature. Furthermore, it is clear that not only the glass material but also the processing of other insulating substrates such as ceramics and metal substrates is effective in suppressing the warp due to the weight of the substrate when the vertical heat treatment apparatus is used. is there.

【0023】又、上述の具体例においては多結晶シリコ
ンの薄膜トランジスタ素子を形成したが本発明はこれに
限られるものではなく、アモルファスシリコンやCdS
e等の半導体薄膜素子を初め、MIM素子や、プラズマ
ディスプレイやELディスプレイやラインセンサ等に使
われる薄膜素子を形成する場合においても有用である。
Further, although the thin film transistor element made of polycrystalline silicon is formed in the above-mentioned embodiment, the present invention is not limited to this, and amorphous silicon or CdS is used.
It is also useful when forming a semiconductor thin film element such as e, an MIM element, or a thin film element used in a plasma display, an EL display, a line sensor, or the like.

【0024】[0024]

【発明の効果】以上説明した様に、本発明によれば、基
板の端部だけを支えて水平に保持した状態で加工を行な
う縦型の熱処理装置を使用する場合、基板の表側を上に
向けた姿勢で熱処理する工程と基板の裏側を上に向けた
姿勢で熱処理する工程の両方を行なう。この為、両工程
の間で基板の自重による反りの発生方向が逆になりお互
いの熱変形が相殺もしくは補償され反りの累積を防止す
る事ができるという効果がある。本発明によれば、各工
程で熱処理を繰り返し行なっても反りが累積されず基板
を初期の平坦な形状に略近く維持する事ができる。かか
る方法により、歪点の高い高価な基板材料を使う必要が
なくなり、反りも抑制できる為高収率で薄膜素子基板を
生産する事が可能になるという効果がある。
As described above, according to the present invention, when a vertical heat treatment apparatus for supporting a substrate and holding it horizontally is used, the front side of the substrate is placed upward. Both the heat treatment step in which the substrate is oriented and the heat treatment step in which the backside of the substrate is oriented upward are performed. For this reason, the warp generation direction due to the weight of the substrate is reversed between the both steps, and the mutual thermal deformations are canceled or compensated, so that the accumulation of the warp can be prevented. According to the present invention, the warp is not accumulated even if the heat treatment is repeatedly performed in each step, and the substrate can be maintained close to the initial flat shape. With this method, it is not necessary to use an expensive substrate material having a high strain point, and since warpage can be suppressed, it is possible to produce a thin film element substrate with a high yield.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明にかかる基板熱処理方法の基本的な概念
を示す模式図である。
FIG. 1 is a schematic diagram showing the basic concept of a substrate heat treatment method according to the present invention.

【図2】本発明の実施に用いられる縦型配置のボートを
示す斜視図である。
FIG. 2 is a perspective view showing a boat in a vertical arrangement used for implementing the present invention.

【図3】同じくボートの平面図である。FIG. 3 is also a plan view of the boat.

【図4】本発明の実施に用いられる縦型熱処理装置の一
例を示す模式図である。
FIG. 4 is a schematic view showing an example of a vertical heat treatment apparatus used for carrying out the present invention.

【図5】基板の反り量の測定原理図である。FIG. 5 is a principle diagram of measuring the amount of warpage of a substrate.

【符号の説明】[Explanation of symbols]

1 ウェハ 1f ウェハ表面 1r ウェハ裏面 2 溝 3 ボート 6 ポスト 7 反応管 8 ガス導入管 11 ヒータ 1 Wafer 1f Wafer front surface 1r Wafer back surface 2 Groove 3 Boat 6 Post 7 Reaction tube 8 Gas introduction tube 11 Heater

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基板を所定のピッチで水平に保持したボ
ートを反応管の内部に挿入して熱処理を行なう縦型の熱
処理装置で基板を少なくとも2回以上熱処理する基板熱
処理方法において、 前記基板の熱処理面を上に向けて処理する第1の熱処理
工程と、前記熱処理面を下に向けて処理する第2の熱処
理工程とを有する事を特徴とする基板熱処理方法。
1. A substrate heat treatment method for heat treating a substrate at least twice in a vertical heat treatment apparatus in which a boat holding a substrate horizontally at a predetermined pitch is inserted into a reaction tube for heat treatment. A substrate heat treatment method comprising: a first heat treatment step of treating the heat treatment surface facing upward; and a second heat treatment step of treating the heat treatment surface facing downward.
JP11409592A 1992-04-07 1992-04-07 Substrate heat treatment method Expired - Lifetime JP3158307B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11409592A JP3158307B2 (en) 1992-04-07 1992-04-07 Substrate heat treatment method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11409592A JP3158307B2 (en) 1992-04-07 1992-04-07 Substrate heat treatment method

Publications (2)

Publication Number Publication Date
JPH05291163A true JPH05291163A (en) 1993-11-05
JP3158307B2 JP3158307B2 (en) 2001-04-23

Family

ID=14628989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11409592A Expired - Lifetime JP3158307B2 (en) 1992-04-07 1992-04-07 Substrate heat treatment method

Country Status (1)

Country Link
JP (1) JP3158307B2 (en)

Also Published As

Publication number Publication date
JP3158307B2 (en) 2001-04-23

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