JPH0529114A - Surge absorber - Google Patents
Surge absorberInfo
- Publication number
- JPH0529114A JPH0529114A JP20739091A JP20739091A JPH0529114A JP H0529114 A JPH0529114 A JP H0529114A JP 20739091 A JP20739091 A JP 20739091A JP 20739091 A JP20739091 A JP 20739091A JP H0529114 A JPH0529114 A JP H0529114A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- varistor
- surge
- substrate
- resistance element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Thermistors And Varistors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、サージ吸収部品、更
に詳しくは、外来の電圧サージと電流サージを共に抑制
することができると共に、通常の信号伝送には支障をお
よぼさないようにしたサージ吸収部品に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surge absorbing component, and more specifically, it can suppress both an external voltage surge and a current surge and does not hinder normal signal transmission. The present invention relates to surge absorbing parts.
【０００２】[0002]
【従来の技術】信号ラインに侵入する外来サージ対策と
して、図７に示すように、信号ラインＡ−Ａ′に一般の
バリスタ素子１を取付けた場合、電圧サージＶは、バリ
スタ素子１によって抑制することができるものの電流サ
ージＩは抑制できないという欠点がある。2. Description of the Related Art As a measure against an external surge entering a signal line, when a general varistor element 1 is attached to a signal line AA 'as shown in FIG. 7, the voltage surge V is suppressed by the varistor element 1. However, there is a drawback that the current surge I cannot be suppressed.
【０００３】そこで、電圧サージだけでなく電流サージ
をも抑制するために、図８に示すように、抵抗内蔵の三
端子サージ吸収部品が提案されている。Therefore, in order to suppress not only the voltage surge but also the current surge, a three-terminal surge absorbing component with a built-in resistor has been proposed as shown in FIG.
【０００４】このサージ吸収部品は、図８(a) に示すよ
うに、バリスタ基板２の表面に入力電極３と出力電極４
を分割して設け、この入力電極３と出力電極４間に抵抗
素子５を取付けると共に、図８(b) のように、バリスタ
基板２の裏面側に、上記入力電極３および出力電極４と
バリスタ基板２を挾んで相対向する大きさのアース電極
６を設け、入力電極３と出力電極４およびアース電極６
の各々にリード端子７，８，９を接続した構造になって
いる。In this surge absorbing component, as shown in FIG. 8 (a), the input electrode 3 and the output electrode 4 are formed on the surface of the varistor substrate 2.
And the resistance element 5 is mounted between the input electrode 3 and the output electrode 4, and the input electrode 3 and the output electrode 4 and the varistor 4 are provided on the back side of the varistor substrate 2 as shown in FIG. 8 (b). A ground electrode 6 having a size facing each other across the substrate 2 is provided, and the input electrode 3, the output electrode 4 and the ground electrode 6 are provided.
The lead terminals 7, 8 and 9 are connected to each of the above.
【０００５】[0005]
【発明が解決しようとする課題】ところで上記した従来
のサージ吸収部品は、アース電極６が入力電極３及び出
力電極４の両者にわたって対向するように設けられてい
るため、図９の等価回路に示すように、抵抗素子５を挾
んで二個のバリスタ素子１０，１１が存在することにな
り、これにより出力電極４側のバリスタ素子１１が持つ
静電容量Ｃ2 と抵抗素子５の抵抗値Ｒの時定数により、
図１０に示したように、信号ラインを伝送させたい信号
波形が弱るか伝送できなくなるという問題がある。By the way, in the above-mentioned conventional surge absorbing component, the ground electrode 6 is provided so as to face both the input electrode 3 and the output electrode 4, and therefore, the equivalent circuit of FIG. 9 is shown. Thus, there are two varistor elements 10 and 11 sandwiching the resistance element 5, whereby the capacitance C 2 of the varistor element 11 on the output electrode 4 side and the resistance value R of the resistance element 5 are Depending on the time constant,
As shown in FIG. 10, there is a problem that the signal waveform desired to be transmitted through the signal line is weakened or cannot be transmitted.
【０００６】そこで、この発明は、上記のような問題点
を解決するため、電圧サージと電流サージを共に除去で
きると共に、信号の伝送には支障を与えることのないサ
ージ吸収部品を提供することを目的とする。In order to solve the above problems, the present invention provides a surge absorbing component that can remove both voltage surge and current surge and does not hinder signal transmission. To aim.
【０００７】[0007]
【課題を解決するための手段】上記のような課題を解決
するため、この発明は、バリスタ基板の一面側に、複数
に分割された電極と、分割された電極間に位置する抵抗
素子とを設け、前記バリスタ基板の他面側に、分割され
た電極の一方電極のみと、バリスタ基板を挾んで相対向
する電極を設けた構成を採用したものである。In order to solve the above problems, the present invention provides a plurality of divided electrodes and a resistance element located between the divided electrodes on one side of a varistor substrate. A structure is provided in which only one electrode of the divided electrodes and an electrode facing each other across the varistor substrate are provided on the other surface side of the varistor substrate.
【０００８】[0008]
【作用】バリスタ基板の一面側に複数に分割された電極
と、分割された電極間に位置する抵抗素子を設け、バリ
スタ基板の他面側に分割された一方電極のみと相対向す
る電極を設けたので、対向する電極によって形成された
一つのバリスタ素子と抵抗素子を有するサージ吸収部品
となり、電圧サージと電流サージを共に吸収できると共
に、抵抗素子と連なる出力電極側にはバリスタ素子によ
る容量の発生がなく、通常の信号伝送には支障を与える
ことがない。A plurality of divided electrodes and a resistance element located between the divided electrodes are provided on one surface side of the varistor substrate, and an electrode opposed to only one electrode is provided on the other surface side of the varistor substrate. Therefore, it becomes a surge absorbing component that has one varistor element and resistance element formed by the opposing electrodes, can absorb both voltage surge and current surge, and the varistor element generates capacitance on the output electrode side connected to the resistance element. Therefore, it does not hinder normal signal transmission.
【０００９】[0009]
【実施例】以下、この発明の実施例を添付図面の図１乃
至図６に基づいて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
【００１０】図１に示す第１の実施例において、図１
(a) に示すようにバリスタ基板２１の表面に入力電極２
２と出力電極２３を両側に分割して設け、分割された入
力電極２２と出力電極２３間に抵抗素子２４が設けら
れ、入力電極２２には入力端子２５が、出力電極２３に
は出力端子２６が各々接続されている。In the first embodiment shown in FIG.
As shown in (a), the input electrode 2 is formed on the surface of the varistor substrate 21.
2 and the output electrode 23 are separately provided on both sides, and a resistance element 24 is provided between the divided input electrode 22 and output electrode 23. The input electrode 22 has an input terminal 25 and the output electrode 23 has an output terminal 26. Are connected to each other.
【００１１】前記バリスタ基板２１の裏面には図１(b)
のように、バリスタ基板２１を挾んで入力電極２２のみ
と相対向するアース電極２７を設け、このアース電極２
７にアース端子２８が接続されている。The back surface of the varistor substrate 21 is shown in FIG.
As described above, the ground electrode 27 is provided so as to face the input electrode 22 by sandwiching the varistor substrate 21.
A ground terminal 28 is connected to 7.
【００１２】上記した出力電極２３は、出力端子２６及
び抵抗素子２４を接続するだけのために用いられ、その
電極面積は入力電極２２に比べて小さく形成されている
と共に、アース電極２７は入力電極２２と相対向する面
積にアース端子２８を接続する部分を設けた大きさに形
成され、出力電極２３とは相対向していない。The above-mentioned output electrode 23 is used only for connecting the output terminal 26 and the resistance element 24, the electrode area thereof is formed smaller than that of the input electrode 22, and the ground electrode 27 is connected to the input electrode. It is formed in such a size that a portion for connecting the ground terminal 28 is provided in an area facing the electrode 22, and does not face the output electrode 23.
【００１３】上記のような構造のサージ吸収部品は、バ
リスタ基板２１を挾んで入力電極２２とアース電極２７
が相対向し、出力電極２３は単独で独立しているため、
図２の等価回路で示すように、入力電極２２とアース電
極２７によって形成した一つのバリスタ素子２９と、抵
抗素子２４を有する構造になる。In the surge absorbing component having the above structure, the varistor substrate 21 is sandwiched between the input electrode 22 and the ground electrode 27.
Face each other and the output electrodes 23 are independent of each other,
As shown in the equivalent circuit of FIG. 2, the structure has one varistor element 29 formed by the input electrode 22 and the ground electrode 27, and the resistance element 24.
【００１４】次に図３(a) ，(b) に示す第２の実施例
は、第１の実施例に比べてアース電極２７の面積を小さ
くし、アース端子２８を入力端子２５に接近させるよう
にしたものである。Next, in the second embodiment shown in FIGS. 3A and 3B, the area of the ground electrode 27 is made smaller than that of the first embodiment, and the ground terminal 28 is brought closer to the input terminal 25. It was done like this.
【００１５】このようにすることにより、アース電極２
７のオフセット量を増やし、アース電極２７と出力電極
２３の間に発生しがちなストレー容量を小さくすること
ができ、更に端子２５，２８間と端子２６，２８間の間
隔が相違することにより部品に方向性が生じ、誤接続を
防ぐことができる。By doing so, the ground electrode 2
7 can be increased to reduce the stray capacitance that tends to occur between the earth electrode 27 and the output electrode 23, and the gap between the terminals 25 and 28 and the gap between the terminals 26 and 28 can be made different from each other. Directionality can be generated, and incorrect connection can be prevented.
【００１６】図４(a) ，(b) に示す第３の実施例は、入
力電極２２の上部に延長部２２ａを設け、この延長部２
２ａの下方位置に分離して設けた出力電極２３と上記延
長部２２ａの間に抵抗素子２４を設けたものである。In the third embodiment shown in FIGS. 4 (a) and 4 (b), an extension 22a is provided on the upper portion of the input electrode 22, and the extension 2
A resistance element 24 is provided between the output electrode 23 and the extension portion 22a which are separately provided at a position below 2a.
【００１７】図５(a) ，(b) に示す第４の実施例は、入
力電極２２に延長部２２ａを設け、この延長部２２ａに
チップ抵抗素子２４ａを接続し、出力電極として、チッ
プ抵抗素子２４ａの外部電極２４ｂを代用したものであ
り、バリスタ基板２１の表面に出力電極がないので、ア
ース端子２８と出力端子２６間のストレー容量がなくな
る。In the fourth embodiment shown in FIGS. 5 (a) and 5 (b), the input electrode 22 is provided with an extension portion 22a, and a chip resistance element 24a is connected to this extension portion 22a, and a chip resistance is used as an output electrode. This is a substitute for the external electrode 24b of the element 24a, and since there is no output electrode on the surface of the varistor substrate 21, there is no stray capacitance between the ground terminal 28 and the output terminal 26.
【００１８】図６(a) ，(b) に示す第５の実施例は、バ
リスタ基板２１の表面に、抵抗用材料をペースト塗布
し、焼付けて形成した抵抗素子２４ｃを設けたものであ
る。この抵抗素子２４ｃの一方端部は入力電極２２に重
なっており、他方端部には同じく塗布、焼付等により形
成された出力電極２３が設けられ、この出力電極２３に
出力端子２６が接続している。In the fifth embodiment shown in FIGS. 6 (a) and 6 (b), a resistor element 24c formed by paste-applying and baking a resistor material on the surface of the varistor substrate 21 is provided. One end of the resistance element 24c overlaps the input electrode 22, and the other end of the resistance element 24c is provided with an output electrode 23 also formed by coating, baking, etc., and an output terminal 26 is connected to the output electrode 23. There is.
【００１９】なお、第２実施例乃至第５実施例において
も図３で示した等価回路になると共に、何れの実施例
も、用いるバリスタ基板２１の組成、各電極の材質及び
形成方法、抵抗素子の種類と形成方法は自由に選択すれ
ばよい。In the second to fifth embodiments, the equivalent circuit shown in FIG. 3 is obtained, and in any of the embodiments, the composition of the varistor substrate 21 used, the material and forming method of each electrode, the resistance element are used. The type and the forming method of the may be freely selected.
【００２０】この発明のサージ吸収部品は、上記のよう
な構成であり、バリスタ基板に一つのバリスタ素子と、
抵抗素子を設けた構造になり、電圧サージと電流サージ
を共に除去して内部回路の保護を図ると共に、バリスタ
素子が持つ静電容量によって伝送させたい信号波形を弱
めることがなく通常の信号伝送に支障を及ぼさない。The surge absorbing component of the present invention has the above-mentioned structure, and one varistor element is provided on the varistor substrate.
It has a structure with a resistance element, removes both voltage surge and current surge to protect the internal circuit, and it can be used for normal signal transmission without weakening the signal waveform to be transmitted due to the capacitance of the varistor element. It does not hinder.
【００２１】[0021]
【効果】以上のように、この発明によると、信号ライン
に侵入する電圧サージと電流サージを共に除去すること
ができると同時に信号の伝送には支障を与えることがな
いという効果がある。As described above, according to the present invention, it is possible to remove both the voltage surge and the current surge that enter the signal line, and at the same time, the signal transmission is not hindered.
【図１】(a) はこの発明に係るサージ吸収部品の第１の
実施例を示す正面図、(b) はその背面図である。FIG. 1A is a front view showing a first embodiment of a surge absorbing component according to the present invention, and FIG. 1B is a rear view thereof.
【図２】この発明に係るサージ吸収部品の第１の実施例
の等価回路図である。FIG. 2 is an equivalent circuit diagram of the first embodiment of the surge absorbing component according to the present invention.
【図３】(a) はこの発明に係るサージ吸収部品の第２の
実施例を示す正面図、(b) はその背面図である。3 (a) is a front view showing a second embodiment of the surge absorbing component according to the present invention, and FIG. 3 (b) is a rear view thereof.
【図４】(a) はこの発明に係るサージ吸収部品の第３の
実施例を示す正面図、(b) はその背面図である。FIG. 4 (a) is a front view showing a third embodiment of the surge absorbing component according to the present invention, and FIG. 4 (b) is a rear view thereof.
【図５】(a) はこの発明に係るサージ吸収部品の第４の
実施例を示す正面図、(b) はその背面図である。5A is a front view showing a fourth embodiment of a surge absorbing component according to the present invention, and FIG. 5B is a rear view thereof.
【図６】(a) はこの発明に係るサージ吸収部品の第５の
実施例を示す正面図、(b) はその背面図である。6 (a) is a front view showing a fifth embodiment of the surge absorbing component according to the present invention, and FIG. 6 (b) is a rear view thereof.
【図７】従来の電圧サージ吸収を行なう回路図である。FIG. 7 is a circuit diagram for performing conventional voltage surge absorption.
【図８】(a) は従来のサージ吸収部品を示す正面図、
(b) はその背面図である。FIG. 8 (a) is a front view showing a conventional surge absorbing component,
(b) is the rear view.
【図９】従来のサージ吸収部品の等価回路図である。FIG. 9 is an equivalent circuit diagram of a conventional surge absorbing component.
【図１０】信号波形の変化を示す説明図である。FIG. 10 is an explanatory diagram showing changes in signal waveform.
２１ 絶縁基板 ２２ 入力電極 ２３ 出力電極 ２４ 抵抗素子 ２５ 入力端子 ２６ 出力端子 ２７ アース電極 ２８ アース端子 21 Insulating Substrate 22 Input Electrode 23 Output Electrode 24 Resistance Element 25 Input Terminal 26 Output Terminal 27 Ground Electrode 28 Ground Terminal
───────────────────────────────────────────────────── フロントページの続き (72)発明者 上山 昌則 京都府長岡京市天神二丁目26番10号 株式 会社村田製作所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masanori Ueyama 2 26-10 Tenjin Tenjin, Nagaokakyo, Kyoto Prefecture Murata Manufacturing Co., Ltd.
Claims (1)
た電極と、分割された電極間に位置する抵抗素子とを設
け、前記バリスタ基板の他面側に、分割された電極の一
方電極のみとバリスタ基板を挾んで相対向する電極を設
けたサージ吸収部品。Claim: What is claimed is: 1. A plurality of divided electrodes and a resistance element located between the divided electrodes are provided on one surface side of the varistor substrate, and are divided on the other surface side of the varistor substrate. A surge absorbing component that has only one electrode and the opposite electrode sandwiching the varistor substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3207390A JP2624042B2 (en) | 1991-07-23 | 1991-07-23 | Surge absorbing parts |
| US07/913,956 US5386335A (en) | 1991-07-18 | 1992-07-17 | Surge absorber |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3207390A JP2624042B2 (en) | 1991-07-23 | 1991-07-23 | Surge absorbing parts |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0529114A true JPH0529114A (en) | 1993-02-05 |
| JP2624042B2 JP2624042B2 (en) | 1997-06-25 |
Family
ID=16538951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3207390A Expired - Lifetime JP2624042B2 (en) | 1991-07-18 | 1991-07-23 | Surge absorbing parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2624042B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1538487A2 (en) | 2003-09-10 | 2005-06-08 | Seiko Epson Corporation | Developing device, image forming apparatus, computer system, and seal-assisting member |
| JP2005277362A (en) * | 2003-10-01 | 2005-10-06 | Mitsubishi Materials Corp | Compound element |
| US7855631B2 (en) | 2004-05-18 | 2010-12-21 | Mitsubishi Materials Corporation | Composite device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5899803U (en) * | 1981-12-26 | 1983-07-07 | 松下電器産業株式会社 | Composite constant voltage parts |
-
1991
- 1991-07-23 JP JP3207390A patent/JP2624042B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5899803U (en) * | 1981-12-26 | 1983-07-07 | 松下電器産業株式会社 | Composite constant voltage parts |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1538487A2 (en) | 2003-09-10 | 2005-06-08 | Seiko Epson Corporation | Developing device, image forming apparatus, computer system, and seal-assisting member |
| US7076185B2 (en) | 2003-09-10 | 2006-07-11 | Seiko Epson Corporation | Developing device, image forming apparatus, computer system, and seal-assisting member |
| JP2005277362A (en) * | 2003-10-01 | 2005-10-06 | Mitsubishi Materials Corp | Compound element |
| US7855631B2 (en) | 2004-05-18 | 2010-12-21 | Mitsubishi Materials Corporation | Composite device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2624042B2 (en) | 1997-06-25 |
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