JPH05289635A - Liquid crystal display device - Google Patents

Liquid crystal display device

Info

Publication number
JPH05289635A
JPH05289635A JP9431692A JP9431692A JPH05289635A JP H05289635 A JPH05289635 A JP H05289635A JP 9431692 A JP9431692 A JP 9431692A JP 9431692 A JP9431692 A JP 9431692A JP H05289635 A JPH05289635 A JP H05289635A
Authority
JP
Japan
Prior art keywords
liquid crystal
display device
crystal display
channel mos
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9431692A
Other languages
Japanese (ja)
Inventor
Katsumi Watanabe
克己 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP9431692A priority Critical patent/JPH05289635A/en
Publication of JPH05289635A publication Critical patent/JPH05289635A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136213Storage capacitors associated with the pixel electrode
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/13624Active matrix addressed cells having more than one switching element per pixel

Landscapes

  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

PURPOSE:To provide the liquid crystal display device which adjust the quantity of variation in pixel voltage and then adjust variation in hue by adjusting pixel capacity to an optimum value. CONSTITUTION:This liquid crystal display device consists of (n) channel MOS transistors nTFT1 having their gate terminals connected to scanning lines X1, X2'... connected in series between signal lines Y1, Y2... and a common power source for a common potential VCOM, liquid crystal capacitors CLC, and series circuits of (n) channel MOS transistors nTFT2 connected in parallel to the liquid crystal capacitors CLC and auxiliary capacitors CS2 for adjustment.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は画素容量を調整すること
ができる液晶表示装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device capable of adjusting pixel capacitance.

【0002】[0002]

【従来の技術】図4は従来のアクティブマトリックスT
FT液晶表示装置の表示駆動素子マトリックス回路部を
示す回路図である。即ち、信号線駆動回路部に接続され
た信号線Y1,Y2………と共通電位VCOM の共通電源
との間にはnチャネルMOSトランジスタnTFT及び
液晶容量CLCが直列に接続され、この液晶容量CLCには
補助容量CS が並列に接続される。前記nチャネルMO
SトランジスタnTFTのゲート端子は走査線X1,X
2………に接続され、この走査線X1,X2………は走
査線駆動回路に接続される。
2. Description of the Related Art FIG. 4 shows a conventional active matrix T.
It is a circuit diagram which shows the display drive element matrix circuit part of an FT liquid crystal display device. That is, the n-channel MOS transistor nTFT and the liquid crystal capacitance C LC are connected in series between the signal lines Y1, Y2 ... Connected to the signal line drive circuit section and the common power source of the common potential V COM. An auxiliary capacitance C S is connected in parallel to the capacitance C LC . The n-channel MO
The gate terminals of the S-transistor nTFT are scanning lines X1 and X
2 ..., and these scanning lines X1, X2 ... Are connected to the scanning line driving circuit.

【0003】しかして、走査線駆動回路からのゲート電
圧VG を走査線X1,X2………に供給し、ゲート電圧
G がハイレベルの走査線に接続されたnチャネルMO
SトランジスタnTFTをオンして、信号線駆動回路部
から信号線Y1,Y2………に供給されている信号電圧
D を液晶容量CLC及び補助容量CS に蓄積する。
However, the gate voltage V G from the scanning line driving circuit is supplied to the scanning lines X1, X2 ..., And the n-channel MO connected to the scanning line whose gate voltage V G is at the high level.
The S-transistor nTFT is turned on, and the signal voltage V D supplied from the signal line drive circuit section to the signal lines Y1, Y2, ... Is accumulated in the liquid crystal capacitance C LC and the auxiliary capacitance C S.

【0004】図5は図4の1画素の等価回路を示す回路
図である。図5において、CGSはnチャネルMOSトラ
ンジスタnTFTのゲート・ソース間容量、RLCは液晶
抵抗であり、液晶容量CLC,補助容量CS 及び液晶抵抗
LCに画素電圧VP が加えられる。この画素電圧VP
nチャネルMOSトランジスタnTFTのゲート・ソー
ス間容量CGSにより信号電圧VD に対して ΔVP ={CGS/(CGS+CLC+CS )}・VG
FIG. 5 is a circuit diagram showing an equivalent circuit of one pixel in FIG. In FIG. 5, C GS is a gate-source capacitance of the n-channel MOS transistor nTFT, R LC is a liquid crystal resistance, and the pixel voltage V P is applied to the liquid crystal capacitance C LC , the auxiliary capacitance C S and the liquid crystal resistance R LC . This pixel voltage V P is ΔV P = {C GS / (C GS + C LC + C S )} · V G with respect to the signal voltage V D due to the gate-source capacitance C GS of the n-channel MOS transistor nTFT.

【0005】だけ変動する。このため、共通電源の共通
電位VCOM が印加される共通電極に、共通電位VCOM
り固定電圧ΔVP だけシフトした電圧を印加している。
It fluctuates only. Therefore, a voltage shifted by a fixed voltage ΔV P from the common potential V COM is applied to the common electrode to which the common potential V COM of the common power source is applied.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、液晶表
示装置の表示画面により、画面全体が明る過ぎたり、暗
過ぎたりすると、色調が赤や青の方に移行し、不自然な
色合いとなるが、シフト電圧ΔVP が固定されているの
で、このような場合の調整ができなかった。
However, depending on the display screen of the liquid crystal display device, if the entire screen is too bright or too dark, the color tone shifts to red or blue, resulting in an unnatural hue. Since the shift voltage ΔV P is fixed, adjustment in such a case could not be performed.

【0007】本発明は上記の実情に鑑みてなされたもの
で、画素容量を最適な値に調整することにより、画素電
圧の変動量を調整して色調の変化を調整し得る液晶表示
装置を提供することを目的とする。
The present invention has been made in view of the above circumstances, and provides a liquid crystal display device capable of adjusting a variation in pixel voltage to adjust a change in color tone by adjusting a pixel capacitance to an optimum value. The purpose is to do.

【0008】[0008]

【課題を解決するための手段】本発明は上記課題を解決
するために、走査線に制御端子が接続された第1のスイ
ッチング素子及び液晶容量を信号線と共通電源との間に
直列に接続した液晶表示装置において、第2のスイッチ
ング素子及び調整用補助容量よりなる直列回路を前記液
晶容量と並列に接続したものである。
In order to solve the above-mentioned problems, the present invention connects a first switching element having a control terminal connected to a scanning line and a liquid crystal capacitor in series between a signal line and a common power source. In the above liquid crystal display device, a series circuit including a second switching element and an adjusting auxiliary capacitance is connected in parallel with the liquid crystal capacitance.

【0009】[0009]

【作用】本発明は、液晶表示装置の表示画面の明暗に対
応してスイッチング素子をオン,オフ制御することによ
り、調整用補助容量を液晶容量と並列に接続したり、接
続しなかったりして画素容量を最適な値に調整し、画素
電圧の変動量を調整して色調の変化を調整することがで
き、正しい色調の自然な色合いとなるように調整するよ
うにしたものである。
The present invention controls the switching element to be turned on and off in accordance with the brightness of the display screen of the liquid crystal display device, thereby connecting or not connecting the adjustment auxiliary capacitor in parallel with the liquid crystal capacitor. The pixel capacitance is adjusted to an optimum value, the variation of the pixel voltage is adjusted to adjust the change of the color tone, and the adjustment is performed so that the natural color tone of the correct color tone is obtained.

【0010】[0010]

【実施例】以下図面を参照して本発明の実施例を詳細に
説明する。
Embodiments of the present invention will now be described in detail with reference to the drawings.

【0011】図3は本発明の一実施例に係るアクティブ
マトリックス液晶表示装置を示す概略ブロック図であ
る。即ち、表示駆動素子マトリックス回路部11は信号
線駆動回路部12及び走査線駆動回路部13により駆動
される。尚、これらの全ての回路は薄膜トランジスタに
より構成することができ、全ての回路を一枚の基板上に
形成することができる。
FIG. 3 is a schematic block diagram showing an active matrix liquid crystal display device according to an embodiment of the present invention. That is, the display driving element matrix circuit unit 11 is driven by the signal line driving circuit unit 12 and the scanning line driving circuit unit 13. Note that all of these circuits can be formed using thin film transistors and all the circuits can be formed over one substrate.

【0012】図1は図3の表示駆動素子マトリックス回
路部11の一例を示す回路図である。すなわち、信号線
駆動回路部12に接続された信号線Y1,Y2………と
共通電位VCOM の共通電源との間には第1のスイッチン
グ素子であるnチャネルMOSトランジスタnTFT1
及び液晶容量CLCが直列に接続され、この液晶容量CLC
には補助容量CS1、及び第2のスイッチング素子である
nチャネルMOSトランジスタnTFT2と調整用補助
容量CS2よりなる直列回路が並列に接続される。前記n
チャネルMOSトランジスタnTFT1のゲート端子は
走査線X1,X2………に接続され、この走査線X1,
X2………は走査線駆動回路部13に接続される。又、
前記nチャネルMOSトランジスタnTFT2のゲート
端子は制御用ゲート信号印加端子Tgに接続される。
FIG. 1 is a circuit diagram showing an example of the display drive element matrix circuit section 11 of FIG. That is, the n-channel MOS transistor nTFT1 which is the first switching element is provided between the signal lines Y1, Y2 ... Connected to the signal line drive circuit section 12 and the common power source of the common potential V COM.
And the liquid crystal capacitance C LC are connected in series, the liquid crystal capacitance C LC
A series circuit composed of an auxiliary capacitance C S1 and an n-channel MOS transistor nTFT2 that is a second switching element and an adjustment auxiliary capacitance C S2 is connected in parallel to the. N
The gate terminal of the channel MOS transistor nTFT1 is connected to the scanning lines X1, X2 ...
.. are connected to the scanning line drive circuit section 13. or,
The gate terminal of the n-channel MOS transistor nTFT2 is connected to the control gate signal application terminal Tg.

【0013】図2は本発明に係るアクティブマトリック
ス液晶表示パネルの一例を示す断面図である。即ち、下
ガラス基板21上には例えばAl等よりなるゲート電極
G1,G2が形成され、このゲート電極G1,G2及び
下ガラス基板21上には例えばSiO2 等の絶縁膜22
が形成される。この絶縁膜22上の前記ゲート電極G
1,G2に対応した位置にはシリコン活性層23が形成
される。又、前記絶縁膜22上には例えばAl等よりな
る画素電極ITOが形成され、前記絶縁膜22及びシリ
コン活性層23の一部にはドレイン電極D1,D2及び
ソース電極S1,S2が前記画素電極ITOに接続され
て形成される。前記絶縁膜22,画素電極ITO,シリ
コン活性層23,ドレイン電極D1,D2及びソース電
極S1,S2上には例えばSiO2 等の保護膜24が形
成され、この保護膜24上には例えばポリイミド等の配
向膜25が形成される。一方、上ガラス基板26上には
例えばクロム等の目隠し層27が形成され、この目隠し
層27及び上ガラス基板26上には例えばSiO2 等の
絶縁膜28が形成される。この絶縁膜28上には例えば
Al等よりなる共通電極29が形成され、この共通電極
29上には例えばポリイミド等の配向膜30が形成され
る。しかして、上ガラス基板26と下ガラス基板21を
配向膜30と配向膜25が対向するようにしてスペーサ
(図示せず)を介在して配置し、この配向膜30と配向
膜25の間に液晶31を充填してアクティブマトリック
ス液晶表示パネルが構成される。前記ゲート電極G1,
ドレイン電極D1,ソース電極S1及びシリコン活性層
23は第1のスイッチング素子であるnチャネルMOS
トランジスタnTFT1を構成し、前記ゲート電極G
2,ドレイン電極D2,ソース電極S2及びシリコン活
性層23は第2のスイッチング素子であるnチャネルM
OSトランジスタnTFT2を構成する。
FIG. 2 is a sectional view showing an example of an active matrix liquid crystal display panel according to the present invention. That is, gate electrodes G1 and G2 made of, for example, Al are formed on the lower glass substrate 21, and an insulating film 22 such as SiO 2 is formed on the gate electrodes G1 and G2 and the lower glass substrate 21.
Is formed. The gate electrode G on the insulating film 22
Silicon active layers 23 are formed at positions corresponding to 1 and G2. A pixel electrode ITO made of, for example, Al is formed on the insulating film 22, and drain electrodes D1 and D2 and source electrodes S1 and S2 are formed on the insulating film 22 and a part of the silicon active layer 23. It is formed by being connected to ITO. A protective film 24 such as SiO 2 is formed on the insulating film 22, the pixel electrode ITO, the silicon active layer 23, the drain electrodes D1 and D2, and the source electrodes S1 and S2. On the protective film 24, for example, polyimide or the like is formed. Alignment film 25 is formed. On the other hand, a blind layer 27 such as chromium is formed on the upper glass substrate 26, and an insulating film 28 such as SiO 2 is formed on the blind layer 27 and the upper glass substrate 26. A common electrode 29 made of, for example, Al is formed on the insulating film 28, and an alignment film 30 made of, for example, polyimide is formed on the common electrode 29. Then, the upper glass substrate 26 and the lower glass substrate 21 are arranged with a spacer (not shown) interposed so that the alignment film 30 and the alignment film 25 face each other, and between the alignment film 30 and the alignment film 25. An active matrix liquid crystal display panel is constructed by filling the liquid crystal 31. The gate electrode G1,
The drain electrode D1, the source electrode S1 and the silicon active layer 23 are the n-channel MOS which is the first switching element.
The transistor nTFT1 is formed, and the gate electrode G
2, the drain electrode D2, the source electrode S2, and the silicon active layer 23 are the n-channel M that is the second switching element.
The OS transistor nTFT2 is configured.

【0014】しかして、手動操作スイッチ、又は液晶表
示装置の表示画面の明暗に対応して制御部より制御用ゲ
ート信号Gsが制御用ゲート信号印加端子Tgに印加さ
れ、制御用ゲート信号Gsが例えば20V等のハイレベ
ルのときにはnチャネルMOSトランジスタnTFT2
がオンして液晶容量CLC,補助容量CS1と並列に調整用
補助容量CS2が接続される。この状態において、走査線
駆動回路部13からのゲート電圧VG を走査線X1,X
2………に供給し、ゲート電圧VG がハイレベルの走査
線に接続されたnチャネルMOSトランジスタnTFT
1をオンして、信号線駆動回路部12から信号線Y1,
Y2………に供給されている信号電圧VD を液晶容量C
LC,補助容量CS1及び調整用補助容量CS2に蓄積する。
この場合、信号電圧VD に対して画素電圧VP の変動量
ΔVP 1は ΔVP 1={CGS/(CGS+CLC+CS1+CS2)}・VG となり、変動量ΔVP 1は小さくなる。CGSはnチャネ
ルMOSトランジスタnTFT1のゲート・ソース間容
量である。
However, the control gate signal Gs is applied to the control gate signal application terminal Tg from the control unit in accordance with the brightness of the display screen of the liquid crystal display device or the manual operation switch, and the control gate signal Gs is, for example, When high level such as 20V, n-channel MOS transistor nTFT2
When turned on, the liquid crystal capacitance C LC and the auxiliary capacitance C S1 are connected in parallel with the auxiliary capacitance C S2 for adjustment. In this state, the gate voltage V G from the scanning line driving circuit unit 13 is applied to the scanning lines X1, X
2 ..., And an n-channel MOS transistor nTFT connected to the scanning line with a high gate voltage V G
1 is turned on, and the signal line drive circuit unit 12 outputs the signal lines Y1,
The signal voltage V D supplied to Y2 ...
Store in LC , auxiliary capacitance C S1 and adjustment auxiliary capacitance C S2 .
In this case, the variation amount ΔV P 1 of the pixel voltage V P with respect to the signal voltage V D is ΔV P 1 = {C GS / (C GS + C LC + C S1 + C S2 )} · V G , and the variation amount ΔV P 1 Becomes smaller. C GS is the gate-source capacitance of the n-channel MOS transistor nTFT1.

【0015】一方、前記制御用ゲート信号Gsが例えば
0V等のローレベルのときにはnチャネルMOSトラン
ジスタnTFT2がオフして液晶容量CLC,補助容量C
S1と並列に調整用補助容量CS2が接続されない。この状
態において、走査線駆動回路部13からのゲート電圧V
G を走査線X1,X2………に供給し、ゲート電圧VG
がハイレベルの走査線に接続されたnチャネルMOSト
ランジスタnTFT1をオンして、信号線駆動回路部1
2から信号線Y1,Y2………に供給されている信号電
圧VD を液晶容量CLC及び補助容量CS1に蓄積する。こ
の場合、信号電圧VD に対して画素電圧VP の変動量Δ
P 2は ΔVP 2={CGS/(CGS+CLC+CS1)}・VG となり、変動量ΔVP 2は大きくなる。
On the other hand, the control gate signal Gs is, for example,
When it is low level such as 0V, n-channel MOS transistor
The transistor nTFT2 is turned off and the liquid crystal capacitance CLC, Auxiliary capacity C
S1Auxiliary capacitance C for adjustment in parallel withS2Is not connected. This state
In the state, the gate voltage V from the scanning line drive circuit unit 13
GTo the scanning lines X1, X2 ...G
Is an n-channel MOS transistor connected to the high-level scanning line
The transistor nTFT1 is turned on, and the signal line drive circuit unit 1
2 the signal power supplied to the signal lines Y1, Y2 ...
Pressure VDThe liquid crystal capacity CLCAnd auxiliary capacity CS1Accumulate in. This
, The signal voltage VDAgainst the pixel voltage VPVariation Δ
VP2 is ΔVP2 = {CGS/ (CGS+ CLC+ CS1)} ・ VG  And the fluctuation amount ΔVP2 becomes larger.

【0016】以上のように、液晶表示装置の表示画面の
明暗に対応して画素電圧VP の変動量をΔVP 1または
ΔVP 2に切換えることにより、正しい色調の自然な色
合いとなるように調整することができる。
As described above, by changing the variation amount of the pixel voltage V P to ΔV P 1 or ΔV P 2 in accordance with the lightness and darkness of the display screen of the liquid crystal display device, a natural hue of a correct color tone can be obtained. Can be adjusted.

【0017】尚、第2のスイッチング素子であるnチャ
ネルMOSトランジスタnTFT2と調整用補助容量C
S2よりなる直列回路を2組以上液晶容量CLCと並列に接
続するようにしてもよく、この場合には画素電圧VP
変動量の範囲を広げることができる。
The n-channel MOS transistor nTFT2, which is the second switching element, and the auxiliary capacitance C for adjustment.
Two or more sets of series circuits of S2 may be connected in parallel with the liquid crystal capacitance C LC , in which case the range of variation of the pixel voltage V P can be widened.

【0018】[0018]

【発明の効果】以上述べたように本発明によれば、液晶
表示装置の表示画面の明暗に対応してスイッチング素子
をオン,オフ制御することにより、調整用補助容量を液
晶容量と並列に接続したり、接続しなかったりして画素
容量を最適な値に調整し、画素電圧の変動量を調整して
色調の変化を調整することができ、正しい色調の自然な
色合いとなるように調整することができる。
As described above, according to the present invention, the auxiliary storage capacitor for adjustment is connected in parallel with the liquid crystal capacitor by controlling the switching elements to be turned on and off according to the brightness of the display screen of the liquid crystal display device. Adjust the pixel capacity to the optimum value by connecting or not connecting it, and adjust the variation of the pixel voltage to adjust the change in the color tone, and adjust the color tone to obtain a natural hue. be able to.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る表示駆動素子マトリックス回路部
の一例を示す回路図である。
FIG. 1 is a circuit diagram showing an example of a display drive element matrix circuit section according to the present invention.

【図2】本発明に係る液晶表示パネルの一例を示す断面
図である。
FIG. 2 is a cross-sectional view showing an example of a liquid crystal display panel according to the present invention.

【図3】本発明の一実施例を示す概略ブロック図であ
る。
FIG. 3 is a schematic block diagram showing an embodiment of the present invention.

【図4】従来の表示駆動素子マトリックス回路部を示す
回路図である。
FIG. 4 is a circuit diagram showing a conventional display drive element matrix circuit section.

【図5】従来の表示駆動素子マトリックス回路部の1画
素を示す等価回路図である。
FIG. 5 is an equivalent circuit diagram showing one pixel of a conventional display drive element matrix circuit section.

【符号の説明】[Explanation of symbols]

11…表示駆動素子マトリックス回路部、12…信号線
駆動回路部、13…走査線駆動回路部、nTFT1…n
チャネルMOSトランジスタ、nTFT2…nチャネル
MOSトランジスタ、CLC…液晶容量、CS1…補助容
量、CS2…調整用補助容量、Tg…制御用ゲート信号印
加端子。
11 ... Display drive element matrix circuit section, 12 ... Signal line drive circuit section, 13 ... Scan line drive circuit section, nTFT1 ... n
Channel MOS transistor, nTFT2 ... n-channel MOS transistors, C LC ... liquid crystal capacitance, C S1 ... auxiliary capacitance, C S2 ... adjustment auxiliary capacitor, Tg ... controlling gate signal applying terminals.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 信号線と共通電源との間に直列に接続さ
れた走査線に制御端子が接続された第1のスイッチング
素子及び液晶容量と、 この液晶容量と並列に接続された第2のスイッチング素
子及び補助容量よりなる直列回路とを具備することを特
徴とする液晶表示装置。
1. A first switching element and a liquid crystal capacitor having a control terminal connected to a scanning line connected in series between a signal line and a common power source, and a second switching device connected in parallel with the liquid crystal capacitor. A liquid crystal display device comprising a series circuit including a switching element and an auxiliary capacitor.
JP9431692A 1992-04-14 1992-04-14 Liquid crystal display device Pending JPH05289635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9431692A JPH05289635A (en) 1992-04-14 1992-04-14 Liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9431692A JPH05289635A (en) 1992-04-14 1992-04-14 Liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH05289635A true JPH05289635A (en) 1993-11-05

Family

ID=14106875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9431692A Pending JPH05289635A (en) 1992-04-14 1992-04-14 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH05289635A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002202755A (en) * 2000-10-02 2002-07-19 Semiconductor Energy Lab Co Ltd Light-emitting device and its drive method
US6937222B2 (en) 2001-01-18 2005-08-30 Sharp Kabushiki Kaisha Display, portable device, and substrate
CN100356438C (en) * 2000-07-24 2007-12-19 精工爱普生株式会社 Electro-optical device and method for driving the same
US7423639B2 (en) 2004-01-12 2008-09-09 Samsung Electronics Co., Ltd. Photosensor and display device including photosensor
WO2011061964A1 (en) * 2009-11-18 2011-05-26 シャープ株式会社 Substrate for liquid crystal display device, liquid crystal display device, and method for driving liquid crystal display device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100356438C (en) * 2000-07-24 2007-12-19 精工爱普生株式会社 Electro-optical device and method for driving the same
JP2002202755A (en) * 2000-10-02 2002-07-19 Semiconductor Energy Lab Co Ltd Light-emitting device and its drive method
US6937222B2 (en) 2001-01-18 2005-08-30 Sharp Kabushiki Kaisha Display, portable device, and substrate
US7423639B2 (en) 2004-01-12 2008-09-09 Samsung Electronics Co., Ltd. Photosensor and display device including photosensor
WO2011061964A1 (en) * 2009-11-18 2011-05-26 シャープ株式会社 Substrate for liquid crystal display device, liquid crystal display device, and method for driving liquid crystal display device

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