JPH0528865B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a multiprocessor system in which the processors do not have a shared memory that can be accessed in common, so that the clocks that each processor has for indicating the time can be shared with each other. This invention relates to a clock synchronization method for adjustment.

[Conventional technology]

In a multiprocessor system, it is necessary to synchronize the clocks of each processor making up the system so that they indicate a common time throughout the system. For example, in a distributed filing system, a common time between processors is required to identify versions of files based on the creation and editing times recorded in each file. Also, if each processor accumulates its own history information based on the time common to the system,
It is possible to know in what order the failures were detected when they occur, and useful information for identifying the location where the failure has occurred can be obtained.

Even in a communication network system, which is an example of a multiprocessor system without a shared memory, a synchronization method is required so that the clocks of each communication node indicate a common time. For example, the 6th International Conference on
The clock synchronization method introduced in the paper ``An Erection Algorithm and Feature-Reviewed Clock Synchronization Program'' (Reference 1), which is included in the Proceedings of Taste-Reviewed Computing Systems, pages 364-371. TEMPO is UNIX
It is implemented in a network running on the 4.3BSD operating system.

In the above-mentioned system, one node serving as a master adjusts the time of all nodes at predetermined time intervals, and calculates an average time based on the determined times of each node. Thereafter, a clock adjustment instruction is given to all nodes, and each node adjusts its clock according to this instruction.

In addition, the digest paper of “16th Annual International Symposium on Fault Tolerant Computing”
The paper “Clock Synchronization in the Presence” on p.218-223
The clock synchronization method introduced in "Of Faults and Processors Joints" (Reference 2) uses distributed control rather than master-slave control like "TEMPO" explained above. In this system, the processor adjusts the clock according to the synchronization message indicating the earliest time among the synchronization messages periodically transmitted within the system. As a result, the fastest running clock will control the time in the system.

Furthermore, the paper ``Synchronizing Clocks in the Presence of Faults'' (Reference 3) described in ``Journal of Association of Computing Machinery'' Vol. 32, No. 1, January 1985, p. 52-78. The clock synchronization method introduced in 2007 is a synchronization method based on completely distributed control in which all processors periodically communicate the time of each processor.

[Problem that the invention seeks to solve]

In the synchronization method described in Document 1, a master node is essential. Therefore, in the event of a failure of the master node, a method of acting as a master node is required so that another node can perform the function of the master node. In addition, since one master node coordinates the clocks of all nodes, as the number of nodes increases, the amount of communication to the master node increases, and the task of calculating the average time of all nodes increases. increases.

On the other hand, in the method described in Reference 2 which employs distributed control, although it is distributed, one processor with the fastest clock controls the time within the system. Furthermore, if the clocks of the processors indicate approximately the same time, synchronization messages will be transmitted from a plurality of processors at the same time, resulting in a problem that the processing for synchronization control will be concentrated at a certain time.

Furthermore, in the method of Reference 3, since all processors communicate with each other, communication overhead becomes a problem when applied to an actual system.

As a method to solve these problems, "Basic study of time management methods in networks" (Reference 4) described in the 1st material of the Institute of Electronics, Information and Communication Engineers' Information and Communication Network Safety and Reliability Symposium, p. 35-38, In the method described in , each processor periodically selects a plurality of processors at random and ensures synchronization based on the time of the selected processors. In the method of Reference 4, there is no need to provide a processor for centralized control, and even when the number of processors in the system increases, communication messages are not concentrated on a certain processor, and the total number of messages in the system can be reduced. It is possible to reduce the amount compared to the conventional method. However, since all processors start synchronous control at a predetermined time, if synchronization is ensured and all processors indicate approximately the same time, the message transmission for synchronous control is There is a problem in that they are concentrated at a predetermined time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock synchronization method for a multiprocessor system in which messages for ensuring time synchronization of processors are not sent concentrated at specific times.

[Means to solve the problem]

According to the present invention, there is provided a clock synchronization method for a multiprocessor system consisting of n processors, in which the processors are provided with a clock indicating time, and m processors are randomly selected from among the n processors. In a clock synchronization method in a multiprocessor system, the processor reads clock information of the m processors, and repeats control of the clock based on the time of the m processors.
A timer capable of measuring the passage of arbitrary time within a predetermined range is provided, and when the clock reaches the predetermined time, the timer is set to a random value within the range and activated, and the timer is activated. A clock synchronization method in a multiprocessor system is provided, characterized in that a timer measures the time corresponding to the random value and reads clock information of the randomly selected m processors at the time when a timeout occurs. It will be done.

[Action of the invention]

The principle of the present invention will be explained with reference to FIG.

FIG. 3 is a diagram showing a specific example of a multiprocessor system. Each processor 301, 302,
303, 304, and 305 are equipped with clocks that indicate their own time. Further, each processor is connected to each other by a logical communication path 306 so that clock information of any processor can be read out. In a multiprocessor system that does not have a shared memory that can be commonly accessed by each processor, the clocks of each processor do not indicate the same time when the system is in its initial state. Moreover, the clock started from the same value,
Although the time is measured at roughly the same rate, the time gradually deviates as time passes. Therefore, each processor adjusts the clocks of each other through message communication according to this synchronization method described below.
As a result, the clocks of all processors are controlled to point to the same time within a certain synchronization accuracy.

In this synchronization method, each processor waits for a random period of time within a predetermined range to elapse when its own processor's clock reaches a predetermined time.
After this, m processors are randomly selected from among the n processors in the system, and the clock information of the processors is queried. Furthermore, it resets its own clock value based on the inquired clock information. For example, if the range of random meeting times is 10 minutes, 1:00, 2:00,
Assume that it is determined that synchronous control is to be performed at a time of 3:00. When the processor 301's clock reaches 1:00, it waits for a random period of time up to 10 minutes to elapse. If 6 minutes is selected as the random waiting time, at time 1:06, three processors are randomly selected from among the five processors in the system. If processor 301 selects processors 302, 303, and 304, it sends a message to these processors via communication path 306 inquiring about their clock values. Processor 301 calculates the average value of the returned clock values of the three processors, and resets its own clock value based on the average value. On the other hand, if the processor 302 selects a random waiting time of 4 minutes at time 1:00, it performs the control described above at time 1:04. For example, if the average value of the times of three processors is δ ahead of the time indicated by its own clock, each processor adds the difference δ to its own clock, and calculates the average of the times of the three processors. If the value is δ behind the time indicated by your clock, change your clock to δ
make it stop. The above operation requires that all processors set their own clocks to 1:00, 2:00, and 3:00.
This is repeated every predetermined time.

In this way, all processors are on a completely equal footing and implement exactly the same algorithms. At this time, since each processor performs synchronous control based on the clock information of the m processors, the amount of communication can be reduced compared to the conventional method. Moreover, since the m processors are selected at random at this time, the clock information of all the processors in the system is reflected in the synchronization control by repeating the synchronization control. Furthermore, since each processor starts sending time-aligned messages after a random lapse of time from a predetermined time, message sending does not concentrate at a specific time, and each processor processing can be distributed. A simulation experiment showed that the synchronization range of the processor clock was n
It has been confirmed that the convergence is independent of the value of m and satisfies sufficient synchronization accuracy when m = 2 to 10.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIGS. 1a and 1b show a first embodiment of an algorithm implementing the clock synchronization scheme according to the invention.

Figure 1a shows an algorithm that the processor executes when its own clock indicates a predetermined time; for example, when its own clock indicates 1:00,
Execution starts at certain predetermined times, such as 2:00 and 3:00. FIG. 1b shows the algorithm executed when a processor executes the algorithm of FIG. 1a and receives a message from the same processor. Note that these two algorithms may be executed in parallel, and a request to send clock information to itself may be generated.

The processor detects in control block 100 shown in FIG. 1a an interrupt from a clock that is set to occur when its own clock reaches a predetermined time. Detection of an interrupt from this clock activates the subsequent synchronous control algorithm.

That is, the control block 101 sets the timer to a random value within a predetermined range and starts the timer. Next, the control block 102 waits for the timer to time out, and after the timeout occurs, the control block 103 randomly selects m processors from among the n processors. Subsequently, control block 104 sends a message to these m processors to inquire about clock information.

Each processor also executes the algorithm shown in Figure 1b in parallel.
10, it is possible to detect a reception interrupt that occurs when a clock information transmission request message is received from the processor. That is, when a certain processor sends a message in control block 104 of FIG. 1a, the processor that received the message detects a reception interrupt in control block 110 of FIG. control block 1
At step 11, clock information is sent to the processor that sent the message. The clock information sent by the processor at this time is the value indicated by the clock itself, but if the processor requesting clock information records its own time in the request message, the difference between the clock and the requesting processor's time is recorded. You may send it as information.

In this way, the processor that sent the clock information transmission request message receives clock information from m processors. Continuing control block 1
In 05, the average clock value of the m processors is calculated based on the clock information of these m processors, and the average time of the m processors is subtracted from the time indicated by the clock of the own processor.
Find the difference δ.

Based on the difference δ from the average time of the m processors obtained as described above, the processor sets the value of its own clock as described below in control block 106 and thereafter.

That is, if the time indicated by the own processor's clock is equal to the average time (δ=0), control returns to control block 100. Also, if the time indicated by your own clock is later than the average time (δ
<0), control block 107 adds the difference δ to its own clock to advance the time, and then returns to control block 100. Furthermore, if the time indicated by its own clock is ahead of the average time (δ>0), the control block 108 stops the clock until the time δ has elapsed. After delaying the time in this manner, control returns to block 100. In either case, control block 100 detects an interrupt from the next clock occurring at a predetermined time.

The algorithm described above is executed by all processors.

FIGS. 2a and 2b show a second embodiment of the algorithm implementing the clock synchronization scheme according to the invention.

In a communication network system, which is an example of a multiprocessor system, when processors read each other's clock information, there is a communication delay between the processors, or the time required for communication processing and average time calculation is affected by the time accuracy of the clock. It is possible that it will be larger than . In order to prevent the clock synchronization control from being adversely affected by such processing overhead, the processor time at which the clock information is read is defined using an algorithm as described below.

Figures 2a and b illustrate the same algorithm. The algorithm shown here corresponds to the control blocks 103, 104, and 105 in FIG. This figure shows control in which the requested message is repeatedly transmitted m times, and the difference δ between the time indicated by the clock of the own processor and the average time is calculated based on the clock information sequentially received from these m processors. . In the second embodiment, the control procedures after the control block 107 in FIG. 1a are the same as those after the control block 107 in FIG. 1a.

The connector 200 shown in FIG. 2a is connected to the rear of the control block 102 of FIG. 1a. In control block 201, a value 0 is assigned to a variable k that counts the number of processors to be selected, and in control block 202, processor i is randomly selected from n processors in the system. Next, in control block 203, the time indicated by the clock in its own processor at this time is substituted into variable Ti,0, and in control block 204, a message is sent to request processor i to send clock information. After this, control block 205
, 1 is added to a variable k that counts the number of randomly selected processors. Control block 206
At , the variable k is compared with the value m, and if k<m, the process returns to the control block 202, and if k=m, the process continues to the connector 207 connected to the next process.

Connector 207 is connected to the front of control block 208 shown in FIG. 2b. control block 208
Now, as explained in FIG. 2a, responses to the clock information request messages sent to m processors are awaited. Due to variations in the transmission times of the request messages and variations in communication delays, responses from each processor also arrive at different times. When a response from a processor i arrives, a control block 209 assigns the time at which the response arrived to a variable ti,1, and a control block 210 assigns the time of the processor i recorded in the response message to a variable ti,1. Assign to Ti. Thereafter, 1 is subtracted from a variable k that stores the number of processors that are randomly selected and sent the request message, and the value of the variable k is compared in control block 212. If k>0, control block 2
Return to step 08 and wait for responses from other processors.
Receive responses from all processors, k=0
If so, control block 213 is executed.

Note that there may be cases where responses are not obtained from all processors even after a certain period of time has elapsed due to message loss or the like. In this case, control block 213 may be executed based on already obtained clock information. In the same control block 213, a variable indicating the time when processor i was selected.
Based on ti,0, a variable ti,1 indicating the time when the response from processor i arrived, and a variable Ti indicating the time of processor i recorded in the response message from processor i, the own processor determines the time ti. ，
The time of processor i when the time is 0 is predicted, and the difference δi between the time of processor i and the time of its own processor is determined. That is, assuming that the communication delay of a message from processor a to processor i is equal to the communication delay of a message sent from processor i to processor a almost at the same time, the time of processor i is predicted according to the following equation.

Ti-(ti, 1-ti, 0)/2 (1) Therefore, the difference δi between the time indicated by the clock of its own processor and the time indicated by the clock of processor i is expressed as follows.

δi=ti,0−{Ti−(ti,1−ti,0)/2}
...(2) The control block 214 calculates the average value of the m δi obtained in this way, and assumes that the same value is the difference δ from the average time of m randomly selected processors. .

Note that the connector 215 is connected to the front of the control block 106 in FIG. 1a. Based on the difference δ from the average time obtained as described above, the procedures starting from control block 106 in FIG. 1A, which have already been explained, are carried out. This algorithm predicts processor time by taking into account communication delays between processors, making it possible to eliminate the effects of communication delays.

〔Effect of the invention〕

As described above, by using the clock synchronization method of the present invention, in a multiprocessor system, all processors can be operated equally without providing a centrally controlled processor, and the clocks of each processor can be controlled within a certain range. Since there is no need for a centrally controlled processor that can be controlled to point to a common time, a failure in a particular processor will not cause a fatal failure to the system, ensuring high reliability. Since the messages sent by each processor are not concentrated at a specific time, it is possible to distribute the processing of the processors. The information required by each processor is only the time information of m processors, and according to simulation experiments, sufficient synchronization accuracy can be obtained when m=2 to 10. As described above, the effects obtained by the present invention are significant.

[Brief explanation of the drawing]

Figures 1a and b are flowcharts showing a first embodiment of the present invention, and Figures 2a and b show an algorithm for determining processor time in the second embodiment when communication delays are taken into account. Figure 3 is
1 is a diagram showing an example of a multiprocessor system. 100-111, 201-214... Control block, 200, 207, 215... Connector, 30
1 to 305... processors, 306... logical communication path between processors.

Claims (1)

[Claims] 1 This is a clock synchronization method for a multiprocessor system consisting of n processors, in which the processor is equipped with a clock that indicates the time, and m processors are randomly selected from among the n processors. In a clock synchronization method in a multiprocessor system, the clock information of the m processors is read out and the clock control based on the clock information of the m processors is repeated. A timer capable of measuring the passage of time is provided, and when the clock reaches a predetermined time, the timer is set to a random value within the range and activated, and the timer is set to a random value within the range, and the timer is set to a time corresponding to the random value. 1. A clock synchronization method in a multiprocessor system, characterized in that clock information of the m randomly selected processors is read out at a time when a timeout occurs.