JPH0528758A - Clock preparing circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution of the entire refresh circuit of a D-RAM by preparing a refresh clock signal by a simple circuit constitution. CONSTITUTION:In the refresh circuit of a D-RAM 3, the refresh clock signal of a refresh address counter circuit 5 can be prepared by combining an ALE signal outputted from a CPU 2 at every prescribed clock cycle when an access to the D-RAM 3 is not performed, with a writing signal or reading signal outputted from the CPU 2 to the D-RAM 3. At the same time, the reset signal of the refresh address counter 5 can be prepared based on a reset signal outputted from a reset circuit 6, and the writing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly to a clock generation circuit for generating a refresh clock signal for a refresh address counter circuit in a dynamic RAM (hereinafter referred to as D-RAM) refresh circuit.

[0002]

2. Description of the Related Art Conventionally, as a refresh circuit for a D-RAM, a refresh circuit having a structure shown in FIG. 4 has been known. In the figure, a CPU (central processing circuit) 2 which uses a clock oscillated by an oscillator 1 as a reference clock sends a write / read signal to a D-RAM 3 and also a D-RAM.
An address bus signal is sent to the address setting circuit 4. The refresh address counter circuit 5 is reset by the reset signal from the reset circuit 6, performs a counting operation using the refresh clock signal from the frequency dividing circuit 7 as a reference clock, and sends the refresh address signal to the refresh address counter circuit 5.

The D-RAM address setting circuit 4 selects the supplied address bus signal or refresh address signal, sends the D-RAM address signals A _{0 to} A ₇ to the D-RAM 3, and outputs the row address signal and the row address signal. Send the column address signal. On the other hand, the refresh clock signal of the refresh address counter circuit 5 is obtained by dividing the clock signal sent from the clock circuit 8 by the frequency dividing circuit 7. The frequency divider circuit 7 generates a refresh clock signal by synchronizing with the signal of the CPU 2 by the synchronizing signal output from the port of the CPU 2. FIG. 5 shows a time chart of the reset signal and the refresh clock signal with respect to the reference clock of the CPU 2.

[0004]

However, in the refresh circuit configured as described above, the refresh clock signal of the refresh address counter circuit 5 is generated by dividing the clock signal from the clock circuit 8 by the frequency dividing circuit 7. However, since the clock circuit 8 and the frequency dividing circuit 7 need to be configured by using an oscillator or a plurality of stages of counter circuits, there is a problem that the circuit configuration becomes complicated.

Therefore, the present invention provides a clock generation circuit which can contribute to simplification of the circuit configuration of the entire refresh circuit of the D-RAM by enabling generation of the refresh clock signal with a simple circuit configuration. The purpose is to provide.

[0006]

A clock generation circuit according to the present invention is a refresh circuit of a D-RAM having an address counter circuit for generating a refresh address signal, and a predetermined clock cycle from the CPU when the D-RAM is not accessed. Output from the reset circuit and a first generation circuit that generates a refresh clock signal of the address counter circuit by a combination of a timing control signal output for each time and a write signal or a read signal output from the CPU to the D-RAM And a second generation circuit that generates a reset signal for the address counter circuit based on the reset signal and the write signal.

[0007]

In the refresh circuit of the D-RAM, the CP
From U, write / read signal to D-RAM,
When the D-RAM is not accessed, a timing control signal called an ALE (Address Latch Enable) signal is sent every predetermined clock cycle. In the clock generation circuit according to the present invention, the refresh clock signal is generated by the combination of the write / read signal output from the CPU and the ALE signal, and the reset signal output from the reset circuit and the write signal output from the CPU are generated. A reset signal for the address counter circuit is generated based on

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a block diagram showing an embodiment of a clock generation circuit according to the present invention, and FIG. 2 is a block diagram showing an example of a circuit configuration of a refresh circuit of a D-RAM using the clock generation circuit according to the present invention. First, in FIG. 2, the clock generation circuit 10 according to the present invention is used as a circuit for generating a refresh clock signal to be supplied to the refresh address counter circuit 5, and other than that, the circuit configuration is the same as that of the conventional example of FIG. is there.

As shown in FIG. 1, the clock generation circuit 10 according to the present invention includes a NAND gate 11 which receives a write signal from the CPU 2 and a NAND gate 12 which receives a write signal and a read signal from the CPU 2 as two inputs. , Reset signal from reset circuit 6 and NAND gate 1
An OR gate 13 having two gate outputs of 1 and D-
When the RAM 3 is not accessed, the ALE signal output from the CPU 2 every predetermined clock cycle (6 clock cycles in this example) and the OR gate 14 having two inputs of the gate output of the NAND gate 12, and the reset signal from the reset circuit 6 Is a reset (R) input, and the gate output of the OR gate 14 is a clock (CK) input.
It is composed of a flip-flop 15.

The circuit operation of the clock generation circuit 10 having such a configuration will be described with reference to the time chart of FIG. Basically, the flip-flop 15 generates the refresh clock signal at the timing of the rising edge of the ALE signal sent from the CPU 2 in 6 clock cycles, but when the CPU 2 sends the write / read signal, that is, D- When accessing the RAM3, since the ALE signal is not transmitted, the flip-flop 1 is output at the falling timing of the write signal or the read signal.
By triggering 5, the refresh clock signal can be generated even during the period in which the ALE signal is not transmitted.

In the non-delivery period of the ALE signal, by utilizing the falling timing of the write signal or the read signal, as is apparent from the time chart of FIG. 3, only one clock is required as compared with the refresh clock signal of FIG. It will start up quickly, but looking at the overall time series,
Other timings are exactly the same, and D-RAM3
Since the refresh operation is performed only with the row address signal at a timing other than the timing when the write signal or the read signal is valid, the same operation as the conventional one can be performed. Further, not only the reset signal from the reset circuit 6 but also the write signal is used to generate the reset signal of the refresh address counter circuit 5, so that the reset can be performed at any time.

[0012]

As described above in detail, according to the present invention, in the refresh circuit of the D-RAM, the DR
The ALE signal output from the CPU every predetermined clock cycle when the AM is not accessed and the D-RA from the CPU
A refresh clock signal is generated by a combination with a write signal or a read signal output to M, and a reset signal for a refresh address counter circuit is generated based on the reset signal and the write signal output from the reset circuit. By doing so, the refresh clock signal and the reset signal can be generated with a simple circuit configuration, which can contribute to simplification of the circuit configuration of the entire refresh circuit of the D-RAM.

Further, in the clock generation circuit according to the present invention, the ALE signal is used in place of the conventional synchronization signal. Therefore, when the synchronization signal is output from the CPU, it is necessary to program for it. Since it is not necessary in the case of a signal, it is possible to reduce the burden on the CPU, and it is possible to achieve synchronization even if the oscillation frequency of the clock of the CPU changes. Further, by generating not only the reset signal from the reset circuit but also the write signal, the refresh address counter circuit can be reset at any time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock generation circuit according to the present invention.

FIG. 2 is a DR using a clock generation circuit according to the present invention.
It is a block diagram which shows the structure of the refresh circuit of AM.

FIG. 3 is a time chart for explaining the circuit operation of the present invention.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a time chart for explaining a circuit operation of a conventional example.

[Explanation of symbols]

2 CPU (Central Processing Circuit) 3 Dynamic (D) RAM 4 Address Set Circuit 5 Refresh Address Counter Circuit 10 Clock Generation Circuit According to the Present Invention

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Naoji Akutsu 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Tadashi Kasai 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (1)

Claim: What is claimed is: 1. A dynamic RAM refresh circuit including an address counter circuit for generating a refresh address signal, comprising: a clock generation circuit for generating a refresh clock signal for the address counter circuit; CPU when not accessing RAM
A first generation circuit that generates the refresh clock signal by a combination of a timing control signal output from the CPU every predetermined clock cycle and a write signal or a read signal output from the CPU to the dynamic RAM, and a reset circuit A refresh clock generation circuit comprising: a second generation circuit that generates a reset signal for the address counter circuit based on an output reset signal and the write signal.