JPH05286795A - Silicon semiconductor substrate - Google Patents
Silicon semiconductor substrateInfo
- Publication number
- JPH05286795A JPH05286795A JP4113184A JP11318492A JPH05286795A JP H05286795 A JPH05286795 A JP H05286795A JP 4113184 A JP4113184 A JP 4113184A JP 11318492 A JP11318492 A JP 11318492A JP H05286795 A JPH05286795 A JP H05286795A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- film
- oxide film
- semiconductor substrate
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、集積回路など半導体デ
バイス製造に用いられるシリコン半導体基板材料に関す
るものである。特に、本発明はデバイス製造中に受ける
重金属不純物をシリコン基板内のデバイス領域から除去
する効果を増強する目的のシリコン基板材料である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon semiconductor substrate material used for manufacturing semiconductor devices such as integrated circuits. In particular, the present invention is a silicon substrate material for the purpose of enhancing the effect of removing heavy metal impurities received during device manufacturing from the device region within the silicon substrate.
【0002】[0002]
【従来の技術】集積回路の高集積化に伴い、ダイナミッ
クメモリ(DRAM)において微少リーク電流の減少は
重要課題となっている。この微少リーク電流は半導体集
積回路製造工程中に混入する鉄、ニッケル、銅に代表さ
れる重金属不純物に起因する。この重金属不純物を除去
するためにゲッタリング法が用いられる。このゲッタリ
ング法には、半導体基板裏面に多結晶シリコン膜を形成
する方法、(Journal of Electrochemical Society 1982
年 129巻1294頁、特開昭59−186331、特開平0
1−315144号公報)が知られている。特開昭59
−186331号公報記載のものは、半導体基板裏面に
多結晶シリコン膜を形成する方法が記載され、この方法
では多結晶シリコン粒の粒界は高温で消滅しにくいた
め、高温処理を通して有効なことが示されている。特開
平01−315144号公報記載のものは、半導体基板
裏面に酸化膜を挟んで多結晶シリコン膜を形成する方法
が記載され、従来の多結晶シリコン膜形成法よりも高い
ゲッタリング能力が得られることが示されている。2. Description of the Related Art With the high integration of integrated circuits, reduction of a minute leak current in a dynamic memory (DRAM) has become an important issue. This minute leak current is caused by heavy metal impurities represented by iron, nickel, and copper that are mixed in during the semiconductor integrated circuit manufacturing process. A gettering method is used to remove the heavy metal impurities. This gettering method includes a method of forming a polycrystalline silicon film on the back surface of a semiconductor substrate, (Journal of Electrochemical Society 1982
Volume 129, page 1294, JP-A-59-186331, JP-A-0
No. 1-315144) is known. JP-A-59
JP-A-186331 describes a method of forming a polycrystalline silicon film on the back surface of a semiconductor substrate. In this method, the grain boundaries of polycrystalline silicon grains are hard to disappear at high temperatures, so that it is effective through high temperature treatment. It is shown. Japanese Patent Application Laid-Open No. 01-315144 describes a method of forming a polycrystalline silicon film with an oxide film sandwiched on the back surface of a semiconductor substrate, and a gettering ability higher than that of a conventional polycrystalline silicon film forming method is obtained. Has been shown.
【0003】[0003]
【発明が解決しようとする課題】半導体集積回路製造工
程において、最近の4MDRAMに代表される高集積化
に伴い、CMOS工程と呼ばれる1150℃から120
0℃、6時間〜10時間の高温長時間熱処理が行われて
いる。現在用いられているゲッタリング法の中でゲッタ
リング能力の高い手法である多結晶シリコン膜形成法で
も、高温長時間熱処理後、多結晶シリコン粒の粗大化に
より結晶欠陥密度の減少がおこり、ゲッタリング能力の
低下が問題となる。具体例として1991年日本応用物
理学関係連合講演会春期大会(講演予稿集第1分冊22
4頁)にて報告されている。本発明は、前記課題に対し
て、高温長時間熱処理工程後でも優れたゲッタリング能
力を有するシリコン基板を提供することを目的とする。In the process of manufacturing a semiconductor integrated circuit, with the recent trend toward higher integration represented by 4MDRAM, a temperature of 1150 ° C. to 120 ° C. called a CMOS process is called.
A high temperature and long time heat treatment of 0 ° C. and 6 hours to 10 hours is performed. Among the gettering methods currently used, even in the method of forming a polycrystalline silicon film, which has a high gettering ability, the crystal defect density decreases due to the coarsening of the polycrystalline silicon grains after heat treatment at high temperature for a long time. The deterioration of the ring ability becomes a problem. As a specific example, the 1991 Japan Applied Physics Association Lecture Spring Meeting (Lecture Proceedings 1st Volume 22)
4). It is an object of the present invention to provide a silicon substrate having excellent gettering ability even after a high temperature and long time heat treatment process.
【0004】[0004]
【課題を解決するための手段】本発明は、前記の目的の
ために次のゲッタリング能力増強単結晶シリコン基板と
その製造方法を提供する。シリコン半導体基板の裏面側
に、7Åから20Åの厚さのシリコン酸化膜と該酸化膜
上に形成された多結晶シリコン膜より成る複合膜が2層
以上形成されていることを特徴とするシリコン半導体基
板。The present invention provides the following gettering ability-enhanced single crystal silicon substrate and a method of manufacturing the same for the above-mentioned purpose. A silicon semiconductor, characterized in that, on the back surface side of a silicon semiconductor substrate, two or more layers of a composite film consisting of a silicon oxide film having a thickness of 7Å to 20Å and a polycrystalline silicon film formed on the oxide film are formed. substrate.
【0005】[0005]
【作用】シリコン半導体基板および多結晶シリコン膜の
酸化は、通常、酸化性雰囲気で500℃から1200℃
の温度域で熱酸化により形成される。10Å程度の薄い
酸化膜の形成については、過酸化水素を含む水溶液や硝
酸を含む水溶液に浸す処理を施しても可能である。この
ような手法により形成されたシリコン酸化膜は、シリコ
ン半導体基板上の密着性が良く膜厚も均一である。また
多結晶シリコン膜の形成は化学蒸着法が用いられる。た
とえばシランを原料とし600℃から800℃の温度域
でシランガスの熱分解反応によってシリコン半導体基板
上にシリコン原子を密着性良く均一に析出させることが
可能である。Function: Oxidation of the silicon semiconductor substrate and the polycrystalline silicon film is usually performed in an oxidizing atmosphere at 500 ° C to 1200 ° C.
It is formed by thermal oxidation in the temperature range of. The formation of a thin oxide film of about 10 Å can also be performed by dipping it in an aqueous solution containing hydrogen peroxide or an aqueous solution containing nitric acid. The silicon oxide film formed by such a method has good adhesion on the silicon semiconductor substrate and a uniform film thickness. Further, a chemical vapor deposition method is used for forming the polycrystalline silicon film. For example, it is possible to uniformly deposit silicon atoms on a silicon semiconductor substrate with good adhesion by a thermal decomposition reaction of silane gas in a temperature range of 600 ° C. to 800 ° C. using silane as a raw material.
【0006】シリコン基板上に、前記の方法を用いてシ
リコン酸化膜、多結晶シリコン膜を繰り返し形成するこ
とにより多層構造を得ることができる。前記の方法で形
成したシリコン基板を1150℃、10時間熱処理を行
った場合、酸化膜の厚さが5Å未満では、酸化膜は容易
に分解し、多結晶粒の粗大化がおこり、ゲッタリング能
力が低下する。酸化膜が7Åから20Åの場合には酸化
膜が島状酸化物になり、この酸化物が多結晶粒の粗大化
を防ぎ、微小な結晶粒が得られ、酸化膜が島状酸化物に
解離することにより、重金属元素の拡散の障害にはなら
ないことによりゲッタリング能力が低下しない。酸化膜
が20Åを越えて厚い場合には酸化膜が安定に存在し、
多結晶粒の粗大化を防ぐことはできるが、重金属不純物
の拡散の障壁になりゲッタリング能力が低下する。ま
た、シリコン酸化膜と該酸化膜上に形成された多結晶シ
リコン膜より成る複合膜が2層以上形成されることによ
り、著しくゲッタリング能力が向上する。A multi-layer structure can be obtained by repeatedly forming a silicon oxide film and a polycrystalline silicon film on the silicon substrate by using the above method. When the silicon substrate formed by the above method is heat-treated at 1150 ° C. for 10 hours, if the thickness of the oxide film is less than 5Å, the oxide film is easily decomposed to cause coarsening of polycrystalline grains and gettering ability. Is reduced. When the oxide film is from 7Å to 20Å, the oxide film becomes an island-shaped oxide, and this oxide prevents coarsening of polycrystalline grains, and fine crystal grains are obtained, and the oxide film dissociates into island-shaped oxide. By so doing, the gettering ability is not lowered because it does not hinder the diffusion of the heavy metal element. If the oxide film is thicker than 20Å, the oxide film is stable and
Although it is possible to prevent coarsening of polycrystalline grains, it becomes a barrier to diffusion of heavy metal impurities and the gettering ability is lowered. Further, the gettering ability is remarkably improved by forming two or more layers of the composite film including the silicon oxide film and the polycrystalline silicon film formed on the oxide film.
【0007】[0007]
【実施例】作成したシリコン基板の断面構造の模式図を
図1に示す。各層の酸化膜は500℃から800℃で酸
素ガスを含む雰囲気にて10分の熱処理を行い5Å、7
Å、15Å、20Å、25Åの酸化膜を形成した。各層
の多結晶シリコン膜の形成はシランガスを原料ガスと
し、基板温度650℃で15分、化学蒸着法で形成させ
た。多結晶シリコン膜の膜厚は2000Åである。シリ
コン酸化膜上に多結晶シリコン膜を形成させた複合膜を
2層形成した。EXAMPLE FIG. 1 shows a schematic view of the cross-sectional structure of the silicon substrate thus prepared. The oxide film of each layer is heat-treated for 10 minutes in an atmosphere containing oxygen gas at 500 to 800 ° C. for 5Å, 7
Oxide films of Å, 15Å, 20Å and 25Å were formed. The polycrystalline silicon film of each layer was formed by chemical vapor deposition at a substrate temperature of 650 ° C. for 15 minutes using silane gas as a source gas. The thickness of the polycrystalline silicon film is 2000Å. Two layers of a composite film having a polycrystalline silicon film formed on the silicon oxide film were formed.
【0008】次に本発明のシリコン基板のゲッタリング
能力を各複合膜の酸化膜厚を変えた試料に対して前熱処
理を行った後、銅を意図的に汚染し、銅の拡散熱処理
後、多結晶シリコン膜中に捕獲された銅の量を原子吸光
法により分析し、銅の回収率により評価した。前熱処理
条件は1150℃、10時間0.5%の酸素を含む窒素
雰囲気である。銅の故意汚染は、シリコン基板を回転さ
せ、その基板上に銅を含む水溶液を滴下することにより
行った。本方法では均一に基板上に付着することができ
る。銅の初期表面汚染量は1014/cm2 である。Next, the gettering ability of the silicon substrate of the present invention was preheated to a sample in which the oxide film thickness of each composite film was changed, then intentionally contaminated with copper, and after the diffusion heat treatment of copper, The amount of copper captured in the polycrystalline silicon film was analyzed by an atomic absorption method and evaluated by the copper recovery rate. The pre-heat treatment condition is 1150 ° C. and a nitrogen atmosphere containing 0.5% oxygen for 10 hours. The intentional contamination of copper was performed by rotating a silicon substrate and dropping an aqueous solution containing copper onto the substrate. According to this method, it is possible to uniformly attach the substrate. The initial surface contamination amount of copper is 10 14 / cm 2 .
【0009】汚染後拡散処理条件は、1000℃、25
分酸素雰囲気である。裏面にゲッタリングされた銅の量
は多結晶シリコン膜とシリコン酸化膜を含めて裏面から
0.5μmを弗酸と硝酸の混酸で溶解し、本溶液の銅濃
度を原子吸光法により分析し求めた。汚染した銅の回収
率は初期表面汚染量に対する多結晶シリコン中の銅の量
により求めた。ゲッタリング能力の目標値銅の回収率を
90%以上とした。その結果を表1に示す。The post-contamination diffusion treatment conditions are 1000 ° C. and 25
It is a partial oxygen atmosphere. The amount of copper gettered on the back surface was obtained by dissolving 0.5 μm from the back surface including the polycrystalline silicon film and the silicon oxide film with a mixed acid of hydrofluoric acid and nitric acid, and analyzing the copper concentration of this solution by atomic absorption spectrometry. It was The recovery rate of contaminated copper was determined by the amount of copper in polycrystalline silicon with respect to the amount of initial surface contamination. Target value of gettering ability The copper recovery rate was 90% or more. The results are shown in Table 1.
【0010】[0010]
【表1】 [Table 1]
【0011】本発明例は比較例に比べてゲッタリング能
力は優れている。以下詳細に述べる。比較例Fでは複合
膜が一層で第一シリコン酸化膜がない場合でゲッタリン
グ能力は弱い。比較例Gでは複合膜が一層で第一シリコ
ン酸化膜の膜厚が7Åの場合でゲッタリング能力は弱
い。比較例Hでは複合膜が一層で第一シリコン酸化膜の
膜厚が15Åの場合でゲッタリング能力は弱い。The gettering ability of the inventive example is superior to that of the comparative example. Details will be described below. In Comparative Example F, the gettering ability is weak when the composite film is a single layer and there is no first silicon oxide film. In Comparative Example G, the gettering ability is weak when the composite film is a single layer and the thickness of the first silicon oxide film is 7Å. In Comparative Example H, the gettering ability is weak when the composite film is a single layer and the thickness of the first silicon oxide film is 15Å.
【0012】比較例Iでは複合膜が一層で第一シリコン
酸化膜の膜厚が20Åの場合でゲッタリング能力は弱
い。比較例Jでは複合膜が二層で第一シリコン酸化膜の
膜厚が5Åで第二シリコン酸化膜の膜厚が7Åの場合
で、第一シリコン酸化膜が薄くゲッタリング能力は弱
い。比較例Kでは複合膜が二層で第一シリコン酸化膜の
膜厚が5Åで第二シリコン酸化膜の膜厚が20Åの場合
で、第一シリコン酸化膜が薄くゲッタリング能力は弱
い。In Comparative Example I, the gettering ability is weak when the composite film is a single layer and the thickness of the first silicon oxide film is 20Å. In Comparative Example J, the composite film has two layers, the thickness of the first silicon oxide film is 5Å and the thickness of the second silicon oxide film is 7Å, and the first silicon oxide film is thin and the gettering ability is weak. In Comparative Example K, the composite film has two layers, the thickness of the first silicon oxide film is 5Å and the thickness of the second silicon oxide film is 20Å, and the first silicon oxide film is thin and the gettering ability is weak.
【0013】比較例Lでは複合膜が二層で第一シリコン
酸化膜の膜厚が7Åで第二シリコン酸化膜の膜厚が5Å
の場合で第二シリコン酸化膜が薄くゲッタリング能力は
弱い。比較例Mでは複合膜が二層で第一シリコン酸化膜
の膜厚が7Åで第二シリコン酸化膜の膜厚が25Åの場
合で第二シリコン酸化膜が厚くゲッタリング能力は弱
い。比較例Nでは複合膜が二層で第一シリコン酸化膜の
膜厚が20Åで第二シリコン酸化膜の膜厚が5Åの場合
で第二シリコン酸化膜が薄くゲッタリング能力は弱い。In Comparative Example L, the composite film has two layers and the thickness of the first silicon oxide film is 7Å and the thickness of the second silicon oxide film is 5Å.
In this case, the second silicon oxide film is thin and the gettering ability is weak. In Comparative Example M, when the composite film has two layers and the thickness of the first silicon oxide film is 7Å and the thickness of the second silicon oxide film is 25Å, the second silicon oxide film is thick and the gettering ability is weak. In Comparative Example N, when the composite film has two layers and the thickness of the first silicon oxide film is 20Å and the thickness of the second silicon oxide film is 5Å, the second silicon oxide film is thin and the gettering ability is weak.
【0014】比較例Oでは複合膜が二層で第一シリコン
酸化膜の膜厚が20Åで第二シリコン酸化膜の膜厚が2
5Åの場合で第二シリコン酸化膜が厚くゲッタリング能
力は弱い。比較例Pでは複合膜が二層で第一シリコン酸
化膜の膜厚が25Åで第二シリコン酸化膜の膜厚が7Å
の場合で第一シリコン酸化膜が厚くゲッタリング能力は
弱い。比較例Qでは複合膜が二層で第一シリコン酸化膜
の膜厚が25Åで第二シリコン酸化膜の膜厚が20Åの
場合で第一シリコン酸化膜が厚くゲッタリング能力は弱
い。In Comparative Example O, the composite film has two layers, the first silicon oxide film has a thickness of 20Å, and the second silicon oxide film has a thickness of 2.
In the case of 5Å, the second silicon oxide film is thick and the gettering ability is weak. In Comparative Example P, the composite film has two layers, the thickness of the first silicon oxide film is 25Å and the thickness of the second silicon oxide film is 7Å.
In this case, the first silicon oxide film is thick and the gettering ability is weak. In Comparative Example Q, when the composite film has two layers and the thickness of the first silicon oxide film is 25Å and the thickness of the second silicon oxide film is 20Å, the first silicon oxide film is thick and the gettering ability is weak.
【0015】[0015]
【発明の効果】本発明は、シリコン半導体基板裏面側に
シリコン酸化膜と多結晶シリコン膜の複合膜を2層以上
形成されていることにより、高温長時間熱処理後でも多
結晶シリコン膜の結晶粒の微細化が可能となり、半導体
集積回路製造工程すべてにわたり高いゲッタリング能力
を維持できる。According to the present invention, since two or more composite films of a silicon oxide film and a polycrystalline silicon film are formed on the back surface side of a silicon semiconductor substrate, the crystal grains of the polycrystalline silicon film can be formed even after heat treatment at high temperature for a long time. It becomes possible to miniaturize, and it is possible to maintain high gettering ability throughout the entire semiconductor integrated circuit manufacturing process.
【図1】多結晶シリコン膜とシリコン酸化膜を多層構造
にしたシリコン基板の概念図。FIG. 1 is a conceptual diagram of a silicon substrate having a multilayer structure of a polycrystalline silicon film and a silicon oxide film.
Claims (1)
ら20Åの厚さのシリコン酸化膜と該酸化膜上に形成さ
れた多結晶シリコン膜より成る複合膜が2層以上形成さ
れていることを特徴とするシリコン半導体基板。1. A composite film comprising a silicon oxide film having a thickness of 7Å to 20Å and a polycrystalline silicon film formed on the oxide film is formed in two or more layers on the back surface side of a silicon semiconductor substrate. Characteristic silicon semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4113184A JPH05286795A (en) | 1992-04-07 | 1992-04-07 | Silicon semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4113184A JPH05286795A (en) | 1992-04-07 | 1992-04-07 | Silicon semiconductor substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05286795A true JPH05286795A (en) | 1993-11-02 |
Family
ID=14605689
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4113184A Withdrawn JPH05286795A (en) | 1992-04-07 | 1992-04-07 | Silicon semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05286795A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5973386A (en) * | 1996-02-16 | 1999-10-26 | Nec Corporation | Semiconductor substrate having silicon oxide layers formed between polysilicon layers |
US6300680B1 (en) * | 1997-05-09 | 2001-10-09 | Nec Corporation | Semiconductor substrate and manufacturing method thereof |
US6423556B1 (en) * | 2000-04-06 | 2002-07-23 | Seh America, Inc. | Method for evaluating impurity concentrations in heat treatment furnaces |
WO2011007494A1 (en) * | 2009-07-16 | 2011-01-20 | 信越半導体株式会社 | Method for manufacturing semiconductor epitaxial wafer, and semiconductor epitaxial wafer |
-
1992
- 1992-04-07 JP JP4113184A patent/JPH05286795A/en not_active Withdrawn
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5973386A (en) * | 1996-02-16 | 1999-10-26 | Nec Corporation | Semiconductor substrate having silicon oxide layers formed between polysilicon layers |
US6046095A (en) * | 1996-02-16 | 2000-04-04 | Nec Corporation | Semiconductor substrate having polysilicon layers and fabrication process of semiconductor device using the same |
US6300680B1 (en) * | 1997-05-09 | 2001-10-09 | Nec Corporation | Semiconductor substrate and manufacturing method thereof |
US6423556B1 (en) * | 2000-04-06 | 2002-07-23 | Seh America, Inc. | Method for evaluating impurity concentrations in heat treatment furnaces |
WO2011007494A1 (en) * | 2009-07-16 | 2011-01-20 | 信越半導体株式会社 | Method for manufacturing semiconductor epitaxial wafer, and semiconductor epitaxial wafer |
JP2011023550A (en) * | 2009-07-16 | 2011-02-03 | Shin Etsu Handotai Co Ltd | Method for manufacturing semiconductor epitaxial wafer, and semiconductor epitaxial wafer |
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