JPH05284424A - Word phase adjustment device for video signal - Google Patents

Abstract

PURPOSE:To provide the word phase adjustment device for a video signal in which the word phase is adjusted with a margin and disturbance of a picture is prevented from being incurred. CONSTITUTION:The phase adjustment device sending/receiving a video signal(VS) comprising word data(WD) of a prescribed bit number from picture element data and controlling the read in matching with a receiver side by using FIFO memories to adjust the phase of the word at the sender side and the receiver side is provided with plural FIFO memory cells(MC) fetching one word data of the received VS, a write control means 4 switching sequentially the written MC in the unit of the received VS word data and a detection means 5 detecting a synchronizing signal from the received VS, and also with a read control means 11 selecting the MC in the order of write to read the WD from the written MC among the plural MC in matching with the phase of the WD at the receiver side and controlling the selection of the MC in the order apart from the written MC by a prescribed number of the MC upon the receipt of a correction signal, a means 9 generating an approach signal when the selected MCs of the read write control means are close to each other, and a means 10 receiving an output of the detection means and the approach signal and outputting a correction signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a word phase adjusting device for a video signal, which performs word phase adjustment using an IFO (Fast In Fast Out) type memory.

[0002]

2. Description of the Related Art For example, in a studio, a convention hall, an event hall, a theater, etc., TV cameras are installed at various places, and the TV video signals captured by these TV cameras are transmitted to a broadcasting room or a broadcasting station. There is a system for performing adjustment, editing, recording, broadcasting and the like.

In addition to such multi-way relay, also in a remote monitoring device or the like, a video signal obtained by a television camera installed in each place is sent to the center for monitoring or recording by a VTR or the like. ..

In this case, there are a plurality of television cameras, and the video signals from the cameras are digitally transmitted via transmission lines such as optical cables. Then, these video signals are taken in by selecting any desired channel (any of the above-mentioned transmission paths for a television camera) via a channel changeover switch called a switcher.

Here, even if the video signals of the respective channels are almost frame-synchronized, the word phase of each video output device on the transmission side and the device (monitor, VTR, editing device, etc.) on the reception side. There is a slight deviation in Then, when the channel to be taken in is switched by the switcher in the state where the word phase is deviated, the video signals having different word phases are switched as they are. Therefore, the screen jump is disturbed by the phase jump at the moment of switching. This is very unsightly.

In other words, considering a video signal, the video signal to be transmitted is sampled at a predetermined sampling rate, digitized, and transmitted, but the data per sample is, for example, a quantum so that it can be contained in about 10 bits of data. Turn into. The data per sample is treated, for example, as one word by adding C bits indicating the delimiter for each word, but if the phase of the word does not match when the digital data of another channel is switched, a jump of the word phase occurs. However, there is a problem that noise is generated during word synchronous hunting in the D / A conversion unit. Further, in the large-scale matrix switcher, if the signals are not bit-synchronized, there is a problem that noise occurs due to crosstalk. For this reason, the conventional FIFO
Using the memory of the shape, once the video signal before switching,
The data is buffered, and the reading is adjusted according to the word phase of the receiving device.

FIG. 3 shows an example of the configuration of a conventional system of this type. The video signal input to the input signal terminal 21 is digitally converted by the A / D converter 22, which is the optical transmitter 23.
After being converted into an optical signal by
4, is received by an optical receiver 25 provided on the other end side of the transmission path 24, is returned to an electric signal, and is further D / A.
The converter 27 converts the analog signal into the original video signal. There are a plurality of TV cameras, and the video signal of each TV camera is sent to the receiving side through the above-described system provided corresponding to each. Since each of these video signals is frame-synchronized with the receiving system,
Only the word phase of the video signal matters.

Therefore, FI for adjusting the word phase
The FO memory 26 is provided in front of the D / A converter 27, and the read is adjusted by adjusting the word phase of the system on the receiving side to read. The FIFO type memory 26 synchronizes the word phases, and then supplies the word phase to a switcher 29. The switch 29 has a plurality of input channels, and when the input channel is designated on the controller 28, the controller 28 controls the switch 29 to pass the video signal of the designated channel. As a result, the switch 29
A video signal of a designated channel, that is, a video signal from a designated television camera is output from the signal output terminal 30.

Each FI provided for each channel
The FO type memory 26 is subjected to writing and reading operations under the control of the control circuit 31. Therefore, the frame-synchronized video signals of the respective channels are passed through the respective FIFO type memories 26. The word phase is adjusted and output.

[0010]

As described above, video signals of a plurality of channels, which are substantially frame-synchronized, are individually received, and these are input to the switching device, and the switching device selects one of them. There is a system that switches to the video of the desired channel by outputting the video signal of each channel.In this case, although the video signal of each channel has a frame synchronization relationship, the word phase between the video output device and the input side video device is It is inevitable that there will be subtle differences. Therefore, at the moment when the channel is switched, noise may occur on the screen due to the word phase jump, which causes many problems when used for commercial broadcasting.

As described above, when two or more digital signals are to be used by switching, even if at least the digital signals of the respective different channels have substantially the same frame phase, that is not enough, and the word phase is not sufficient. In many cases, the phases must match.

In other words, considering a video signal, the video signal to be transmitted is sampled at a predetermined sampling rate, digitized, and then transmitted, and the data per sample is, for example, a quantum so that it can be contained in about 10 bits of data. Turn into. The data per sample is treated, for example, as one word by adding C bits indicating the delimiter for each word, but if the phase of the word does not match when the digital data of another channel is switched, a jump of the word phase occurs. However, there is a problem that noise is generated during word synchronous hunting in the D / A conversion unit.

If the output devices are different, it is unavoidable that there is a slight difference in the frame frequency, and accordingly, the word phase shift is unavoidable. Therefore, the occurrence of the word jump becomes a problem. Further, in the large-scale matrix switcher, if the signals are not bit-synchronized, there is a problem that noise occurs due to crosstalk.

Therefore, the FI having a capacity of several words
The word phase is adjusted by adjusting the read phase through the FO. However, as long as the write address and read address of the FIFO are opened with a sufficient buffer capacity,
Depending on the situation, the write address and the read address may be close to each other, and the written data may be read without any delay, and the writing is restricted because the reading is not in time. There is a possibility that the data may be written or the read data may be lost because the writing is not in time. With this, the word phase cannot be adjusted with a sufficient margin, and it is inevitable that the image is disturbed.

Therefore, the object of the present invention is that the word phase can be adjusted with a sufficient margin, and therefore,
An object of the present invention is to provide a word phase adjusting device for a video signal, which can surely prevent the screen from being disturbed.

[0016]

In order to achieve the above object, the present invention is configured as follows. That is, a system for transmitting / receiving a digital video signal in which pixel data is represented by a predetermined number of bits and converted into word data,
A plurality of FIFO-type memory cells for fetching one word data of a received video signal in an apparatus for adjusting the word phase between the transmitting side and the receiving side by controlling the reading according to the receiving side using a memory A write control means for sequentially switching the plurality of memory cells in units of word data of a received video signal to switch write memory cells; a sync signal detecting means for detecting a sync signal from the received video signal; Of the plurality of memory cells in accordance with the word data phase of the system, in order to read word data from a written memory cell, the memory cells are selected in the write order, read control is performed, and a timing correction signal is selected. The memory cells are in the order in which the memory cells are separated from the write memory cells by the specified number of memory cells. Read control means for performing selective correction control so as to form cells, and comparing means for comparing selected states of the selected memory cells of the read control means and the write control means and generating an approach signal when the two are close to each other; And a control means that responds to the detection output of the synchronization signal detection means and outputs the timing correction signal when the approach signal is received.

[0017]

In the above structure, the write control means sequentially switches the plurality of memory cells in units of word data of the received video signal to switch the write memory cell, and the switched memory cell switches the received video signal by one word. Sequentially capture data. On the other hand, the sync signal detecting means detects the sync signal from the received video signal, and the read control means matches the word from the written memory cell among the plurality of memory cells according to the word data phase of the receiving side system. In order to read data, memory cells are selected in the order of writing and read control is performed. Further, the comparing means compares the selected states of the selected memory cells of the read control means and the write control means and generates an approach signal when the two are close to each other. Then, the control means responds to the detection output of the synchronization signal detection means, and when receiving the approach signal, outputs a timing correction signal to give to the read control means. When the read control means receives the timing correction signal, the read control means performs selective correction control so that the memory cells to be selected become memory cells in a sequence in which the memory cells are separated from the write memory cells by a predetermined number.

As a result, when the memory cell used for writing and the memory cell used for reading come close to each other and there is no more margin for buffering, the generation period of the synchronization signal is used. Adjusting the read memory cell selected so that the read memory cell is separated from the memory cell currently being written by a predetermined number of memory cells, whereby the memory cell being written and the read memory cell are adjusted. It is possible to control such that the memory cells provided for the memory cell and the memory cell are not located close to each other. As a result, reading is delayed and writing is restricted,
It is possible to prevent the occurrence of a situation where the read data is lost because the writing is not in time.

When the video signal output of a video output device such as a television camera or VTR is sent to a video input device on the input side such as a television monitor, VTR or editing device, the output side and the input side are frame-synchronized. However, since the device is different, the frame frequency (subcarrier frequency fsc)
Will be slightly different. In order to synchronize the video signals having slightly different frame frequencies, the video signals must be compressed or expanded.

In the present invention, by performing such compression or decompression in the sync signal portion, the synchronization is performed without deteriorating the image. The present invention monitors the write and read timing in the FIFO so that they are close together,
When the margin is reduced, the timing is corrected when the synchronization signal is detected, so that the synchronization can be performed without image deterioration.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a word phase adjusting device of the present invention. In FIG. 1, 1 is a signal terminal for inputting a video signal, 2 is a clock signal input terminal for inputting a bit clock signal, and 3 is a word of a signal input to the signal terminal 1 operating in synchronization with this clock signal. It is a word synchronization circuit that synchronizes.

The bit clock signal input to the bit clock signal input terminal 2 is obtained by extracting the clock from the signal transmitted through the transmission path, and the video signal input to the signal terminal 1 is For example, 10-bit digital data is obtained by sampling the sampling frequency at a frequency corresponding to the subcarrier frequency f sc, and C bits that are word synchronization bits (C bit data are alternately "1" and "0"). “Repeat” is added, and this 11-bit data is called word data.

The word synchronizing circuit 3 is a circuit for detecting the C bit of such word data and generating a word synchronizing signal. The word synchronizing circuit 3 detects the word synchronizing by using the clock signal input to the clock input terminal 2 as an operation clock. ..

Reference numeral 4 is a write counter, 5 is a synchronizing signal detection circuit, 6 is a switch, 7a to 7d are memory cells, 8 is a switch, 9 is a phase comparator, 10 is an AND gate, 11 is a read counter, and 12 is a counter. The signal output circuit 13 is a read clock input terminal. The write counter 4 controls the switching of the switch 6 in synchronization with the word synchronizing signal from the word synchronizing circuit 3 and inputs it to the phase comparator 9.

Each of the memory cells 7a to 7d is a FIFO type memory having a memory capacity of one word, and the write counter 4 counts the word synchronization signal of the word counter 4 to write data in the memory cells 7a to 7d. A switch signal (memory cell address information) designating a memory cell to be used for is generated, and the switch 6 selects a memory cell in which the input signal from the input terminal 1 can be written corresponding to this switch signal. It is a circuit that provides the input signal.

The synchronizing signal detecting circuit 5 is a circuit for receiving an input signal from the input terminal 1 and detecting the synchronizing signal from the input signal. The read clock input terminal 13 is a clock corresponding to the word transmission rate obtained from a switcher or the like. The read counter 11 is input as a read clock signal, and the read counter 11 counts the read clock signal to read the memory cells 7a to 7a.
A switch signal (memory cell address information) that specifies a memory cell to be used for reading is generated from among d, and the switch 8 selects a memory cell corresponding to the switch signal and selects the selected memory. This is a circuit for giving read data from the cell to the signal output terminal 12.

The phase comparator 9 receives the switching signal (write address information) of the write counter 4 and the switching signal (read address information) from the read counter 11, compares the two, and both become adjacent memory cells. If the memory cells are adjacent to each other, an adjacent signal is output.

The AND gate 10 is a gate for passing an adjacent signal in synchronization with the detection sync signal from the sync signal detection circuit 5, and the adjacent signal output via the AND gate 10 is read by the read counter 11. It becomes a correction signal.

Upon receiving this timing correction signal, the read counter 11 adjusts the read address so that the memory cell currently used for writing and the memory cell currently used for reading have the maximum span. This is performed by giving the same address twice, returning some of the current addresses, or advancing some of them.

In this embodiment, the memory cells are from 7a to 7a.
In the ideal state, when the memory cell 7a is in the write state, the memory cell 7c is in the read state, and when the memory cell 7b is in the write state, the memory cell 7d is in the read state and the memory cell 7c is in the ideal state. Is in the write state, the memory cell 7a is in the read state, and
When the memory cell 7d is in the write state, the memory cell 7b
In the read state, every other write memory cell and read memory cell is the maximum margin state. That is, the data storage capacity is set to have the maximum margin. The word phase adjusting device 20 is configured as described above.

The word phase adjusting device 20 having such a configuration is arranged and used as shown in FIG. 2, for example. 2 is an example applied to the system of FIG. 3 described in the prior art, and the same components as those in FIG. 3 are denoted by the same reference numerals and the description thereof will be omitted.

Next, the operation of the present apparatus having the above structure will be described.
The video signal input to the input signal terminal 21 is digitally converted by the A / D converter 22, converted into an optical signal by the optical transmitter 23, and then transmitted through the transmission line 24 by the optical fiber. Is received by the optical receiver 25 provided on the other end side of the signal and converted into an electric signal, and further converted into an analog signal by the D / A converter 27 to become the original video signal. There are a plurality of TV cameras, and the video signal of each TV camera is sent to the receiving side through the above-described system provided corresponding to each.

Since each of these video signals is frame-synchronized with the receiving system, only the word phase of the video signal becomes a problem. Therefore, the word phase adjusting device 20 for adjusting the word phase is provided in the preceding stage of the D / A converter 27, and the reading is adjusted so as to match the word phase of the receiving side system. I have to. The word phases are synchronized by the word phase adjusting device 20 and then applied to a switcher 29. The switch 29 has a plurality of input channels, and when the input channel is designated on the controller 28, the controller 28 controls the switch 29 to pass the video signal of the designated channel. As a result, the video signal of the designated channel from the switch 29, that is, the video signal from the designated television camera is output from the signal output terminal 30.

The operation of the word phase adjusting device 20 will be described in detail. In the word phase adjustment device 20, when the data of the video signal converted into word data is input to the signal terminal 1 as serial data, the word synchronization circuit 3 generates a word clock. That is,
The word synchronization circuit 3 receives the bit clock signal extracted from the transmission line by the extraction circuit (not shown) through the bit clock input terminal 2 and receives the serial data input from the signal terminal 1, and the word synchronization circuit 3 receives the serial data. 3 operates in synchronization with this bit clock signal to extract a word synchronization bit from the serial data and outputs it as a word clock signal. This word clock signal is input to the write counter 4, and the write counter 4 counts this word clock signal and outputs a switching signal (address information) corresponding to the count value.

The switch 6 selects the memory cells 7a to 7d in response to this switch signal, sends the serial data from the input terminal 1 to the selected memory cell, and the switch 6 selects the serial data. Write to the selected memory cell. Since the word clock signal is output in units of words, when one word of serial data is written in a memory cell, it is controlled to switch to the next memory cell. As a result, the memory cells 7a to 7d are set to 1
Every time data of word is fetched, the data is switched in order to store the word data. In this way, the switch 6 is switched in synchronization with the word clock, and the input signals are sequentially written into the memory cells 7a to 7d.

On the other hand, the read word clock input terminal 13
Is supplied with a read word clock signal, and the read counter 11 counts the input read word clock signal and outputs a switching signal (address information) corresponding to the count value.

The switch 8 selects one of the memory cells 7a to 7d in response to this switch signal, and controls the serial data stored in the selected memory cell to be read in the order of writing. Read serial data.

Since the word clock signal is output word by word, when one word of serial data is read from a memory cell, it is controlled to switch to the next memory cell. As a result, the memory cells 7a to 7d are sequentially switched every time data of one word is read in synchronization with the word clock from the switcher side, and the word data is read out.

In this way, the switch 8 is switched in synchronization with the word clock to sequentially read the word data from the memory cells 7a to 7d. Then, the read data string is output to the output terminal 12.

Further, the phase comparator 9 compares the timings of writing and reading, and outputs an adjacent signal when writing and reading are performed in adjacent memory cells. That is,
The phase comparator 9 compares the switching signal (address information) of the write counter 4 with the switching signal (address information) of the read counter 11 and determines whether one of the adjacent memory cells is for writing and the other is for reading. Check by comparison. Then, when the adjacent memory cells are selected as described above, an adjacent signal is output,
It is given to the AND gate 10.

Further, the sync signal detection circuit 5 detects a signal corresponding to the sync signal in the data string from the input terminal 1 and outputs it as a sync detection signal, which is given to the AND gate 10. As a result, the adjacent signal is output from the AND gate 10 during the output period of the synchronization detection signal and is given to the read counter 11 as a timing correction signal.

Upon receipt of this timing correction signal, the read counter 11 adjusts the read address so that the memory cell currently used for writing and the memory cell currently used for reading have the maximum opening as the address space. To do. This is performed by giving the same address twice, returning some of the current addresses, or advancing some of them.

In this embodiment, the memory cells are 7a to 7a.
In the ideal state, when the memory cell 7a is in the write state, the memory cell 7c is in the read state, and when the memory cell 7b is in the write state, the memory cell 7d is in the read state and the memory cell 7c is in the ideal state. Is in the write state, the memory cell 7a is in the read state, and
When the memory cell 7d is in the write state, the memory cell 7b
In the read state, every other write memory cell and read memory cell is the maximum margin state. That is, the data storage capacity is set to have the maximum margin.

In this way, the adjacent signal and the sync detection signal are ANDed by the AND circuit 10 to become the read timing correction signal, which is input to the read counter 11 and the timing adjustment of the write counter 4 and the read counter 11 is performed. The word phase is adjusted and output.

Since the timing correction of the read counter 11 is performed within the sync signal generation time, the repetition or deletion of the same word occurs only within the sync signal time, and therefore there is no image deterioration.

In the case of NTSC video, the sampling frequency of the input signal is 4 fsc (14.31818 MHz), 10-bit encoding, and parallel processing 10B1C (10 binary 1 complement ins).
ertion) code, one line of video (corresponding to the sync signal interval) has 910 sampling, and the deviation of the writing and reading phases occurring in one line is due to the allowable deviation of the subcarrier frequency (fsc) of 3,579,545 Hz. , ± 15Hz, so 910 × 2 × 15 / 3,579,545 = 0.008, and if it is a correction for each line of the NTSC video signal,
Since it is a slip of 1 word or less, it is sufficient that the memory cells have a configuration of 4 memory cells 7a to 7d as shown in the figure.

On the other hand, the blanking level (0 IRE) is 0Fh (however, h indicates a hexadecimal number), the white level (100 IRE) is 320h, and the synchronization level (-40 IRE) as the quantization level of the video signal. ) For 010h, video full scale for 004h ~
When it is set to 3FBh, any of 000h to 003h and 3FCh to 3FFh can be inserted as a correction instruction signal during A / D conversion. By this method, correction can be made for each frame, and if the video signal is considered to have a scanning line of 525 lines, a slip of about 4 words occurs, so that a memory cell of about 8 words is sufficient.

As described above, although the present system is frame-synchronized, when capturing a video signal having a slightly different frame frequency, several memories having a very small synchronization of about 1 word (the above-mentioned memory) are used. If about 4 memories are prepared in the embodiment), the video signal can be synchronized by adjusting the word phase, so that the video processing device such as a video switcher can be made compact and low in cost.

As described above in detail, this system is a system for expressing pixel data by a predetermined number of bits and converting it into word data, and transmitting and receiving a digital video signal, which is a FIF.
A plurality of FIFO type memories for fetching one word data of a received video signal in a device for adjusting the word phase between the transmitting side and the receiving side by controlling the reading according to the receiving side using an O type memory. A cell, a write control means for sequentially switching the plurality of memory cells in units of word data of a received video signal to switch a write memory cell, a sync signal detecting means for detecting a sync signal from the received video signal, and a receiving side Of the plurality of memory cells in accordance with the word data phase of the system, the memory cells are selected in the written order in order to read the word data from the written memory cells, and the read control is performed, and the timing correction signal is also selected. The memory cells to be written are separated by a predetermined number of memory cells from the write memory cells. Read control means for performing selective correction control so as to be a recell, comparing means for comparing selected states of the selected memory cells of the read control means and the write control means, and generating an approach signal when both are in close proximity, In response to the detection output of the synchronization signal detection means, when it receives the approach signal, it comprises a control means for outputting the timing correction signal, the write control means, a plurality of memory cells, The write memory cells are sequentially switched in units of word data of the received video signal, and the received video signal is sequentially fetched into the switched memory cells one word data at a time. The sync signal is detected, and the read control means sets the plurality of signals in accordance with the word data phase of the receiving system. Of the memory cells, in order to read word data from the written memory cells, the memory cells are selected in the write order and read-controlled, and the comparing means selects the selected memory cells of the read control means and the write control means. When the two are close to each other, an approach signal is generated, and the control means responds to the detection output of the synchronization signal detecting means. When the approach signal is received, a timing correction signal is output to control reading. Give to the means. Then, the read control means performs selective correction control when the timing correction signal is received so that the memory cells to be selected become memory cells in the order in which the memory cells are separated from the write memory cells by a predetermined number of memory cells.

As a result, when the memory cell being used for writing and the memory cell being used for reading come close to each other and there is no more room for buffering, the generation period of the synchronization signal is used. Adjusting the read memory cell selected so that the read memory cell is separated from the memory cell currently being written by a predetermined number of memory cells, whereby the memory cell being written and the read memory cell are adjusted. It is possible to control the memory cells provided in the memory cell so that they are not in close proximity to each other, and thus, the reading is delayed and the writing is restricted, or the reading data is lost due to the insufficient writing. This can prevent the occurrence of such a situation.

The present invention is not limited to the embodiments described above and shown in the drawings, but can be appropriately modified and implemented without departing from the scope of the invention. For example, in the above embodiments, Although the C bit is used for word separation, the present invention is not limited to this, and a unique pattern is inserted in a specific portion of the synchronization signal, and this is detected to detect the timing correction signal. It is also possible to obtain the output timing of.

[0052]

As described above in detail, according to the present invention, the word phase can be adjusted with a sufficient margin, and therefore the word of the video signal can be surely prevented from causing the disturbance of the screen. A phase adjustment device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example in which the present invention is applied to a video switching device.

FIG. 3 is a block diagram illustrating a configuration example of a conventional system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Signal terminal, 2 ... Clock signal input terminal, 3 is a word synchronizing circuit, 4 is a write counter, 5 is a synchronizing signal detecting circuit, 6, 8 ... Switchers, 7a to 7d ... Memory cells, 9 ... Phase comparator, Reference numeral 10 ... AND gate, 11 ... Read counter, 12 ... Signal output circuit, 13 ... Read clock input terminal, 20 ... Word phase adjusting device.

Claims (2)

[Claims] 1. A system for transmitting and receiving a digital video signal, in which pixel data is represented by a predetermined number of bits and converted into word data, by using a FIFO type memory to control reading according to the receiving side and transmitting. In a device that adjusts the word phase between the receiving side and the receiving side, a FIFO that takes in the received video signal for one word data
-Shaped memory cells, write control means for sequentially switching these memory cells in units of word data of the received video signal to switch the write memory cells, and a sync signal detection for detecting a sync signal from the received video signal. And a memory cell selected from the plurality of memory cells in accordance with the word data phase of the receiving side system so as to read the word data from the written memory cell in the written order, and the timing is corrected. When a signal is received, the selected memory cells are selected and modified so that the memory cells to be selected are the memory cells in the order separated from the write memory cells by a predetermined number, and the read control means and the write control means are selected. Generates an approach signal when the memory cells are selected and the two are in close proximity. A video signal word phase adjusting apparatus comprising: a comparison means, and a control means that responds to a detection output of the synchronization signal detection means and outputs the timing correction signal when the approach signal is received. 2. The word phase adjusting device for a video signal according to claim 1, wherein the digital video signal is a serial signal capable of self-word synchronization in which an additional bit is added to one word.