JPH0528080A - Input/output controller - Google Patents

Abstract

PURPOSE:To improve the processing efficiency by writing data, which is transferred by plural transfer requests from a channel which does not report the final transfer of a series of data transfer at the time of input transfer, in a main storage by one transfer request. CONSTITUTION:A channel priority discriminating circuit 30 which selects firmware interrupt requests from plural channels, an input data buffer 40 where plural transfer data are stored, a processor part 70, an input transfer control part 50, etc., are provided. At the time of the lower-order end of input transfer to the channel which does not report the final transfer of a series of data transfer, the processor part 70 outputs a final transfer instruction to an input transfer control circuit 50 by the firmware interrupt request from the same channel. Then, the input transfer control circuit 50 requests write to the main storage, and data which is not written in the main storage at the time of the lower-order end is transferred. Consequently, transfer data to plural transfer requests from the channel are transferred by one request of transfer to the main storage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device,
In particular, the present invention relates to an input / output control device that arbitrates input data transfer from a channel that does not report a final transfer in a series of data transfers and input transfer to a main memory via a system bus.

[0002]

2. Description of the Related Art Conventionally, in this type of input / output control device, in input transfer between a channel and a main memory for which a final transfer is not reported in a series of data transfer, data received by one transfer request from the channel Is arbitrated with the system bus, transferred as data for one transfer request to the main memory, and written to the main memory.

[0003]

In the above-mentioned conventional input / output control device, in the input transfer, since data is written to the main memory for each transfer request from the channel, data for a plurality of transfer requests from the channel are buffered. However, there is a drawback in that the load on the system bus is greater than that of the operation of storing the data in the main memory and transferring the stored data at once to the main memory via the system bus in the buffer full state.

Further, since there is no report from the channel that it is the last transfer at the end of a series of data transfers, lower end (before the count value of the number of remaining transfer bytes becomes "0",
In the case where the channel ends the transfer), it cannot be recognized even when the transfer from the channel ends.

Therefore, since the data stored in the buffer cannot be transferred to the main memory as the last transfer data at the lower end when the buffer does not become full, transfer data for a plurality of transfer requests from the channel are transferred to the main memory at one time. However, there was a drawback that the performance could not be improved.

An object of the present invention is to provide an input / output control device that solves the above problems.

[0007]

In order to achieve the above object, in the input / output control device according to the first invention of the present application, data transfer requests from a plurality of channels which do not report final transfer in a series of data transfer, Channel priority judgment circuit that selects one transfer request and firmware interrupt request from firmware interrupt request according to priority, data transfer request for each channel, input data buffer that stores transfer data for multiple times, and data transfer remaining for each channel A transfer byte number counting unit that counts the number of transfer bytes, a processor unit that performs interrupt processing and microinstruction control by a firmware interrupt request selected by the channel priority determination circuit, and a data transfer request selected by the channel priority determination circuit The input data buffer Fafuru (free area runs out in the storage area per channel by a plurality of times of transfer request)
When the count "0" of the transfer byte number counting unit is detected, or when there is data in the input data buffer due to execution of a microinstruction from the processor unit, a request for writing transfer data to the main memory via the system bus. And an input transfer control circuit for performing.

The input / output control device according to the second invention of the present application is, in the information processing device of the first invention, in the input data buffer of the corresponding channel when the firmware interrupt request selected by the channel priority determination circuit is received. It has a final transfer generation circuit for requesting data transfer, and
Instead of the input transfer control circuit, when the data transfer request selected by the channel priority determination circuit is accepted and the buffer of the input data buffer is full, when the count “0” of the transfer byte number counting unit is detected, or When the transfer request from the final transfer generation circuit is received, when there is data in the input data buffer, it has an input transfer control circuit which requests writing of transfer data to the main memory via the system bus.

Also, the input / output control device according to the third invention of the present application is, in the information processing device of the first invention, when the firmware interrupt from the channel is received, the transfer of the data in the input data buffer of the corresponding channel is performed for each channel. In addition to the input transfer control circuit, a final transfer request generation circuit for requesting a data transfer request selected by the channel priority determination circuit is accepted to transfer the number of transfer bytes when the buffer of the input data buffer is full. When the count "0" of the count unit is detected, or when a transfer request for each channel is received from the final transfer generation circuit, when there is data in the input data buffer, transfer of the corresponding channel to the main memory via the system bus It has an input transfer control circuit for making a data write request.

[0010]

According to the present invention, the performance is improved by writing the data transferred by a plurality of transfer requests from the channel which does not report the final transfer in the series of data transfer to the main memory by one transfer request. Is.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, in this embodiment, the input / output control device 10 includes a channel priority determination circuit 30, an input data buffer 40, an input transfer control circuit 50, a transfer byte number counting unit 60, and a processor unit 70. There is.

The channel priority determination circuit 30 determines the data transfer request signal c0 of the highest priority channel from the data transfer request signals a0 from a plurality of channels that do not report the final transfer in a series of data transfers, according to the priority order peculiar to the channel. Similarly, the FW interrupt request signal d0 having the highest priority is selected from the firmware (hereinafter, FW) interrupt request signals b0 from a plurality of channels.

The transfer byte number counting unit 60 counts the number of remaining transfer bytes of transfer data for each channel.

The input data buffer 40 can store 32 bytes of transfer data e0 from the channel corresponding to the channel, and can store 16 bytes of data transferred by one data transfer request from the channel for two times.

The input transfer control circuit 50 controls and manages the input data buffer 40, and the channel priority determination circuit 30.
When the data transfer request signal c0 selected in
The control signal j0 controls the input data buffer 40 to store the transfer data e0 from the channel in the corresponding channel area.

When a 32-byte storage is detected in the input data buffer 40, a write request signal h to the main memory is sent.
0 is output, the write data i0 is read and transferred to the system bus 20.

The processor unit 70 receives the FW interrupt request signal d of the channel selected by the channel priority determination circuit 30.
When 0 is accepted, microinstruction control by interrupt processing is performed.

Next, the operation will be described.

After the transfer is completed, normally, the transfer data e0 from the channel is stored in the input data buffer 40 by the data transfer with the channel, and the count output f0 of the corresponding channel of the transfer byte number counting unit 60 becomes "0". The input transfer control circuit 50 detects "0" and outputs the write request signal h0 to the main memory even when 32 bytes of data are not stored in the input data buffer 40 (only 16 bytes of data). Then the data transfer ends.

However, the channel ends the transfer before the count value of the corresponding channel of the transfer byte number counting unit 60 becomes "0" (this is called lower end).
Therefore, when the transfer data stored in the input data buffer 40 at the end of the transfer is not 32 bytes, the input transfer control circuit 50 cannot make a write request to the main memory.

Therefore, after the transfer is completed, the processor unit 7 receives the FW interrupt request signal b0 requested by the same channel.
When interrupting to 0, the processor unit 70 outputs the final transfer instruction g0 (micro instruction) to the input transfer control circuit 50.

In response to the final transfer instruction g0, the input transfer control circuit 50 makes a write request to the main memory, and transfers the data that could not be written to the main memory when the lower order was completed.

(Second Embodiment) FIG. 2 is a block diagram showing a second embodiment of the present invention.

In FIG. 2, 11 is an input / output control device, 2
1 is a system bus, 31 is a channel priority determination circuit, 41
Is an input data buffer, 61 is a transfer byte number counting unit, and 71 is a processor unit. The configuration and function of these are almost the same as those of the first embodiment.

Further, a1 is a data transfer request from the channel, b1 is a FW interrupt request from the channel, c1 is a data transfer request, d1 is an FW interrupt request, e1 is transfer data from the channel, f1 is a counter output, h1 is A write request to the main memory, i1 is write data, and j1 is a control signal.

Further, the present invention has the final transfer generation circuit 81 which requests the transfer of the data in the input data buffer of the corresponding channel when the firmware interrupt request selected by the channel priority determination circuit 31 is received.

Further, instead of the input transfer control circuit 50, when the data transfer request selected by the channel priority determination circuit 31 is accepted and the buffer of the input data buffer 41 is full, the count "0" of the transfer byte number counting section 61 is received. Is detected, or when the transfer request from the final transfer generation circuit 81 is received, when there is data in the input data buffer 41, an input transfer control circuit 51 that requests writing of transfer data to the main memory via the system bus 21 Have

The final transfer generation circuit 81 creates a final transfer report from the FW interrupt request signal d1 selected by the channel priority determination circuit 31 and outputs the final transfer request signal k1 to the input transfer control circuit 51.

In response to the final transfer request signal k1, the input transfer control circuit 51 makes a transfer request to the main memory, and transfers the data that could not be written to the main memory when the lower order was completed.

(Third Embodiment) FIG. 3 is a block diagram showing a third embodiment of the present invention.

In FIG. 3, reference numeral 12 denotes an input / output control device, 2
2 is a system bus, 32 is a channel priority determination circuit, 42
Is an input data buffer, 62 is a transfer byte number counting unit, and 72 is a processor unit. The configuration and function of these are almost the same as those of the first embodiment.

Further, a2 is a data transfer request from the channel, b2 is a firmware interrupt request from the channel, c2 is a data transfer request, d2 is a firmware interrupt request, e2 is transfer data from the channel, f2 is counter output, h2 is A main memory write request, i2 is write data, and j2 is a control signal.

Further, in the present embodiment, when the firmware interrupt from the channel is received, the final transfer request generation circuit 82 for requesting the transfer of the data in the input data buffer of the corresponding channel is provided for each channel.

Further, in place of the input transfer control circuit 50, when the data transfer request selected by the channel priority determination circuit 32 is accepted and the buffer of the input data buffer 42 is full, the count "0" of the transfer byte number counting section 62. Is detected, or when a transfer request for each channel is received from the final transfer generation circuit 82, when there is data in the input data buffer 42, a request to write the transfer data of the corresponding channel to the main memory via the system bus 22 is made. It has an input transfer control circuit 52.

The final transfer generation circuit 82 creates a final transfer report from the FW interrupt request signal b2 from the channel and outputs the final transfer request signal 12 for each channel to the input transfer control circuit 52.

In response to the final transfer request signal 12 for each channel, the input transfer control circuit 52 makes a transfer request to the main memory, and transfers the data that could not be written to the main memory when the lower order was completed.

[0039]

As described above, according to the present invention, in the case where the lower end is completed in the input transfer with the channel for which the final transfer is not reported in the series of data transfer, the FW interrupt request from the channel is transferred to the main memory. By making it possible to transfer the remaining data that cannot be transferred to the input data buffer by the write request, it is possible to transfer the transfer data from the channel for a plurality of times with a single write request to the main memory. There is an effect that the load on the system bus can be reduced as well as the improvement.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

[Explanation of symbols]

10, 11, 12 Input / output control device 20, 21, 22 System bus 30, 31, 32 Channel priority determination circuit 40, 41, 42 Input data buffer 50, 51, 52 Input transfer control circuit 60, 61, 62 Number of transfer bytes Counting unit 70, 71, 72 Processor unit 81, 82 Final transfer generation circuit a0, a1, a2 Data transfer request from channel b0, b1, b2 Firmware interrupt request from channel c0, c1, c2 Data transfer request d0, d1, d2 Firmware interrupt request e0, e1, e2 Channel transfer data f0, f1, f2 Counter output g0 Final transfer instruction h0, h1, h2 Main memory write request i0, i1, i2 Write data j0, j1, j2 Control signal k1 final transfer request signal 12 final transfer request signal for each channel

Claims (3)

[Claims] 1. A channel priority determination circuit for selecting one transfer request and firmware interrupt request from data transfer requests and firmware interrupt requests from a plurality of channels that do not report final transfer in a series of data transfers, and for each channel. The data transfer request is based on an input data buffer that stores transfer data for multiple times, a transfer byte number counting unit that counts the number of remaining transfer bytes of data transfer for each channel, and a firmware interrupt request selected by the channel priority determination circuit. A processor unit that performs interrupt processing and microinstruction control, receives the data transfer request selected by the channel priority determination circuit, and fills the buffer of the input data buffer (a storage area per channel for a plurality of transfer requests has an empty area. Disappeared), When the count "0" of the byte count unit for sending bytes is detected, or when there is data in the input data buffer by the execution of a microinstruction from the processor unit, a request for writing transfer data to the main memory via the system bus is made. An input / output control device comprising an input transfer control circuit. 2. The information processing apparatus according to claim 1, further comprising a final transfer generation circuit that requests transfer of data in the input data buffer of the corresponding channel when the firmware interrupt request selected by the channel priority determination circuit is received. Further, in place of the input transfer control circuit, when the data transfer request selected by the channel priority determination circuit is accepted and the buffer of the input data buffer is full, and when the count “0” of the transfer byte number counting unit is detected. Or an input transfer control circuit for requesting write of transfer data to the main memory via the system bus when the transfer request from the final transfer generation circuit is received when there is data in the input data buffer. I / O controller. 3. The information processing apparatus according to claim 1, further comprising a final transfer request generation circuit for requesting transfer of data in an input data buffer of a corresponding channel when receiving a firmware interrupt from the channel, In place of the input transfer control circuit, when the data transfer request selected by the channel priority determination circuit is accepted and the buffer of the input data buffer is full, when the count “0” of the transfer byte number counting unit is detected, or An input transfer control circuit is provided which, when receiving a transfer request for each channel from the final transfer generation circuit, requests writing of transfer data of a corresponding channel to a main memory via a system bus when there is data in the input data buffer. Input / output control device characterized by.