JPH0528031B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a driving method and a driving circuit for a solid-state image sensor using a CCD (charge transfer device) as a signal charge transfer means.

[Background of the invention]

Conventionally, video cameras have used image pickup tubes such as Pijicon as image pickup elements.
Solid-state image sensors, which are integrated with photoelectric conversion elements arranged in an array on a semiconductor substrate, are smaller, lighter, and consume less power than image pickup tubes.
In recent years, it has become widely used due to its advantages in terms of image retention, lifespan, stability, etc.

Currently commercialized solid-state image sensors are MOS
type (Metal Oxide Semiconductor type), CPD type (Charge Priming Device type), and CCD type.
There are different types (for example, Journal of the Television Society).
(Refer to October 1983 issue) Among these, CPD type and
CCD-type solid-state image sensors have the advantage of low noise compared to MOS-type solid-state image sensors, but on the other hand, because CCDs are used for horizontal charge transfer, the driving voltage is high. It has the disadvantage of becoming.

Hereinafter, using a CPD type solid-state image sensor as an example, the reason why the drive voltage becomes higher will be explained.

FIG. 1 is a block diagram showing a conventional example of a CPD type solid-state image sensor, in which 1 is a CCD for horizontal transfer, 2 is an input section, 3 is a transfer section, 4 is an output section, 5 is a coupling section,
6 is a MOS transistor, 7 is a transfer gate line, 8
is a photoelectric conversion section, 9 is a vertical signal line, and 10 is a vertical line.
MOS transistor, 11 is photodiode, 1
2 is a vertical gate line, and 13 is a vertical scanning circuit.

In the figure, in the photoelectric conversion section 8, a photodiode 11 and a vertical MOS transistor 10 form a pair to constitute a picture element, and a large number of such picture elements are arranged in an array. A light image of the subject is formed on the photoelectric conversion unit 8, and a signal charge is generated in the photodiode 11 according to the amount of light received. When a pulse is supplied from the vertical scanning circuit 13 to the vertical MOS transistor 10 through the vertical gate line 12, the signal charge generated in the photodiode 11 is transferred to the vertical signal line 9 through the vertical MOS transistor 10.

The coupling section 5 connects the photoelectric conversion section 8 and the CCD for horizontal transfer.
1, and connects the signal charge of the vertical signal line 9 through the transfer gate line 7 for horizontal transfer.
Transfer to CCD1. Note that the coupling section 5 is provided with a circuit for increasing charge transfer efficiency and a circuit for sweeping out unnecessary signals such as vertical smear to the outside, but these are omitted here and the basic It is shown in the circuit configuration.

Next, the operating principle of this solid-state image sensor will be explained.

The vertical scanning circuit 13 sequentially outputs pulses to the vertical gate lines 12 arranged in the vertical direction (vertical direction in the drawing) for each horizontal retrace period. When this pulse is output to the vertical gate line 12, all of the MOS transistors 10 in a row in the horizontal direction (horizontal direction in the drawing) connected to the vertical gate line 12 are turned on, and the signal charges generated in the photodiodes 11 are is transferred to the vertical signal line 9. A pulse is then supplied to the transfer gate line 7 to
The MOS transistor 6 is turned on, and the signal charges of all the vertical signal lines 9 are transferred to the horizontal transfer via the coupling part 5.
It is transferred to the transfer unit 3 of the CCD 1.

Next, during the horizontal scanning period, the signal charges of the transfer section 3 are sequentially transferred in the horizontal direction, whereby a video signal is obtained from the output section 4.

In the next horizontal retrace period, the vertical scanning circuit 13 generates a pulse to the next vertical gate line 12, and a similar signal charge transfer is performed. Shifting in the vertical direction, a continuous video signal is thereby obtained from the output section 4.

In addition, in order to improve the transfer efficiency of signal charges in the transfer section 3, the input section 2 of the horizontal transfer CCD 1 receives the signal charges every time the signal charges are transferred through the coupling section 5.
Bias charges are injected into the transfer section 3.

In such solid-state image sensors, horizontal transfer
A high voltage is required between the output section 4 and the coupling section 5 of the CCD 1. Therefore, first, this output section 4 will be explained using FIGS. 2 to 4.

FIG. 2 is a block diagram showing the vicinity of the output section 4 of the horizontal transfer CCD 1 in FIG. 1, in which 14 is an n-type substrate;
15 is a p-type well, 16 is an n-type diffusion layer, 17,1
8 is a gate, 19 is an output gate, 20 and 21 are
MOS transistor, 22 is a resistor, 23 and 24 are drive pulse input terminals, 25 is a voltage application terminal, 26
2 is a reset gate pulse input terminal, 27 is a reset voltage application terminal, and 28 is a video signal output terminal.

In FIG. 2, a p-type well 15 is formed on an n-type substrate 14, gates 17 and 18 are alternately arranged on this p-type well 15, and transfer portions 3 (first
). In this case, gate 17,1
The gates 17 and 18 partially overlap each other so that there are no gaps between the gates 8 and undesirable potentials. Driving pulses φ ₁ and φ ₂ having mutually different phases are supplied to the gates 17 and 18, respectively.

An n-type diffusion layer 16 is formed at the end of the p-type well 15, and an output gate 19 is provided between the n-type diffusion layer 16 and the final stage gate 18 of the transfer section 3.
A constant voltage V _pg is applied from the voltage application terminal 25 . The source of a MOS transistor 20 and the gate of a MOS transistor 21 are connected to the n-type diffusion layer 16, and the drains of these MOS transistors 20 and 21 are connected to a voltage application terminal 27. Further, a resistor 22 is connected to the source of the MOS transistor 21, and a source follower type output amplifier is formed by the MOS transistor 21 and the resistor 22, and the video signal output terminal 28 is connected to the MOS transistor 21.
Connected to the source of transistor 21.

The above n-type diffusion layer 16, MOS transistor 2
0,21 and resistor 22 for horizontal transfer
It constitutes the output section 4 of the CCD 1 (Fig. 1),
A reset gate pulse RG is supplied to the MOS transistor 20 from an input terminal 26, and a reset voltage VR is applied to a reset voltage application terminal 27.

There is a stray capacitance on the source side of the n-type diffusion layer 16 and the MOS transistor 21, and the signal charge from the transfer section 3 and the bias charge mentioned earlier are accumulated in the combined stray capacitance (hereinafter referred to as output capacitance) _C0 . is,
It is taken out as a video signal through the MOS transistor 21 to the output terminal 28. In this case, before the signal charges and bias charges are transferred from the transfer section 3, the reset gate pulse RG is applied.
When the MOS transistor 20 is turned on, the potential of the output capacitor C ₀ is reset by the reset voltage VR from the reset voltage application terminal 27, and the charge is transferred from the transfer section 3, the potential of the output capacitor C ₀ remains constant. I'm trying to make it happen. In addition, the reset voltage
VR also serves as a bias voltage for the MOS transistor 21.

FIG. 3 is a timing chart showing the timing relationship between the drive pulses φ ₁ and _{φ 2} and _the reset gate pulse RG in FIG. V ₁ (v) is zero (v) at low level (hereinafter referred to as "L"), and the reset gate pulse RG is V ₂ (v) at "H" and V ₃ at "L".
(v). Charge transfer in the transfer section 3 and reset of the output capacitance _C0 are performed in accordance with level changes of the drive pulses φ ₁ and φ ₂ and the reset gate pulse RG. Such operations will be explained using FIG. 4. In addition, in FIG. 4, t ₁ , t ₂ , t ₃ , and t ₄ indicate the potential states of each part in FIG. 2 at each time t ₁ , t ₂ , t ₃ , and t ₄ in FIG. Further, in order to distinguish the potential of each part in FIG. 2, the reference numerals of these parts are shown, and the drive pulses φ ₁ and φ ₂ supplied to the gates 17 and 18 are also shown at the same time. Note that e _s is a signal charge, e _b is a bias charge, and e _o is a negative charge due to the reset voltage VR.
Further, V _t1 is the threshold voltage of the gate 17, V _t2 is the threshold voltage of the gate 18, and V _t3 is the threshold voltage of the MOS transistor 20.
is the threshold voltage of

In FIGS. 2 to 4, the driving pulses φ ₁ ,
_φ2 is “L” and reset gate pulse RG is “H”
(time t ₁ ), the potentials of gates 17 and 18 are -V _t1 and -V _t2 (however, -V _t1 > -V _t2 ), respectively.
(hereinafter, the potential of each part is expressed by the voltage generated in each part), and the gate 18 to which the drive pulse _φ1 is supplied has a signal charge e _s and a bias charge e _b ,
The potential of the MOS transistor 20 is reduced by V ₂ to (V ₂ −V _t3 ). Here, if the voltage value of the reset voltage VR is V _r , then the voltage value is (V ₂
-V _t3 )<V _r , and the output capacitance C ₀ is reset to V _r (v).

Next, when the drive pulse _φ2 becomes “H” (time
t ₂ ), the gate 17 to which this driving pulse φ ₂ is supplied,
The potential of gate 18 is lowered by V ₁ so that the potential of gate 17 is lower than the potential of gate 18 to which drive pulse φ ₁ is supplied, and as shown by the arrow, the potential of gate 18 to which drive pulse φ ₁ is supplied is lowered. The signal charge e _s and the bias charge e _b are transferred from the gate 18 to the gate 18 to which the drive pulse φ ₂ is supplied. At this time, the reset gate pulse RG becomes "L", so the potential of the MOS transistor 20 becomes sufficiently high.

Next, when the drive pulse φ ₂ becomes “L” (time
t ₃ ), the gate 17,1 to which the drive pulse φ ₂ is supplied
8, the original potential increases, and the transfer unit 3 changes the time.
Set to potential state at t ₁ . Since the potential of output gate 19 is set lower than the potential of gates 17 and 18,
The signal charge e _s and bias charge e _b transferred to the final gate 18 are connected to the output gate 1 as shown by the arrow.
9 to the output capacitor _C0 . However, the signal charge e _s and bias charge e _b of the other gate 18 are held as they are with the potential of the gate 17 acting as a barrier. The signal charge e _s and bias charge e _b transferred to the output capacitor C ₀ are taken out to the output terminal 28 as a video signal through the MOS transistor 21, as described above.

Next, when the drive pulse φ ₁ becomes “H” (time t ₄ ), the gate 17 to which the drive pulse φ ₁ is supplied,
18 is lowered by V ₁ and gate 1 is supplied with drive pulse φ ₂ , as shown by the arrow.
The signal charge e _s and the bias charge e _b are transferred from the gate 8 to the gate 18 to which the drive pulse φ ₁ is supplied. Then, as the drive pulse _φ1 becomes “L”,
The reset gate pulse RG becomes "H", the potential of the gates 17 and 18 to which the drive pulse φ ₁ is supplied increases, and the potential of the MOS transistor 20 decreases to reach the same potential state as at time t ₁ . In this state, the signal charge e _s
and bias charge e _b are discharged to the voltage application terminal 27 via the MOS transistor 20, and the output capacitance C ₀
is reset by reset voltage VR.

By repeating the above operation, horizontal transfer is performed in the transfer section 3 by sequentially transferring from the gate 18 to the next gate 18, and in the output section 4, the signal charge e _s is transferred from the transfer section 3 to the output capacitor _C0 . and bias charge
The transfer of e _b and the reset of output capacitance C ₀ are repeated alternately.

By the way, in the above operation, all the signal charges e _s and bias charges e _b must be transferred from the transfer section 3 to the output section 4, and for this purpose, in the potential state at time t ₃ in FIG. , the potential of the output gate 19 must always be lower than the potential of the gate 18, and the following relational expression must hold between the respective voltages.

V _pg −V _t1 ≧ −V _t2 ...(1) On the other hand, at the same time t ₃ , the potential at the output capacitance C ₀ when the signal charge e _s and the bias charge e _b are transferred is at least equal to the output gate 19 If the potential is not lower than the potential of , a part of the signal charge e _s or bias charge e _b will remain in the output gate 19, and for this reason, the potential state of time t 2 or _{t 3 will} change after passing through the potential states of time t ₄ and t ₁ . When the potential state is reached, the signal charge e _s and bias charge e _b of the output gate 19 will be mixed into the signal charge e _s and bias charge e _b transferred to the final stage gate 18. Become. From this, V _r −Q _d /C ₀ ≧V _pg −V _t1 ...(2) [However, Q _d must be the maximum amount of the total charge amount of the signal charge e _s and the bias charge e _b ] No. Therefore, (1) and (2) above
From the equation, we get the following equation:

V _r ≧ −V _t2 +Q _d /C ₀ ...(3) By the way, in general, in order to improve the transfer characteristics of an embedded channel CCD, the threshold value V _t2 needs to be set to a low value (large value in the negative direction). As an example, it is set to -7(v). Also, the output capacitance C ₀
The smaller the noise, the better. For example,
It is set at 0.05 (pF). Therefore, when Q _d is set to 0.2 (pC), from the above equation (3), V _r ≧11 (v). This number is just an example, but in short, for horizontal transfer
If you try to improve the performance of CCD1 (transfer characteristics, noise, dynamic range, etc.), the reset voltage VR will inevitably become higher.

On the other hand, in general, in a video camera, a stable voltage of about 9 (V) is created from the unstable power supply voltage of 10 to 13 (V) supplied from a video tape recorder, and this is used as the power supply voltage. For this purpose, for example, as mentioned above, in order to obtain the DC reset voltage VR of 11(v), the DC voltage of 9(v) above is converted into a pulse voltage of an appropriate frequency, and this is passed through a transformer. After boosting the voltage, it is necessary to use a booster circuit for detection and smoothing, which inevitably increases the circuit scale of the video camera and increases power consumption.

Next, the coupling part 5 which also requires high voltage.
(FIG. 1) will be explained using FIGS. 5 to 7.

FIG. 5 is an equivalent circuit diagram showing an example of the coupling section 5, in which 29 to 32 are MOS transistors, 33 is a capacitor, 34 is the capacitance of the vertical signal line 9 (FIG. 1), and 18 is shown in FIG. This is the gate of the transfer section 3.

The coupling section 5 includes MOS transistors 29 to 32 and a capacitor 33, and transfers the signal charge of the vertical signal line capacitor 34 to the gate 18 of the transfer section 3 to which the drive pulse φ ₁ is supplied. At this time, the transfer efficiency is increased using bias charges, but in order to transfer the signal charges from the vertical signal line capacitor 34 to the coupling part 5,
The internal bias charge of the capacitor 33 is injected into the vertical signal line capacitance 34, and in order to transfer the signal charge from the coupling part 5 to the gate 18, the bias charge (hereinafter referred to as CCD) is transferred from the gate 18 to the capacitor 33.
bias charge) is injected. When injecting the CCD bias charge from the gate 18 to the capacitor 33, the MOS transistor 32 must be driven with a large amplitude driving pulse _T1 , as will be described later.

6 is a timing chart of each drive pulse in FIG. 5, and FIG. 7 is a potential diagram showing the potential state of each part in FIG. 5 at each time shown in FIG. The charge transfer operation shown in FIG. 5 will be explained using FIGS. In addition,
In FIG. 7, e _s is a signal charge, e _bi is an internal bias charge of the capacitor 34, and e _bc is a transfer unit 3 (first
Figure) CCD bias charge, e _o is a general negative charge,
V ₁₁ and V ₁₂ are the "H" and "L" voltage values of the drive pulse T ₁ , respectively, V _t9 is the threshold of the MOS transistor 32, and V _t2 is the threshold of the gate 18 as in FIG.

During the transfer of the signal charge described above in the transfer section 3 (FIG. 1), the drive pulses T ₁ , T ₂ , T ₃ ,
_T5 is "L" and drive pulse _T4 is "H", and the potential of each part of the coupling part 5 at this time is
It is becoming as in t ₁₁ . In this state,
The vertical signal line capacitor 34 has a signal charge e _b and a negative charge e _o
In addition, the capacitor 33 has a negative charge e _o
and internal bias charge e _bi . Further, the CCD bias charge e _bc present in the gate 18 is injected from the input section 2 after the charge transfer in the transfer section 3 is completed, and is a signal charge e bc that is injected from the input section 2 from the coupling section 5 to the transfer section 3. It is used for transfer and transfer of signal charges in the transfer section 3, and is equal to the bias charge e _b in FIG. Therefore, the potential state at time _t11 in FIG. 7 shows the state after all signal charges of the transfer section 3 have been transferred to the output section 4.

Next, when the drive pulse _T5 becomes "H" and the drive pulse _T4 becomes "L" (time _t12 ), the MOS transistor 2
9 decreases, the potential of capacitor 33 increases, and the internal charge of capacitor 33 increases.
e _bi is injected into the vertical signal line capacitor 34 through the MOS transistor 29.

Next, when the drive pulse T ₄ becomes “H” (time
t ₁₃ ), the potential of the capacitor 33 decreases,
The signal charge e _s is transferred from the vertical signal line capacitor 34 to the capacitor 33 together with the internal bias charge e _bi .

Next, when the drive pulses T ₅ and φ ₁ become “L” and the drive pulses T ₁ , T ₂ , and T ₃ become “H” (time
t ₁₄ ), the potential of the MOS transistors 30, 31, and 32 decreases, and the potential of the gate 18 increases. In this case, MOS transistor 32
The voltage value at "H" of the drive pulse _T1 is made sufficiently large so that the potential of the gate 18 is lower than that of the gate 18. For this purpose, the CCD bias charge e _bc of the gate 18 is transferred to the MOS transistor 32.

Next, the drive pulse _T1 becomes “L” (time
t ₁₅ ), the CCD bias charge e _bc is transferred from the MOS transistor 32 to the MOS transistor 31. and,
The drive pulse T ₂ becomes “L” (time t ₁₆ ), and the MOS
The potential of transistor 31 increases, so that CCD bias charge e _bc is injected into capacitor 33 through MOS transistor 30. At this time, the drive pulse φ ₁ becomes "H" and the potential of the gate 18 becomes low.

Next, the driving pulses T ₁ and T ₂ become “H” (time t ₁₇ ), and the potential of the MOS transistors 31 and 32 decreases while the potential of the MOS transistor 30 is low, and the signal charge of the capacitor 33 decreases.
e _s and CCD bias charge e _bc are MOS transistor 3
0, 31, and 32 to the gate 18. Then, the drive pulses T ₁ , T ₂ , and T ₃ become “L” (time t ₁₈ ), the transfer section 3 starts operating, and the signal charge e _s and CCD bias charge e _bc are As explained in the figure, it is transferred horizontally.

By the way, as shown in the potential diagram at time _t11 in FIG. 7, a potential step 35 occurs at the boundary between the MOS transistor 32 and the gate 18. This occurs because impurity ions implanted into the p-type well 15 (FIG. 2) to form the gate 18 have entered a part of the MOS transistor 32. Each MOS transistor and gate is formed by patterning using a photomask, but taking into account the misalignment of the photomask,
Even in the worst case, in order to implant the desired impurity ions into the entire area of the gate 18, the region where the impurity is implanted will inevitably partially overlap the region of the MOS transistor 32. . That is, in order to inject the CCD bias charge e _bc into the coupling part 5, there must be no potential barrier between the gate 18 and the MOS transistor 32, and in order to avoid this, the gate 1
The impurity ions implanted into the entire area of MOS transistor 32 have no choice but to be implanted into a part of the region of MOS transistor 32 as well.

The potential difference between this potential step 35 is V _t2 , and when the potential of the MOS transistor 32 becomes lower than the potential of the gate 18 at time _t14 , a potential hole 36 with a depth of V _t2 is created between them. , a charge will enter into this.

During horizontal charge transfer in the transfer section 3 (FIG. 1), the gate 18 and the MOS transistor 32
A potential hole is created between the transfer charge (i.e., the signal charge e _s and
Experiments conducted by the inventors have revealed that when CCD bias charge e _bc ) enters, the transfer efficiency drops sharply.
This is thought to be because there is a large potential barrier on both sides of this potential hole in the charge transfer direction (that is, in the horizontal direction) in the transfer section 3, and the charge that enters this potential hole cannot cross this potential barrier. It will be done.

By the way, during the horizontal charge transfer operation of the transfer section 3, the drive pulse _T5 is "L", the potential of the MOS transistor 32 is ( _V12 - _Vt9 ), and the potential at the bottom of the step 35 of the potential is "L". is lower than this by −V _t2 (V ₁₂ −V _t9
−V _t2 ). At this time, in order to prevent transfer charges from entering the potential step portion 35 from the gate 18 (that is, the gate 18,
In order to prevent potential holes from forming between the MOS transistors 32), if the maximum voltage value due to the transferred charge in the gate 18 is V _s1 , then V ₁₂ −V _t9 −V _t2 ≦−V _t2 −V _s1 ...(4) must be satisfied. Now, V _t9 =2(v),
When V _s1 =1.5 (v), the “L” voltage value V ₁₂ of the drive pulse T ₁ needs to be 0.5 (v) or less.

In addition, in order for the CCD bias charge e _bc to be injected from the gate 18 to the coupling portion 5, the driving pulse T ₁ must be “H” as in the potential state at time t ₁₄ .
From the potential of the MOS transistor 32 (V ₁₁ −V _t9 ) when the _voltage becomes “L”, the potential of the gate ₁₈ (−V _t2 ) must be high.
Therefore, when the voltage value due to the CCD bias charge e _bc is V _s2 , the following must be satisfied: V ₁₁ −V _t9 −V _s2 ≧−V _t2 (5). Now, V _t2 =-7
(v), V _s2 = 1.5(v), and as above, V _t9
=2(v), the "H" voltage value _V11 of the drive pulse _T1 must be 10.5(v) or more.

As mentioned above, the drive pulse T ₁ is 0.5(v) at “L”
Hereinafter, since "H" is 10.5 (v) or more, the amplitude must be increased to 10 (v) or more. For this reason, video cameras with a power supply voltage of 9(V) still require a booster circuit.

[Purpose of the invention]

The purpose of the present invention is to eliminate the drawbacks of the above-mentioned prior art,
An object of the present invention is to provide a driving method and a driving circuit for a solid-state image sensor, which can use a low power supply voltage, have a small circuit scale, and reduce power consumption.

[Summary of the invention]

To achieve this objective, the present invention applies a high level pulsed voltage higher than the power supply voltage for horizontal transfer.
The feature is that the reset voltage is used for the output section of the CCD.

Further, the present invention supplies the output pulse of the pulse generation circuit to a level setting circuit to which a power supply voltage is supplied, increases the high level of the output pulse to a potential higher than the power supply voltage, and increases the output pulse of the level setting circuit. is the input voltage of the driven part driven at a high voltage.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 8 is a timing chart showing an embodiment of the method for driving a solid-state image sensor according to the present invention. This embodiment is for the horizontal transfer of Figures 1 and 2.
This relates to the reset voltage VR at the output section 4 of the CCD 1. In FIG. 8, 1H indicates a horizontal period, and HBL indicates a horizontal retrace period.

As explained earlier, the output capacity of the output section 4
In order to reset _C0 , the reset voltage VR must normally be set higher than the power supply voltage of the video camera. In the previous example, the power supply voltage is 9(v), while the reset voltage VR is
11(v) or higher.

In this embodiment shown in FIG.
As VR, a pulse voltage is used which becomes "L" during a part of HBL but becomes "H" during the other period. In this case, the "H" voltage of the reset voltage VR is higher than the power supply voltage of the video camera, and the output capacitance is
Set _C0 so that it can be reset to a desired potential.

In a solid-state image sensor, HBL is a period during which signal charges from the photoelectric conversion section 8 (Fig. 1) are transferred to the horizontal transfer CCD 1 through the coupling section 5 (Fig. 1); has not been carried out. Therefore, in the output section 4, the output capacity
There is no need to reset C ₀ ; therefore,
The reset voltage VR may have any voltage value, and may be less than or equal to the voltage value required to reset the output capacitance _C0 . From this, the reset voltage
The “L” period of VR is set within HBL.

FIG. 9 is a circuit diagram showing an embodiment of a driving circuit for a solid-state image sensor according to the present invention for forming the pulse-like reset voltage VR shown in FIG.
37 is a pulse generation circuit, 38 is a capacitor, 39
is a diode, 40 is a capacitor, 41 and 42 are resistors, 43 is a power supply, 44 is a solid-state image sensor,
27 is an input terminal for the reset voltage VR shown in FIG.

In FIG. 9, the pulse generation circuit 37 is "L"
generates periodic pulses within the HBL. The "L" potential is zero (v), and the "H" potential is (V _r -V ₄ )(v). However, V _r is the reset voltage
This is the “H” potential of VR, and 0V ₄ <V _r .

On the other hand, the power supply 43 is, for example, a voltage V _dd (in the previous example, 10
It is a virtual power supply that generates a voltage equal to ~13(v), and this power supply 43, a capacitor 40, and a resistor 4
1 and 42 constitute a voltage source for the video camera, and generate a stable voltage V ₄ (9(v) in the previous example). Also, capacitor 38 and diode 3
9 forms a clamp circuit.

Pulses from the pulse generating circuit 37 are supplied to a capacitor 38, and a power supply voltage V ₄ obtained at the capacitor 40 is supplied to a diode 39. As a result, the "L" level of the pulse is fixed at the voltage _V4 , and at the same time, the potential of the "H" level becomes VR. In this way, the reset voltage VR can be set to a higher voltage than the power supply voltage _V4 . When the pulse generation circuit 37 is driven by the voltage V _dd of the power supply 43, the amplitude of the pulse generated by the pulse generation circuit 37 is approximately V _dd
Since the reset voltage VR can be set to the voltage V _dd
It can be set to a value nearly twice that of .

In this way, without using a booster circuit,
It is possible to obtain a reset voltage VR that is sufficiently higher than the power supply voltage.

Figure 10 shows that the reset voltage VR (Figure 8) is "L".
FIG. 3 is a potential diagram showing the potential state of each part in FIG. 2 when

In the same figure, when the reset voltage VR is "L", the potential of the output capacitance _C0 is equal to the gate 1.
It's not a problem unless you exceed the potential of 7.
Therefore, V ₄ >−V _t1 must hold. Now, assuming that V _t1 =-4(v), the "L" level of the reset voltage VR needs to be 4(v) or more.

FIGS. 11 and 12 are circuit diagrams showing other embodiments of the driving circuit for a solid-state image sensor according to the present invention.

The embodiment shown in FIG. 11 uses a transistor 45 instead of the diode 39 in the embodiment shown in FIG.
When the amplitude of VR is not very large and is within the range of the reverse emitter-base breakdown voltage of the transistor 45, there is an advantage that the clamping operation is fast.

The embodiment shown in FIG. 12 similarly uses a Zener diode 46 in place of the diode 39 shown in FIG.
Although it can be used only when the average voltage of VR is lower than the voltage V _dd of the power supply 43, it has the feature that "H" of the reset voltage VR can be directly determined to a desired potential. In addition, 47, 48, 4
9 is resistance.

Even in the embodiments shown in FIGS. 9, 11, and 12 shown above, it has been confirmed through experiments by the inventors that there is almost no increase in noise in the solid-state image sensor 44. In principle, there should be some increase in noise compared to the case where In order to prevent this increase in noise, it is effective to clip the "H" level of the pulsed reset voltage VR. Examples for this purpose are shown in FIGS. 13 and 14.

In the embodiment shown in FIG. 13, the clip potential is set using resistors 50 and 51 and a capacitor 52, and
4. The Zener diode 53 clips the "H" level of the pulse whose level is set by the capacitor 38 and the diode to form a reset voltage VR whose "H" is a predetermined potential. For this purpose, the amplitude of the pulse generated by the pulse generator 37 is (V _r
−V ₄ ) slightly larger than

The embodiment of FIG. 14 uses diodes 55 to 58 in place of the Zener diode 53 of FIG. 13, and provides the same effect as the embodiment of FIG. 13.

In addition, in Fig. 13 and Fig. 14,
Parts corresponding to the figures are given the same reference numerals.

FIG. 15 is a timing chart showing another embodiment of the method for driving a solid-state image pickup device according to the present invention, and drive pulses corresponding to those in FIG. 2 are given the same reference numerals.

In this embodiment, the reset voltage VR is a pulse voltage having the same frequency as the reset gate pulse RG,
The reset voltage VR is set to "L" during the period when the reset gate pulse RG is "L" (that is, when the MOS transistor 20 (FIG. 2) is off).

The drive circuit for realizing this embodiment can have the same circuit configuration as the embodiments shown in FIGS. 9 and 11 to 14, and since the pulses are high-speed, There is an advantage that the capacitance of the capacitor 38 can be designed to be small. However, since the pulse is high-speed, noise tends to increase, and the amplitude of the reset voltage VR needs to be smaller than the amplitude of the reset gate pulse RG to some extent, so compared to the embodiment shown in FIG. Therefore, there is a drawback that the upper limit value of the reset voltage VR becomes low.

Figure 16 shows the second waveform at times t ₄ and t ₅ in Figure 15.
4 is a potential diagram showing the potential state of each part in the figure, and parts corresponding to those in FIG. 4 are given the same reference numerals.

In FIGS. 2, 15, and 16, when the reset gate pulse RG is "L", the input terminal 27 and the output capacitance C ₀ are isolated by the potential (V ₃ -V _t3 ) of the MOS transistor 20. , drive pulse φ ₁ is “L”, drive pulse φ ₂
is "H" and the reset voltage VR is "H" (time t ₄ ), a signal charge e _s and a bias charge e _b are present at the gate 18 of the transfer section 3. Drive pulse _φ1 is “H”, drive pulse _φ2 is “L”, reset voltage VR
When becomes “L” (time t ₅ ), the signal charge e _s and the bias charge e _b are transferred from the gate 18 to which the drive pulse φ ₂ is applied to the gate ₁₈ to which the drive pulse φ 1 is applied, and the final stage Charge is similarly transferred from the gate 18 to the output capacitor C ₀ , but at the same time, the potential of the input terminal 27 also increases. At this time, in order to prevent negative charge e _o from transferring from the input terminal 27 to the output capacitor C ₀ , the "L" potential V ₅ of the reset voltage VR is set so that the potential V ₅ of the input terminal 27 at this time is It is set to be lower than the potential (V ₃ −V _t3 ) of the MOS transistor 20.
Also, set the reset gate pulse RG to “H”,
Since the reset voltage VR becomes "H" and the output capacitance C ₀ is reset, the reset voltage VR is changed so that the potential V _r of the input terminal 27 exceeds the potential (V ₂ - V _t3 ) of the MOS transistor 20. The "H" potential V _r must be set.

Therefore, if the amplitude of the reset gate pulse RG is limited by the voltage V _dd of the power supply 43 (eg, FIG. 9), the amplitude of the reset voltage VR must be made slightly smaller than this voltage V _dd . Here, the “H” potential V _r of the reset voltage VR is defined as the voltage
A value slightly less than twice V _dd (for example, 1.5
can be increased up to 2 times).

FIG. 17 is a circuit diagram showing still another embodiment of a driving circuit for a solid-state image sensor according to the present invention.
9 is a pulse generation circuit, 60 is an amplifier, 61 is a capacitor, 62 is a diode, 63 is a capacitor,
64 and 65 are resistors, 66 is an input terminal, and the ninth
Parts corresponding to the figures are given the same reference numerals.

FIG. 18 is a timing chart of pulses at various parts in FIG. 17, and the symbols corresponding to the pulses in FIG. 17 are assigned.

This embodiment is a drive circuit that generates the drive pulse _T1 shown in FIG. 5, and the input terminal 66 of the solid-state image sensor 44 is connected to the gate of the MOS transistor 32 shown in FIG. In addition, the capacitor 63,
The resistors 64 and 65 form a stable voltage _V8 from the voltage _Vdd of the power supply 43. The pulse a generated by the pulse generation circuit 59 has a period of 1H and becomes "H" during HBL (horizontal blanking period), and the potential of "L" is zero (v),
The potential of “H” is V ₆ (v).

Pulse a from pulse generating circuit 59 is supplied to capacitor 61, and "L" is clamped to V ₈ (v) by voltage V ₈ supplied to capacitor 62.
As a result, V ₈ (v) at “L” and V ₇ (v) at “H” (=V ₆ +
A pulse b of V ₈ ) is obtained.

This pulse b is supplied as the power supply voltage of the amplifier 60. Since the "H" periods of pulse b and pulse a match, the amplifier 60 obtains pulse c of zero (v) when it is "L" and V ₇ (v) when it is "H". This pulse c is supplied to the input terminal 66 as a drive pulse _T1 .

Now, the power supply voltage of the pulse generation circuit 59 is set to the power supply 4.
3, the "H _" potential of pulse a can be made equal to V _dd , and the voltage of pulse b
Since the "L" potential of can also be set to a value close to V _dd , the amplitude V ₇ of the pulse c (that is, drive pulse T ₁ ) can be set to a value close to 2V _dd .

FIG. 19 is a circuit diagram showing still another embodiment of a driving circuit for a solid-state image sensor according to the present invention,
7 is a pulse generation circuit, 68, 69, 70 are resistors,
71 is a capacitor, 72 is a transistor,
Portions corresponding to those in FIG. 17 are given the same reference numerals.

FIG. 20 is a timing chart of pulses in each part of FIG. 19, and pulses corresponding to those in FIG. 19 are given the same reference numerals.

In FIGS. 19 and 20, a pulse generating circuit 67 generates a pulse d similar to the output pulse a of the pulse generating circuit 59 in FIG. 17, and a pulse e which is an inverted version of this pulse d. pulse e
is clamped by the capacitor 71 and the diode 62 at its “L” level (zero (v)) at the voltage V ₈ obtained by the capacitor 63, and the “L” potential becomes V ₈
(v), a pulse f whose "H" level is V ₇ (v) (=V ₆ +V ₈ ) is obtained. This pulse f is resistor 68, 69
is subtracted by the pulse d supplied to the inverting amplifier consisting of the transistor 72, and a pulse g whose "L" potential is zero (v) and "H" potential is V ₇ (v) is obtained. This pulse g is supplied to the input terminal 66 as a drive pulse _T1 .

Note that the pulse e does not necessarily have to be in an inverted relationship with the pulse d, and the "H" period of the pulse e may be wider than the "L" period of the pulse d.

By the way, in the embodiments shown in FIGS. 17 and 19, the power supply voltage of the amplifier 60 and the transistor 72 is a pulse voltage, so the noise can be reduced by grounding the power supply like an ordinary DC power supply. cannot be measured. For this purpose, the input terminal 66
The noise contained in the pulses c and g (that is, the drive pulse T ₁ ) supplied to the drive pulse T 1 increases somewhat compared to the prior art. However, MOS transistor 32
The operation of (FIG. 5) is hardly affected by noise. That is, in FIG. 5, since the MOS transistors 29 and 30 directly control the negative charge flowing out from the adjacent capacitors by their gate potentials, the drive pulses T ₅ and T ₃
When noise is mixed in, the solid-state image sensor responds sensitively to this noise, and the noise in its output signal increases. On the other hand, the MOS transistor 32 simply digitally opens and closes the flow of negative charges, so the drive pulse T ₁
Even if noise is mixed into the image sensor, it hardly increases the noise in the output signal of the solid-state image sensor. For this reason as well, the embodiments shown in FIGS. 17 and 19 are suitable as a drive circuit for the MOS transistor 32.

The embodiments of the present invention have been described above.
It goes without saying that the embodiment shown in FIG. 9 can be applied not only as a drive circuit for a solid-state image sensor but also as a pulse amplification circuit in general.

〔Effect of the invention〕

As explained above, according to the present invention, the output section of the CCD can be reset with a reset voltage higher than the power supply voltage without using a booster circuit.
The performance of CCD has improved, and low power supply voltage and low power consumption can be achieved with a small-scale circuit configuration.
It is possible to provide a driving method and a driving circuit for a solid-state image sensor that have excellent functions except for the drawbacks of the above-mentioned conventional techniques.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional solid-state image sensor, Fig. 2 is a block diagram showing the vicinity of the output section of the charge transfer device for horizontal transfer shown in Fig. 1, and Fig. 3 is a block diagram showing the vicinity of the output section of the charge transfer device for horizontal transfer shown in Fig. 2. 4 is a potential diagram showing the potential state of each part in FIG. 2 at each time in FIG. 3, and FIG. 5 is an equivalent block diagram showing an example of the coupling part in FIG. 1. , FIG. 6 is a timing chart of each drive pulse in FIG. 5, and FIG. 7 is a timing chart of each drive pulse in FIG.
FIG. 8 is a timing chart showing an embodiment of the method for driving a solid-state image sensor according to the present invention; FIG. 9 is an example of a driving circuit for a solid-state image sensor according to the present invention. FIG. 10 is a potential diagram showing the potential states of each part in FIG. 2 during the low level period of the reset voltage in FIG. A circuit diagram showing another embodiment of the circuit, FIG. 15 is a timing chart showing another embodiment of the method for driving a solid-state image sensor according to the present invention, and FIG. 16 shows each part of FIG. 2 at each time in FIG. 15. FIG. 17 is a circuit diagram showing still another embodiment of the solid-state image sensing device drive circuit according to the present invention, FIG. 18 is a timing chart of pulses in each part of FIG. 17, and FIG. 19 is a potential diagram showing the potential state of FIG. 20 is a circuit diagram showing still another embodiment of a driving circuit for a solid-state image sensor according to the present invention, and FIG. 20 is a timing chart of pulses at various parts in FIG. 19. DESCRIPTION OF SYMBOLS 1...Horizontal transfer charge transfer device, 2...Input section, 3...Transfer section, 4...Output section, 5...Coupling section, 17, 18...Gate, 20...MOS transistor, 23, 24 ...Drive pulse input terminal,
26...Reset gate pulse input terminal, 27...
...Reset voltage application terminal, 29-32...MOS
Transistor, 37... Pulse generating circuit, 44...
...Solid-state image sensor, 59...Pulse generation circuit, 60
...Amplifier, 67...Pulse generation circuit.

Claims (1)

[Claims] 1. A signal transferred from a photoelectric conversion section via a vertical transfer means, using a CCD as a horizontal transfer means,
In a method for driving a solid-state image sensor that transfers data in the horizontal direction, the reset voltage of the output section of the CCD is a pulse voltage, and a voltage at a predetermined level is used so that the high level of the pulse voltage is higher than the power supply voltage of the solid-state image sensor. 1. A method for driving a solid-state image sensing device, comprising: resetting the output section of the CCD to a high level higher than the power supply voltage of the pulse voltage. 2. The signal transferred from the photoelectric conversion unit via the vertical transfer means is transferred using the CCD as the horizontal transfer means.
A drive circuit for a solid-state image sensor that transfers data in the horizontal direction includes a pulse voltage generation circuit, and a voltage at a predetermined level that generates the pulse voltage.
It is characterized by comprising a level conversion circuit that converts the high level to be higher than the power supply voltage of the solid-state image sensor, and resetting the output section of the CCD to the high level of the output pulse voltage of the level conversion circuit. A drive circuit for a solid-state image sensor.