JPH0527956A - Processor for controlling engine - Google Patents

Abstract

PURPOSE:To uniform the processing load of a high-speed processor and to effectively utilize the processor by adding idling control as a load in addition to a drive processing having tolerance in low-speed rotation. CONSTITUTION:This processor is constituted of a host processor and a co- processor having a data flow processor(DFP) 10 as the numerical calculation processor of high performance. Namely, the DFP 10 is added to a host 19 as the co-processor, a drive processing routine is processed by the co-processor DFP 10 and in an idling state, an idling control routine is processed by the DFP 10. Corresponding to the increase of the processing load in the case of high-speed rotation and the decrease of the processing load in the case of low- speed rotation, the idle control routine is processed in the comparatively low- speed rotation so as to uniform the processing load of the co-processor DFP 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an engine control processor, and more particularly to an engine control processor having an improved electronic control program processing system for an automobile engine control device.

[0002]

2. Description of the Related Art FIGS. 8 and 9 show, for example, Japanese Patent Application No. 2-227.
It is a figure which shows the conventional engine control device for motor vehicles shown by No. 80.

In the figure, 100 is an engine control processor, 101 is a power transistor, 102 is an ignition coil, 103 is a distributor, 104 is a spark plug, 105 is an injector drive valve, and 110.
Is an input / output unit of the processor, 111 is an analog / digital converter (A / D converter), 112 is a timer, 11
3 is a counter, 114 is a ROM, 115 is a RAM, 11
The 6 interrupt control unit 117 is a CPU.

Further, FIG. 10 shows an engine control device for an automobile which uses a data flow processor (DFP) as a high speed operation coprocessor in the engine control processor 100 of FIG.

In the figure, 100 is a control processor,
10 is a data flow processor (DFP), 11 is a packet merging unit (J), 12 is a packet branching unit (B), 13
Is a program storage unit (PS), 14 is an ignition processing unit (F)
C), 15 is an arithmetic processing unit (FP), 16 is a queue buffer (Q), and 17 is an input interface (I) of the DFP 10.
/ F _IN ), 18 is the output interface (I
/ F _OUT ), 19 is a host processor that controls the entire control processor 100. Also, 110-
Reference numeral 116 is substantially the same as that designated by the same reference numeral in FIG.

Next, the operation will be described. First, the case of FIG. 9 will be described. Engine control processor 100
The main input signals to the engine are crank angle sensor signals that give information on engine speed and ignition timing,
There are an intake air amount signal corresponding to the engine load, a water temperature signal corresponding to the engine temperature, and a battery voltage which is a battery voltage.
The output signals include an ignition control signal and an injector drive signal.

The engine control processor 100 detects the state of the engine, the engine speed, the intake air amount, and the water temperature from sensors, and calculates the optimum ignition timing from the preset ignition timing based on these detected values. The primary current of the power transistor 101 is cut off and the ignition coil 102 is driven to control the ignition timing. Of the input signals, the idling detection signal is a digital value,
The state is simply shown and read via the I / O 110, and the intake air amount signal, the water temperature signal, and the battery signal are input as analog values and converted into digital values by the A / D converter 111. The crank angle sensor signal is first input to the interrupt control unit 116 to generate an interrupt, divided by a counter 113 that measures the crank angle pulse a predetermined number of times, and then input to the interrupt control unit 116. Some are interrupted and generate an interrupt.

A method of calculating the ignition timing using these signals will be described. First, the basic ignition timing (phase) θ _B is obtained from the intake air amount signal and the crank angle signal value.
A water temperature correction (phase) θ _WT is added to this value by a water temperature signal which is an engine warm-up state signal. Top dead center -5 °
From these times, a correction value that goes back further is determined from these signals. Ignition timing (phase) θ _ADV is θ _ADV = θ _B
It is _calculated by + θ _WT . The actual ignition timing is determined based on the crank angle sensor signal. Figure 1
FIG. 1 shows a conceptual diagram of this correction processing. These arithmetic processes are performed by executing a program in the memory of the engine control processor.

The calculation of the injector pulse for intake / fuel control is performed as follows. Pulse width Ti
Is

Ti = Fuel × K _ar × K _wt × K _VB

And is calculated by the intake air amount signal, the water temperature signal, the battery voltage, the crank angle sensor signal and the idle signal.

Further, the software configuration in this calculation is as shown in FIG. It is also determined by the idle detection sensor whether or not the fuel is cut in the interrupt routine of FIG.

In addition, this software is executed by using the entire crank angle sensor (SGT) signal cycle, and three cycles of fuel injection, ignition timing, and asynchronous injection are repeated.

Next, the operation in the case of FIG. 10 will be described. As in the case of FIG. 9, the control unit 100 has a crank angle sensor signal, an intake air amount signal corresponding to the engine load, a water temperature signal corresponding to the engine temperature, and a battery voltage as input signals. The output signals include an ignition control signal and an injector drive signal. The main routine job and the interrupt job are shown in the example of Fig. 12 (a) and (b). The job of Fig. 12 (a) constantly calculates, but requires the input signal when the crank angle interrupt signal is generated. The data is taken in and the processing of FIG. 12 (b) is executed.
At this time, the Neumann processor 19 operates the peripheral input / output 11
0, A / D 111, timer 112, counter 113 information is received, operation packet is generated for DFP 10, and DFP 1 is sent via interface I / F _IN 17.
Supply to 0. The DFP 10 displays the calculation result on the I / F _OUT 18
, And Neumann processor 19 receives it due to the interrupt generated thereby. The Neumann processor 19 outputs this result as an ignition control signal or an injector drive signal.

The data processing in the DFP 10 is performed by the tag of the packet, and the Neumann processor 19 attaches the destination tag and sends the data to the DFP 10. Further, the data received by the Neumann processor 19 from the DFP 10 has a tag, so that the Neumann processor 19 can distinguish what data is received from the DFP 10 from the ignition control signal or the injector drive signal.

[0016]

In the conventional engine control system, a single processor or a coprocessor is used to control the fuel injection time and the ignition timing for engine control according to the crank angle sensor signal corresponding to the number of revolutions. It was a calculation. However, control at low speed idle, etc.
When the new engine control is added, the program processing and load distribution of the host processor and the coprocessor are not fully considered, and the high-speed processor performs extremely high-speed and large-capacity data processing when the engine rotates at high speed. However, there is a problem in that it is not sufficiently utilized at low speed rotation, and only a simple control by turning on / off the air conditioner is performed.

The present invention has been made to solve the above problems, and in an engine control processor equipped with a high-performance processor, the high-performance processor is effectively used, and various controls at the time of idling and To obtain a control processor for an automobile that can perform other control, for example, extremely high-performance, comfortable ride, high-performance, and high-value-added control that accurately responds to human sensitivity by utilizing modern control theory. To aim.

[0018]

According to another aspect of the present invention, there is provided an engine control processor, which comprises a high speed processor having an arithmetic processing capability adapted to drive processing at high engine speed, wherein the high speed processor is an engine. At the time of high rotation of the vehicle, only the drive processing program is executed, and at the time of low rotation of the engine, when the output is supplied for the purpose other than traveling of the vehicle, the program for performing predetermined control at the time of idling to the drive processing program. Is controlled so as to execute an idling control program to which is added.

[0019]

The engine control device according to the present invention comprises a high-speed processor having an arithmetic processing capacity adapted to drive processing at a high engine speed, wherein the high-speed processor is:
When only the drive processing program is executed and its output is supplied when the engine is running at a low speed for purposes other than running the vehicle, an idling control program is added to the drive processing program to perform a predetermined control during idling. Since it is controlled so as to be executed, the processing load of the high-speed processor can be made uniform, and its effective use can be achieved.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below. FIG. 1 is a diagram showing the configuration of an engine control processor according to an embodiment of the present invention. In FIG.
The same symbols as are the same or corresponding parts. As a high-speed arithmetic processor used as a coprocessor, a data flow processor (DFP) is used as in the conventional example shown in FIG. Reference numeral 118 denotes a packet interface (I / F), which collectively shows 17 and 18 in FIG.

Next, the operation and operation of the embodiment will be described. As shown in FIG. 1, the data flow processor D is not a single processor but a high-performance numerical arithmetic processor.
It is configured as a host + coprocessor configuration engine control processor having an FP10.

The basic engine control operation is almost the same as the conventional example. That is, the fuel injection amount and the ignition timing required for driving are performed by giving parameters to the DFP 10 using the crank angle sensor (SGT) signal corresponding to the engine rotation, and the calculation result is returned to the host processor 19 and the device Given to. FIG. 2 shows the host processor 19, the packet I / F 118, and the DFP 1 at this time.
It is a processing flow chart which shows exchange of data between 0s. In this embodiment, the intake air amount per stroke (instantaneous value:
(A / N) _R ) and the SGT cycle (T _ne ) are obtained by the host processor, and 12 pieces of data are sent to the packet I / F 118. This data is sent to the packet I / F 11
8 is converted into a packet format for DFP10 and converted to DFP1.
Send to 0. The DFP 10 calculates the fuel injection time T and the ignition timing θ in the same manner as the conventional calculation method. DFP1
0 sends this calculated data to the host processor 19 via the packet I / F 118.

FIG. 3 is a diagram showing the processing of FIG. 2 in correspondence with SGT (crank angle signal), and BTDC 75 ° of SGT.
This means that the crank angle interrupt occurs at the timing of CA (75 ° before the top dead center of the crank angle), and the processing from the host processor starts.

The processing shown in FIGS. 2 and 3 is a driving processing for driving the automobile by the engine output and is processing for each SGT cycle. Therefore, the processing is proportional to the engine speed (Ne). The processing amount increases.

FIG. 4 is a diagram showing a flow chart of the program processing operation of this embodiment. This program processing operation is executed in response to the crank angle interruption as shown in FIG. As shown in FIG. 1, a key switch signal, a neutral signal, etc. are input to the host processor 19 via the I / O 110, and a processing routine is selected according to these signals. If the key switch is off, the fuel is cut. If the key switch is on and the idle switch is off, it is in the drive state, so it is processed by the drive processing routine, and when the idle switch is on and not in neutral, it is also processed by the drive processing routine.
When the idle switch is on and is in neutral, the idling control routine is executed.

When the idling process is to be driven in an idling state such as air conditioner drive, steering wheel drive, cooling fan drive, etc., this is optimally controlled according to various input conditions to ensure idle stability, and It is necessary to guarantee the performance of various devices at idle. The control for this is described by a state equation including an eight-dimensional matrix operation, and it is necessary to perform this in a fine range of the crank angle, resulting in a very large processing load.

FIG. 5 is a diagram showing the processing contents of the DFP 10 of this embodiment in the case of high rotation and low rotation such as idling. FIG. 5A shows the contents of the calculation performed by the DFP 10 which is the coprocessor when Ne = 800 rpm, and FIG. 5B shows the contents of the calculation which is performed by the DFP 10 which is the coprocessor when Ne = 8000 rpm.
In the case of Ne = 8000 rpm shown in FIG. 5B, the drive processing calculation occupies most of the crank angle, and the processing amount is such that no other processing can be added. On the other hand, when Ne = 800 rpm shown in FIG. 5 (a), there is a time margin between the driving process and the next driving process.
During this time, the DFP 10, which is the coprocessor, performs the operation of idling control. As described above, when the engine speed is low, both the engine control operation equivalent to the drive processing operation at high engine speed and the idling control operation are performed as the idling control routine by SG.
Corresponding to T.

As described above, in this embodiment, in the host processor 19 to which the DFP 10 is added as a coprocessor, the drive processing routine is processed by the coprocessor,
In addition, in the idling state, the idling control routine is processed by the coprocessor so that the processing load increases at high speed rotation and the processing load decreases at low speed, so that the idle control routine is processed at relatively low speed. Since the coprocessor has a uniform processing load, a highly efficient engine control processor can be realized.

When the data flow processor is used, its processing load is basically proportional to the SGT cycle, and idling control can be performed corresponding to the SGT. Of course, similar processing can be realized in the case of a digital signal processor (DSP) using interrupts.

Next, a second embodiment of the present invention using a digital signal processor (DSP) as a coprocessor will be described.

FIG. 6 is a diagram showing an engine control processor according to a second embodiment of the present invention in which a digital signal processor is used as a coprocessor. In the figure, 21
0 is a digital signal processor (DSP), 211
Is a dual port RAM, and 212 is a DSP interrupt circuit. The dual port RAM is different from the previous embodiment in that the interface with the host processor 19 is taken, and the DSP interrupt circuit 212 to the DSP 210 simultaneously with the data input from the host processor 19.
Is interrupted. DS not shown
When data is sent from P210 to the host processor 19, there is no problem even if an interrupt is generated for the host processor interrupt control unit 116. The communication between the host processor 19 and the DSP 210 is a dual port RA.
This is done via M211. The internal software processing is the same as in the first embodiment. Although not shown, the host processor has an I
A key switch signal, a neutral signal, etc. are input via / O110, and a processing routine is selected according to these signals.

FIG. 7 is a diagram showing an engine control processor according to a third embodiment of the present invention. In the figure, 212 is a data multiplexer, 213 is an address multiplexer, 223 is a RAM, and 224 is a memory access control. is there. In this embodiment, the digital signal processor 210 is used as the coprocessor as in the second embodiment, but the RAM 223 is used instead of the dual port RAM used in the second embodiment.
Memory access control 22
4 is different from the data multiplexer 212 and the address multiplexer 213. The internal software processing in the third embodiment is the same as the second software.
Although it is almost the same as that of the first embodiment, since it does not depend on an interrupt in this embodiment, it is described by using the process of constantly polling the RAM address. Although not shown,
As in the case of FIG. 1, a key switch signal, a neutral signal, and the like are input to the host processor via the I / O 110, and the program processing operation is performed according to these signals.

In each of the above embodiments, the case where the idling control is added to the low rotation drive control has been described, but the process division for effectively utilizing the addition of the processor is not limited to this. It goes without saying that other control when the engine speed is low, for example, automatic tracking processing during non-acceleration and automatic tracking during vehicle congestion (vehicle distance control) can be applied in the same manner.

[0034]

As described above, according to the present invention, the processing of the engine control processor is divided into the driving processing and the idling control processing at the time of relatively low rotation, and only the driving processing is performed at the time of high rotation. , A sufficient processing load was secured, and idling control was added as a load in addition to the drive processing with a margin at low speed rotation, and the processing capacity of the arithmetic processor was configured to be effectively utilized from low speed to high speed. Therefore, it is possible to inexpensively supply a high-performance and high-performance engine control device.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an engine control processor according to a first embodiment of the present invention.

FIG. 2 is a processing flow chart of each processing unit in the embodiment of FIG.

FIG. 3 is a diagram showing the correspondence between the flow of processing shown in FIG. 2 and SGT.

FIG. 4 is a diagram showing a flowchart of a program processing operation of the embodiment of FIG.

5 is a diagram showing the processing contents in the case of high rotation and low rotation of the embodiment of FIG.

FIG. 6 is a diagram showing a configuration of an engine control processor according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of an engine control processor according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a conventional engine control processor.

FIG. 9 is a diagram showing an internal configuration of a conventional engine control processor.

FIG. 10 is a diagram showing an internal configuration of a conventional engine control processor using a data flow processor as a coprocessor.

FIG. 11 is a conceptual diagram of engine control correction.

FIG. 12 is a diagram showing a software configuration of a conventional engine control processor.

[Explanation of symbols]

 10 Data Flow Processor (DFP) 19 Host Processor 100 Engine Control 118 Packet Interface (Packet I / F) 210 Digital Signal Processor (DSP) 211 Dual Port RAM 212 DSP Interrupt Circuit 221 Data Multiplexer 222 Address Multiplexer 223 RAM 224 Memory Access Controller

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Shoichi Washino 8-1-1 Tsukaguchi Honcho, Amagasaki City, Hyogo Prefecture Sanryo Electric Co., Ltd. Industrial Systems Research Institute (72) Inventor Setsuhiro Shimomura Chiyoda Town, Himeji City, Hyogo Prefecture 840 Mitsubishi Electric Corporation Himeji Works (72) Inventor Yoshiaki Sugano 840 Chiyoda Town, Himeji City, Hyogo Prefecture 840 Mitsubishi Electric Corporation Himeji Works (72) Inventor Ikuo Nassa 840 Chiyoda Town, Himeji City, Hyogo Prefecture Mitsubishi Electric Shares Company Himeji Factory

Claims (1)

Claim: What is claimed is: 1. An engine control processor comprising a high-speed processor having an arithmetic processing capacity adapted to drive processing at high engine speed, wherein the high-speed processor is at high engine speed. In the case of running the drive processing program only and supplying the output for the purpose other than running the vehicle when the engine is running at low speed, the drive processing program is added with a program for performing predetermined control during idling. An engine control processor, which is controlled so as to execute a control program and has a uniform processing load.