JPH05275393A - Dry etching method - Google Patents

Abstract

PURPOSE:To improve mask-selectivity of a lower layer resist layer against a mask at the time of etching and to prevent resticking of sputter on a base material layer containing Cu, relating to a three-layer resist process. CONSTITUTION:A lower layer resist layer 3 on an Al-1% Si-0.5% Cu layer 2 is etched with HI/O2 mixture gas. I(iodine) is hard to chemically react with Si. Since Clx which is an etching reactive product can be used as a side wall protective film 6, irradiative ion energy required for anisotropic working is reduced. As a result, the selectivity against an SOG pattern 4a which is an etching mask improves. This is also effective when a base material layer is a Cu layer. In short, by overetching a lower resist layer with gas group containing HI while a wafer is heated, the Cu sputtered can be removed in the form of Cu2I2, thus, particle contamination is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method, and more particularly, to improving the selectivity with respect to a mask and the selectivity with respect to a base when etching a lower resist layer using a silicon oxide type intermediate layer as a mask in a three-layer resist process. The present invention also relates to a method of preventing the redeposition of the base material by sputtering.

[0002]

2. Description of the Related Art As semiconductor device design rules are highly miniaturized from sub-micron level to quarter-micron level, requirements for various processing techniques such as photolithography and dry etching are becoming more severe. .. In the photolithography technology, in recent years, the exposure wavelength has been shortened in order to obtain high resolution, and the step difference on the surface of the substrate has increased.
Adoption of processes is becoming mandatory. Multi-layer resist
The process is a method of using a combination of at least two types of resist layers, that is, a lower resist layer thick enough to absorb surface steps of a substrate and an upper resist layer thin enough to achieve high resolution.

A well-known method is described in J. Vac.
Sci. Tech. 16, (1979), p. 162
There is a so-called three-layer resist process reported in No. 0. This is a thick lower resist layer for flattening the surface steps of the substrate, a thin intermediate layer made of an inorganic material for forming a mask when etching the lower resist layer,
And a thin upper resist layer that is patterned by photolithography and development processing. In this process, first, the upper resist layer is patterned into a predetermined shape, the intermediate layer thereunder is patterned by RIE (reactive ion etching), and the upper resist layer and the intermediate layer are used as a mask. The lower resist layer is patterned by dry etching using O ₂ gas or the like.

By the way, in the step of etching the lower resist layer which is an organic material layer with O ₂ gas,
^{* In} order to prevent the deterioration of the pattern shape due to the isotropic combustion reaction due to (oxygen radicals), it is necessary to adopt the condition where the ion incident energy is increased to some extent. That is, the mean free path of ions and the self-bias potential V _dc under the conditions of low gas pressure and high bias power.
And the high anisotropy is achieved by sputtering utilizing the high kinetic energy of the ions.

However, the adoption of such etching conditions leads to a decrease in the selectivity with respect to the underlying material layer, which is also a factor that hinders the practical application of the multilayer resist process. This problem will be described with reference to FIG. Figure 3
(A) shows the state of the wafer on which the upper layer resist pattern 15 is formed in the three-layer resist process. The steps up to this point will be briefly described. First, the underlying material layer 12 that follows the step is formed on the SiO ₂ interlayer insulating film 11 having the step, and the step is absorbed so that the surface of the wafer can be flattened. A lower resist layer 13 having
Then, a thin SOG intermediate layer 14 made of spin-coated glass (SOG) is sequentially formed, and a thin upper resist layer is further formed on the SOG intermediate layer 14. The upper resist pattern 15 is obtained by patterning the upper resist layer by photolithography and development processing. The resolution of photolithography at this time is extremely high, and the upper layer resist pattern 15 has a clear edge with a width of 0.35 μm.

Next, the SOG intermediate layer 14 is patterned by RIE (reactive ion etching) using the upper resist pattern 15 as a mask to form an SOG pattern 14a as shown in FIG. 3B. This SOG
The pattern 14a also has a very clear edge.

Next, the lower resist layer 13 is etched by using O ₂ gas. In this etching process, the thin upper resist pattern 15 disappears halfway, and thereafter, only the SOG pattern 14a functions as an etching mask. Here, the lower resist layer 13 is a layer formed to have a film thickness sufficient to absorb the surface step difference of the wafer based on the purpose of the three-layer resist process. They are different, and the time required for etching is naturally different. For example, in the region corresponding to the upper part of the step of the base material layer 12, FIG.
Lower layer resist pattern 1 early as shown in
3a is completed (just etching state), and the underlying material layer 12 is exposed.

Subsequently, when overetching is performed to remove the residual portion 13b in the region corresponding to the lower portion of the step, the base material layer 12 is irradiated with ions having a large incident energy and sputtered at the upper portion of the step. It A part of the sputtered product is redeposited on the side wall portion of the lower resist pattern 13a to form a redeposited layer 12a as shown in FIG. 3 (d). Particularly when the underlying material layer 12 is a metal wiring material or the like, the redeposited material layer 12a is difficult to remove and becomes a source of particle contamination. Also, S
In addition to the OG pattern 14a receding by ion irradiation, the redeposited layer 12a described above thickens the substantial line width of the etching mask, so that a dimensional conversion difference is likely to occur.

The problem of reattachment as described above is described in, for example, Proceedings of the 33rd Joint Lecture in Applied Physics (Spring Annual Meeting 1986) p. 542, Abstract No. 2p-Q-8 has been pointed out and is well known. Reattachment layer 28
Although it is clear that the reduction of incident ion energy is effective in suppressing the formation of helium, this causes the above-mentioned isotropic combustion reaction to predominate, resulting in a decrease in anisotropy.

Therefore, a dry etching method for a resist material layer is desired which can achieve both reduction of incident ion energy and achievement of high anisotropy.

As a technique for responding to such a demand, the applicant of the present application has not hitherto depended only on reduction of radicality and enhancement of ionicity for achievement of high anisotropy, but for side wall protection by a reaction product. We are proposing various technologies to be achieved in combination. In other words, if sidewall protection is also used, the ion incident energy can be reduced to the extent that the practical etching rate is not impaired, and even if low temperature etching is performed, it is equivalent in the temperature range much closer to room temperature than before. This is because the effect of is obtained.

For example, in JP-A-2-244625, a reaction product of a lower resist layer and a Cl-based gas is obtained by using an etching gas in which chlorine (Cl) -based gas is added to O _2. A technique for anisotropically etching the lower resist layer while depositing CCl _x as a sidewall protective film has been disclosed. Further, Japanese Patent Application No. 2-198044 proposes a technique of etching a resist material layer using an etching gas mainly composed of NH ₃ in a state where the wafer temperature is controlled at 50 ° C. or lower. .. Here, the etching reaction product containing at least N, C, and O as constituent elements plays a role of a sidewall protective film.

Further, Japanese Patent Application No. 2-298167 discloses that a reaction product of a lower resist layer and a Br-based gas is obtained by using an etching gas in which bromine (Br) -based gas is added to O ₂ . A technique of anisotropically etching the lower resist layer while depositing CBr _x as a side wall protective film was proposed.

[0014]

The respective dry etching methods previously proposed by the applicant of the present invention achieve anisotropic etching with low energy ions in a practical temperature range while ensuring a practical etching rate. In that respect, they were all extremely innovative technologies. However, in order to apply these techniques in the case where the underlying material layer contains copper (Cu), it has become clear that new problems must be overcome.

In recent years, Cu has been added at a rate of about 0.5 to 1% with respect to Al for the purpose of improving electromigration resistance and stress migration resistance of Al-based wiring. Also, Cu
Has a low electrical resistivity of about 1.4 μΩcm, which is about half that of Al, so that it is highly expected as a future wiring material in a semiconductor device if an effective dry etching technique is established.

However, the chloride or bromide of Cu has a low vapor pressure. Therefore, when the lower resist layer is etched using a Cl-based gas or a Br-based gas on the underlying material layer containing Cu, Cu supplied from the exposed surface of the underlying material layer is Cu.
It is expected that particles such as ₂ Cl ₂ and Cu ₂ Br ₂ will adhere to the side wall surface of the pattern and particle contamination will become more serious.

In order to address this problem, the present inventor has previously disclosed in Japanese Patent Application No. 3-4222 that the gas composition during overetching is a mixed composition of a nitrogen compound and an oxygen compound or nitric oxide. A method of preparing a composition containing a system compound is proposed. This is because even if the base material layer is Cu, Cu has a relatively low vapor pressure
It is an extremely excellent method that can volatilize and remove in the form of (NO ₃ ) ₂ . However, since this etching reaction system in which nitric acid is involved has a strong oxidizing property, depending on the conditions, oxidation gradually progresses from the exposed surface of Cu toward the inside, and the wiring resistance of the finally formed Cu wiring pattern increases. There is a concern that it will be done.

Therefore, the present invention improves the selectivity with respect to a silicon oxide type mask such as SOG, effectively prevents the redeposition of sputter products derived from the underlayer material layer, and increases the resistance of the underlayer material layer. It is an object to provide a dry etching method of a resist layer (organic material layer) which is not invited.

[0019]

The dry etching method of the present invention is proposed to achieve the above-mentioned object, and an organic material layer formed on a base material layer is replaced with an organic material layer of the organic material layer. When etching is performed using the silicon oxide pattern selectively formed on the mask as a mask, the etching is performed using an etching gas containing an iodine compound and an oxygen compound.

The present invention is also characterized in that the etching gas further contains a sulfur compound.

In the present invention, the etching is divided into two steps, and the organic material layer is substantially exposed just before the underlying material layer is exposed by using an etching gas containing an iodine compound and an oxygen compound. It is characterized by comprising a just etching step of etching and an overetching step of etching the remaining portion of the organic material layer while heating the substrate to be etched using an etching gas containing an iodine-based compound and NH _3. ..

Further, the present invention is characterized in that the base material layer contains Cu.

[0023]

The point of the present invention is to use iodine as an etching species when etching the organic material layer using the silicon oxide pattern as a mask. When the organic material layer is etched using an etching gas containing an iodine-based compound and an oxygen-based compound, an isotropic combustion reaction by O ^* is assisted by the incident energy of ions such as I ⁺ and O ^+. Anisotropic etching proceeds. However, since iodine has a poor chemical reactivity with silicon oxide-based materials, O ₂ / Cl, which has been conventionally proposed, is used.
It is possible to improve the selectivity with respect to the silicon oxide type mask as compared with the ₂ type and O ₂ / Br ₂ type. Therefore, even when an extremely thin silicon oxide-based pattern such as an SOG intermediate layer in a three-layer resist process is used as a mask, the receding of the mask during etching and the resulting dimensional conversion difference can be prevented. .. Moreover, when iodine is bound to the decomposition product of the organic material layer, CI
_{The x-} polymer is formed, which is deposited on the side wall of the pattern where vertical incidence of ions does not occur in principle, and exerts a side wall protection effect. Therefore, the ion incident energy required for anisotropic processing can be reduced as compared with the conventional process, and not only the mask selectivity but also the underlayer selectivity is improved.

If a sulfur compound is further added to the above gas system, the selectivity can be further improved. This is because, in addition to the above-mentioned CI _x polymer, S (sulfur) generated in the plasma from the above sulfur-based compound under discharge dissociation conditions can also be used for sidewall protection. S
Depends on the conditions, the wafer is deposited on the surface if the temperature is controlled to about room temperature or lower, and is easily sublimated if heated to about 90 ° C. or higher. Therefore, the use of S does not increase particle contamination.

Further, in the present invention, in order to effectively prevent the oxidation of the base material layer, oxygen is eliminated from the gas system in the vicinity of the interface between the organic material layer and the base material layer, and an iodine compound and NH ₃ are contained. We also propose a method of over-etching using an etching gas. Regarding the etching mechanism when NH ₃ is used, the above-mentioned Japanese Patent Application No. Hei 2-19804.
As disclosed in the specification No. 4, the sidewall protection effect of the CI _x polymer is added to this, and high selective highly anisotropic etching under low incident ion energy is realized. This method is effective in preventing the oxidation of the exposed surface, especially when the base material layer is a material layer such as Cu that is easily oxidized.

In the present invention, the selectivity for the silicon oxide-based etching mask and the underlying material layer is improved as described above, but using iodine as an etching species is another important factor. There are merits. That is, when the base material layer contains Cu, Cu released by sputtering of the base material layer can be quickly removed in the form of Cu ₂ I ₂ having a relatively high vapor pressure.

CRC Handbook of Che
mistry and physics, 71st E
position, 6-51 (CRC Press In
c. ), Or the same 53rd Edition, D-1
72, the vapor pressure data of the inorganic compound is 1 to 760 mmHg (= 1.33 × 10 ² to 1.
The temperature when showing a vapor pressure of 01 × 10 ⁵ Pa) is Cu ₂
It is clear that I ₂ is lower than both Cu ₂ Cl ₂ and Cu ₂ Br ₂ . In other words, the vapor pressure of Cu ₂ I _{2 at} the same temperature is equal to that of Cu ₂ Cl ₂ and C.
That is, it is higher than any vapor pressure of u ₂ Br ₂ . The gas pressure of the etching reaction system in which normal dry etching is performed belongs to a region much lower than the above pressure range, but the same tendency is maintained even under such a low pressure.

Therefore, if etching is performed using a gas system containing an iodine-based compound while appropriately heating the wafer, the O ₂ / Cl ₂ system and O ₂ / B system conventionally proposed have been proposed.
Particle contamination due to Cu can be significantly reduced as compared with the r ₂ system and the like.

[0029]

EXAMPLES Specific examples of the present invention will be described below.

Example 1 This example uses Al-1 in a three-layer resist process.
In this example, the lower resist layer formed on the% Si-0.5% Cu layer is etched using a HI / O ₂ mixed gas with the SOG pattern as a mask. This process
This will be described with reference to FIG.

First, as shown in FIG. 1A, an Al-1% Si-0.5% Cu layer 2 conforming to this step is formed on the SiO ₂ interlayer insulating film 1 having the step by about 0.7 μm. And a novolac-based positive photoresist (manufactured by Tokyo Ohka Kogyo Co., Ltd .; trade name OFPR).
-800) was applied to form a lower resist layer 3. Here, the thickness of the lower resist layer 3 in the region corresponding to the lower part of the step is about 1.0 μm. SOG (manufactured by Tokyo Ohka Kogyo Co., Ltd .; trade name OCD-T) is formed on the lower resist layer 3.
ype2) is spin-coated and the thickness of SO is about 0.2 μm.
The G intermediate layer 4 was formed. Further, an upper layer resist pattern 5 patterned into a predetermined shape was formed on the SOG intermediate layer 4. The upper resist pattern 5 is, for example, a negative type three-component chemically amplified resist material (made by Shipley Co .; trade name SAL-601) with a thickness of about 0.7 μm for a KrF excimer laser.
It was formed by performing lithography and development processing. The pattern width of the upper resist pattern 5 is about 0.35 μm.

Next, this wafer is subjected to hex type RIE.
It was set in a (reactive ion etching) apparatus, and the SOG intermediate layer 4 was etched using the upper layer resist pattern 5 as a mask. The conditions at this time are, for example, CHF ₃
Flow rate 75 SCCM, O ₂ flow rate 8 SCCM, gas pressure 6.5
Pa and RF power were 1350 W (13.56 MHz). As a result, as shown in FIG. 1B, the SOG pattern 4a was formed immediately below the upper layer resist pattern 5.

Then, the wafer was transferred to an RF bias application type magnetic field microwave plasma etching apparatus, and the lower resist layer 3 was etched under the following conditions as an example. HI flow rate 15 SCCM O ₂ flow rate 45 SCCM Gas pressure 1.5 Pa Microwave power 900 W RF bias power 300 W (2 MHz) In this etching process, isotropic combustion reaction by O ^* is assisted by ions such as I ⁺ and O ^+. On the other hand, the etching reaction product CI _x was deposited on the pattern side wall surface, and the side wall protective film 6 was formed. Due to the ion assist mechanism and the side wall protection effect, the lower resist pattern 3a having an anisotropic shape was formed as shown in FIG. 1 (c).

In this embodiment, I ^* and I ⁺ having low chemical reactivity with Si are used as the etching species, so that the selectivity for the SOG pattern 4a is improved, and the mask retreat and the dimensional conversion difference caused thereby. Never happened.

Example 2 This example uses Al-1 in a three layer resist process.
The lower resist layer formed on the% Si-0.5% Cu layer is used as an S ₂ Br ₂ / HI mask with the SOG pattern as a mask.
This is an example of etching using a / O ₂ mixed gas. First, the wafer shown in FIG. 1B was set in a magnetic field microwave plasma etching apparatus, and the lower resist layer 3 was etched under the following conditions as an example.

S ₂ Br ₂ flow rate 10 SCCM HI flow rate 15 SCCM O ₂ flow rate 50 SCCM Gas pressure 1.5 Pa Microwave power 900 W RF bias power 180 W (2 MHz) Wafer temperature 0 ° C. (Ethanol-based coolant used) Lower layer resist in this etching process In addition to the etching reaction product CI _x derived from layer 3, S produced in the gas phase by discharge dissociation of S ₂ Br ₂ contributed to sidewall protection on the cooled wafer. That is, as shown in FIG. 1C, the sidewall protective film 7 made of a mixture of CI _x and S was formed. Also, the isotropic radical reaction was suppressed to some extent by cooling the wafer. By enhancing the side wall protection effect and suppressing the radical reaction, excellent anisotropic processing can be performed even under the condition that the incident ion energy is significantly lower than that in Example 1, and the SOG pattern 4 is obtained.
It was possible to further improve the selectivity with respect to a and Al-1% Si-0.5Cu layer 2. Especially, the base Al-1%
Almost no redeposits derived from the Si-0.5Cu layer 2 were confirmed.

Example 3 In this example, the lower resist layer formed on the Cu layer was masked with the SOG pattern to form H ₂ S / HI / O ₂
HI / N after just etching using mixed gas
In this example, overetching is performed using a H ₃ mixed gas. This process will be described with reference to FIG.
Note that the reference numerals in FIG. 2 are partially common to those in FIG.

The wafer used as the etching sample in this example has a stepped C on the SiO ₂ interlayer insulating film 1 having a stepped portion, as shown in FIG.
The u layer 8 is formed, and the lower layer resist layer 3, the SOG pattern 4a, and the upper layer resist pattern 5 are sequentially formed on the u layer 8 by a three-layer resist process. Here, the SOG pattern 4a and the upper layer resist
The patterning method of the pattern 5 is as described above in the first embodiment.

Next, this wafer was set in a magnetic field microwave plasma etching apparatus, and as an example, the lower resist layer 3 was just etched under the following conditions. H ₂ S flow rate 10 SCCM HI flow rate 15 SCCM O ₂ flow rate 50 SCCM Gas pressure 1.5 Pa Microwave power 900 W RF bias power 180 W (2 MHz) Wafer temperature 0 ° C. (using ethanol-based coolant) In this just etching process, CI _x and S Etching progressed anisotropically while forming the side wall protective film 7 formed by mixing. As shown in FIG. 2B, this etching was stopped when the surface of the Cu layer 8 was exposed at the upper part of the step. At this time, the residual portion 3b of the lower resist layer 3 remained in the region corresponding to the lower portion of the step.

Therefore, in order to remove the residual portion 3b, overetching was performed by changing the etching conditions as follows as an example. HI flow rate 15 SCCM NH ₃ flow rate 45 SCCM Gas pressure 1.5 Pa Microwave power 900 W RF bias power 120 W (2 MHz) Wafer temperature 150 ° C. Here, the wafer is heated by operating the heater built in the wafer stage. It was

In this over-etching step, since the gas system contains iodine and the wafer is heated, the C sputtered from the underlying Cu layer 8 is released.
u was quickly volatilized and removed in the form of Cu ₂ I _{2, and} no redeposit layer was formed. The side wall protective film 6 formed at this stage is mainly composed of CI _x .
Further, since the RF bias power is reduced as compared with the just etching process, Cu sputter emission itself is also suppressed.

Another important advantage of this embodiment is that the wiring resistance of the Cu wiring pattern formed in the subsequent step does not increase. This is because the oxidation reaction on the exposed surface of the Cu layer 8 was prevented by eliminating oxygen from the etching reaction system in the above-described overetching step.

In the case where the etching processes having greatly different wafer temperatures are continuously performed as in this embodiment, the wafer stage is set in order to prevent the throughput from being lowered due to the time required for raising and lowering the temperature of the wafer. It is particularly preferable to use a multi-chamber type etching apparatus in which a plurality of etching chambers having different temperatures are connected under high vacuum. Alternatively, the present inventor first applied for Japanese Patent Application No. 3
As proposed in the specification of US Pat. No. 3,011,279,
It is also extremely effective to use an ECR plasma device equipped with a wafer stage in which a fixed electrode having a cooling means and a movable electrode having a heating means are combined.

The present invention has been described above based on the three embodiments, but the present invention is not limited to these embodiments. For example, as the oxygen-based compound, O ₃ can be used in addition to O ₂ described above. As the sulfur-based compound, in addition to S ₂ Br ₂ and H ₂ S described above, S ₂ Cl ₂ , S ₃ Cl
It is also possible to use sulfur chloride such as ₂ , SCl _{2 and} sulfur bromide such as S ₃ Br ₂ and SBr ₂ . Sulfur fluoride such as S ₂ F ₂ can release S under discharge dissociation conditions, but since F ^* lowers the selectivity for a silicon oxide-based mask, it is not suitable for use in the present invention. Is.

In addition, the wafer structure, etching conditions,
The etching apparatus to be used, the composition of etching gas, etc. can be appropriately changed.

[0046]

As is clear from the above description, according to the present invention, when an organic material layer is etched using a silicon oxide pattern as a mask, iodine having a low chemical reactivity with Si is used as an etching species. ,
Mask selectivity can be improved. At this time,
Since the CI _x polymer of the etching reaction product can be used for sidewall protection, incident ion energy required for anisotropic processing can be reduced, and the selectivity with respect to the underlying material layer is also improved. Moreover, this base material layer is C
In the case of containing u, even if Cu is sputtered and released, it can be removed in the form of Cu ₂ I ₂ by the iodine existing in the etching reaction system. It is possible to prevent accompanying particle contamination. Therefore, the utility of the multi-layer resist process can be truly enhanced.

The present invention is extremely effective in manufacturing a semiconductor device which is designed based on a fine design rule and which requires high integration, high performance and high reliability.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view illustrating a process example to which the present invention is applied in the order of steps, in which (a) is a lower resist layer, SOG on an Al-1% Si-0.5% Cu layer having a step. The intermediate layer and the upper layer resist pattern are sequentially formed, (b) is the state where the SOG pattern is formed, and (c) shows the lower layer resist pattern by etching the lower layer resist layer using at least the SOG pattern as a mask. Each of the formed states is shown.

FIG. 2 is a schematic cross-sectional view illustrating another example of the process to which the present invention is applied in the order of steps, in which (a) is a lower resist layer on a Cu layer having a step, an SOG pattern,
Upper resist pattern is sequentially formed, (b)
Is the state where the lower resist layer is just etched,
(C) represents a state in which the lower resist layer is over-etched.

FIG. 3 is a schematic cross-sectional view illustrating a problem in a conventional process, in which (a) is a state in which a lower resist layer, an SOG intermediate layer, and an upper resist pattern are sequentially formed on a base material layer having steps. (B) shows a state in which an SOG pattern is formed, (c) shows a state in which the lower resist layer is just etched, and (d) shows a redeposited layer formed of a sputtered product of the base material layer during overetching. It represents each state.

[Explanation of symbols]

1 ... SiO ₂ interlayer insulating film 2 ··· Al-1% Si- 0.5% Cu layer 3 ... lower resist layer 3a ... lower resist pattern 3b ... (the lower resist layer) Remaining portion 4 ... SOG intermediate layer 4a ... SOG pattern 5 ... Upper layer resist pattern 6 ... Side wall protective film (CI _x ) 7 ... Side wall protective film (CI _x + S) 8 ... Cu layer

Claims (4)

[Claims] 1. A dry etching method in which an organic material layer formed on a base material layer is etched using a silicon oxide pattern selectively formed on the organic material layer as a mask, wherein the etching is iodine-based. A dry etching method, which is performed using an etching gas containing a compound and an oxygen-based compound. 2. The dry etching method according to claim 1, wherein the etching gas contains a sulfur-based compound. 3. A dry etching method of etching an organic material layer formed on a base material layer with a silicon oxide pattern selectively formed on the organic material layer as a mask, wherein an iodine compound and oxygen are used. A just etching step of etching the organic material layer using an etching gas containing a compound based on the organic material layer until just before the underlying material layer is exposed, and an etching gas containing an iodine compound and NH ₃ . An over-etching step of etching the remaining portion of the organic material layer while heating the substrate to be etched, the dry etching method. 4. The dry etching method according to claim 1, wherein the base material layer contains copper.