JPH05274887A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain power down operation in the whole device or in each output system circuit. CONSTITUTION:In addition to a function capable of simultaneously executing the power down of an address circuit 1, a WE input circuit 3 and plural output system circuits 4 in a semiconductor memory, chip select signal input circuits 71 to 7m are allowed to execute power down in each output circuit system 4. Consequently power down operation can be executed in the whole device or in each output system circuit 4 and power consumption can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random access memory device (hereinafter referred to as RAM) or a semiconductor memory device having a built-in RAM, and more particularly to a power down operation control circuit.

[0002]

2. Description of the Related Art A RAM or built-in RAM includes an address circuit 1, a memory cell group 2, a write enable signal input circuit 3, a sense amplifier, a data input circuit, a level conversion circuit and an output circuit as shown in FIG. The output system circuit 4, the chip enable signal input circuit 5, the address input terminal ADD, the write enable terminal WE, the chip select terminal CS, the data input terminals D0 to Dm (m is a positive integer), and the output terminals O0 to O0. Om and.

Next, the operation will be described. In the read operation, m memory cells in the memory cell group 2 are selected for each output terminal O0 to Om through the address circuit 1 according to the logic applied to the address input terminal ADD, and m selected memory cells are selected. Information is output through output circuit 4 to output terminal O
It is read from 0 to Om.

In the write operation, m memory cells in the memory cell group 2 are selected through the address circuit 1 by the logic applied to the address input terminal ADD, and the write enable terminal WE is set to the write mode to input the data. The logic information applied to the terminals D0 to Dm is written in the m selected memory cells. A logic that activates the RAM is applied to the chip select terminal CS during the read operation and the write operation.

During the power-down operation, the chip select terminal CS is changed to a logic that puts the RAM in the inactive mode, and the output signal of the chip select input circuit 5 is the address circuit 1, the write enable signal input circuit 3, and the output system. Control the circuit 4. The logic of the output terminals D0 to Dm during the power-down operation of this RAM is high level or low level,
Alternatively, it becomes high impedance, and this logic can be selected by various configurations.

Recently, in RAM, 4 outputs, 8 outputs,
Products having multiple output terminals such as 16 outputs have been developed, and in addition, products having multiple output terminals having several hundred outputs in the built-in RAM have appeared.

[0007]

However, in the conventional RAM or the built-in RAM, the power-down operation performed by applying the logic for setting the RAM in the inactive mode brings the entire RAM into the power-down state at the same time. .
Therefore, in a RAM having multiple output terminals, power down can be performed only when not all outputs are used, and power down operation cannot be performed when outputs are selectively not used. Even in a built-in RAM having multiple output terminals, at least one output is not used at all, and even if it is desired to always perform a power-down operation for this output, the power-down operation cannot be performed. That is, in the RAM having multiple output terminals or the built-in RAM, there is a problem that the power down operation cannot be controlled for each output terminal and the power consumption cannot be sufficiently reduced.

[0008]

SUMMARY OF THE INVENTION The gist of the present invention is to read from a memory cell array, an input circuit of various control signals for controlling the operation of the memory cell, an inactivating circuit responding to a chip select signal, and a memory cell. In a semiconductor memory device including a plurality of output system circuits that respectively supply a plurality of output data bits to a plurality of output terminals, the deactivating circuit can selectively deactivate the plurality of output system circuits. is there.

[0009]

According to the above structure, the deactivating circuit can deactivate only the unused output system circuit based on the chip select signal.

[0010]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. This embodiment is different from the conventional example in that chip select signal input circuits 71 to 7m are provided for each output system circuit 4 and the output signal of the chip select signal input circuit 7 is output to each output terminal O0.
To the output system circuit 4 connected to each of the Om to Om, the address circuit 1 and the write enable signal input circuit 3
Address / write enable system control circuit 8 and a plurality of chip select signal input terminals CS0 to C
That is, Sm is provided.

Address / write enable system control circuit 8
2 shows a conventional example, assuming that the power-down operation is performed when the chip select signal input terminal CS is at a high level and the output of the chip select signal input circuit 5 is at a low level, in one embodiment of the present invention, the chip select signal is When all of the input terminals CS0 to CSm are high level and all outputs of the chip select signal input circuits 71 to 7m are low level, the output of the address / write enable system control circuit 8 becomes low level, and the address circuit 1 and the write enable signal input circuit. Inactivate 3. Therefore, it is configured by an m-input OR circuit. This m-input OR circuit can be formed by combining various logics, and detailed circuit configuration will be omitted.

In FIG. 1, since the chip select signal input terminals CS0 to CSm are provided for the respective output terminals O0 to Om, when at least one or more output terminals are not used, the corresponding output system circuit 4 is set. It can be inactivated, and the power down operation of the entire RAM can be performed in the same manner as in the conventional case. Therefore, it is possible to save power according to the situation and reduce power consumption.

In the first embodiment, the chip select signal input circuits 71 to 7m and the address / write enable system control circuit constitute an inactivating unit and an overall inactivating unit, respectively.

FIG. 3 is a block diagram of the second embodiment of the present invention. The present embodiment is different from FIG. 2 showing the conventional example in that a decoder circuit 9 is provided at the output of the chip select input circuit 5 and the decoder circuit 9 is connected to the input terminals CSD0 to CSD1 (l).
Is a positive integer), and the output signal of the decoder circuit 9 is distributed and connected to the address circuit 3, the write enable signal input circuit 3, and the output system circuit 4.

When the decoder circuit 9 has the same logic as the example shown in FIG. 1, when the chip select signal input terminal CS is at high level and the output of the chip select signal input circuit 5 is at low level, the output of the decoder circuit 9 is When the decoder circuits are all set to the low level and at least one or more output terminals O0 to Om are in the power down operation, the chip select signal input terminal CS is at the low level, the output of the chip select input circuit 5 is at the high level, The input terminals CSD0 to CSD1 of the decoder circuit 9 must be selectively controlled. The input terminals of the decoder circuit 9 for powering down at least one of the output terminals O0 to Om can be composed of three input terminals of the decoder circuit when the number of outputs is 5, for example.
The logic of D0 to CSD1 can be easily done.

In FIG. 2, since the decoder circuit 9 for controlling the output terminals O0 to Om and the input terminals CSD0 to CSD1 of the decoder circuit 9 are provided, when at least one output terminal is not used, the corresponding output is provided. The system circuit 4 can be powered down, the power down operation of the entire RAM can be performed in the same manner as in the conventional case, and the power consumption can be reduced.

[0017]

As described above, according to the present invention, the power down operation of each output system circuit can be selectively controlled, so that the power down operation can be executed even when some of the output terminals are not used, and the power consumption can be reduced. It has the effect of being able to.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

FIG. 3 is a block diagram of a second embodiment of the present invention.

[Explanation of symbols]

 1 address circuit 2 memory cell group 3 write enable signal input circuit 4 output system circuit 5 chip select signal input circuit 7 chip select signal input circuit 8 address write enable system control circuit 9 decoder circuit

Claims (3)

[Claims] 1. A memory cell array, an input circuit for inputting various control signals for controlling the operation of the memory cell, an inactivating circuit responsive to a chip select signal, and a plurality of data bits read from the memory cell. A semiconductor memory device comprising a plurality of output system circuits respectively supplied to output terminals, wherein the deactivating circuit can selectively deactivate a plurality of output system circuits. 2. The inactivating circuit is provided with a plurality of bits constituting a chip select signal, the plurality of inactivating units provided corresponding to the plurality of output circuits, and the plurality of inactivating units. 2. The semiconductor memory device according to claim 1, further comprising an overall deactivating unit that deactivates the input circuit in response to an output of a specific deactivating unit of the activating units. 3. The inactivation circuit comprises a decoder for decoding a chip select signal and selectively supplying the composite signal to the plurality of output circuits and the input circuit.
The semiconductor storage device described.