JPH05274861A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device capale of quickening the operation of a shared sense amplifier and promptly performing the reading of information. CONSTITUTION:The semiconductor storage device is provided with a bit line selection signal generation circuit 2A generating bit line selection signals S1L, S1R, a word line selection signal generation circuit 4 generating a word line selection signal SW and a memory cell array 7 including plural shared sense amplifier 10 and memory cells 15 to 18. The levels of the bit line selection signals S1L, S1R are made larger than 1/2Vcc reading potential difference and are set to a level Vs below a Vcc. After the shared sense amplifier 10 is operated, the levels of the bit line selection signals S1L, S1R corresponding to the selected bit line pairs is boosted to Vcc + alpha1 from a Vs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a shared sense type semiconductor memory device having a shared sense amplifier.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional shared sense type semiconductor memory device. In the figure, 1 is a buffer circuit to which a row address strobe signal RAS bar (hereinafter, an inverted version of the row address strobe signal RAS) is supplied from the outside, and 2 is a response to the output of the buffer circuit 1, Of course, the bit line selection signal generation circuit 3 for generating the bit line selection signals S1L and S1R based on the address signal from the outside, 3 is the buffer circuit 1
Is a delay circuit that delays the output of the output signal by a predetermined amount.

Reference numeral 4 is a word line selection signal generation circuit which responds to the output of the delay circuit 3 and which generates a word line selection signal SW based on an address signal from the outside (not shown). Reference numeral 5 is a word line selection signal generation circuit. A delay circuit for delaying the output of 4 by a predetermined amount, and 6 is a sense drive signal S based on the output of the delay circuit 5.
A sense drive circuit 7 for generating T is a memory cell array including a shared sense amplifier described later and for writing and reading information based on the signals S1L, S1R, SW and ST.

FIG. 4 representatively shows a part of an example of a concrete circuit configuration of the memory cell array 7 used in FIG. 3. In FIG. 4, 10 is information read from a memory cell described later. Shared sense amplifier for amplifying
Reference numeral 12 denotes a pair of bit lines BL (L) and BL bar (hereinafter, BL) arranged on the left side of the shared sense amplifier 10.
A pair of N-channel MOS transistors inserted in (L), 13, 1 respectively.
Reference numeral 4 is a pair of N-channel type MOS transistors respectively inserted in the pair of bit lines BL (R) and BL bar (R) arranged on the right side of the shared sense amplifier 10.

Reference numeral 15 has a gate electrode connected to a word line WLn (L) arranged on the left side of the shared sense amplifier 10, a first main electrode connected to a bit line BL (L), and a second main electrode. Is an N-channel MOS transistor connected to the power supply terminal via the capacitive element 16, and 17 has a gate electrode connected to the word line WLn (R) arranged on the right side of the shared sense amplifier 10 and has a first main electrode Is connected to the bit line BL (R) and the second main electrode is connected to the power supply terminal via the capacitive element 18
It is an S transistor.

The transistor 15 and the capacitor 16 and the transistor 17 and the capacitor 18 respectively form one memory cell, and this memory has a bit line BL bar (L), a word line WLn (L) and a bit line (not shown). The memory cell array is also connected between the BL bar (R) and the word line WLn (R), and in the same manner, this memory cell is provided in a matrix form between the word line and the bit line according to its storage capacity. (DRAM).

Next, the operation will be described with reference to FIG. FIG. 5 now being supplied to the buffer circuit 1.
When the row address strobe signal RAS from the outside as shown in (a) becomes low level, the bit line selection signals S1L and S1R as shown in FIG. 5 (b) are output to the output side of the bit line selection signal generation circuit 2. It is generated and supplied to each gate electrode of the transistors 11 to 14 in the memory cell array 7. At this time, which of the left and right bit line pairs is selected is determined by an address signal externally supplied to the bit line selection signal generation circuit 2.

Therefore, from the bit line selection signal generation circuit 2, as shown in FIG. 5B, the bit line selection signal S1L or S1R for the selected bit line pair is Vcc (power supply voltage) + α1 (of this α1). Values are transistors 11-1
The bit line selection signal S1L or S1R corresponding to the unselected bit line pair is set to 0V and output. Therefore, the pair of transistors 11 to which the line selection signal at the level of Vcc + α1 is supplied as the gate signal
And 12 or 13 and 14 are turned on, and the pair of transistors 11 and 12 or 13 and 14 to which a bit line selection signal of 0V level is supplied as a gate signal is turned off.

The output of the buffer circuit 1 is delayed by a predetermined amount in the delay circuit 3 and supplied to the word line selection signal generating circuit 4. At this time, which of the left and right word lines is selected is determined by an address signal externally supplied to the word line selection signal generation circuit 4. Therefore, from the word line selection signal generation circuit 4, Vcc + α2 (this α2 is shown on the selected word line WLn as shown in FIG. 5C).
Is set to a threshold level Vth of the transistor of the memory cell or higher), and a word line selection signal SW of 0V is generated on the word line WLn which is not selected (not shown). The signal SW is generated. Then, the transistor 15 or 17 connected to the word line WL in which the word line selection signal SW of the level of Vcc + α2 is generated is turned on, and the data of the corresponding memory cell is read onto the bit line BL.

On the other hand, the output of the word line generation circuit 4 is delayed by a predetermined amount in the delay circuit 5 and supplied to the sense drive circuit 6,
A sense drive signal ST as shown in FIG. 5D is supplied from the sense drive circuit 6 to the shared sense amplifier 10 in the memory cell array 7. As a result, the shared sense amplifier 10 is driven to amplify the level of the bit line pair having the minute potential difference to the levels of 0V and Vcc, as shown in FIG. 5 (e).

[0011]

The conventional semiconductor memory device is configured as described above, and the gate potential of the transistor pair on the selected side among the transistors 11 to 14, that is, the bit line before the shared sense amplifier operates. Since the selection signal is boosted to the power supply voltage Vcc or more, the transconductance g _m of these transistors increases, the on-resistance decreases, and the capacitance of the bit line appears to be substantially large, which results in the operation of the shared sense amplifier. However, there was a problem that the information could not be read quickly because of the delay.

The present invention has been made in order to solve such a problem, and an object thereof is to obtain a semiconductor memory device capable of speeding up the operation of the shared sense amplifier and rapidly reading information.

[0013]

SUMMARY OF THE INVENTION A semiconductor memory device according to the present invention is a memory including memory cells arranged in a matrix between bit lines and word lines, and an amplifier for amplifying information read from the memory cells. A cell array; a first selection signal generation means for generating a bit line selection signal for selecting the bit line; a second selection signal generation means for generating a word line selection signal for selecting the word line; Drive means for generating a drive signal for driving the amplifier on the basis of the output of the selection signal generating means, and the level of the bit line selection signal is higher than 1/2 power supply voltage + reading potential difference and lower than the power supply voltage. And the level of the bit line selection signal of the selected bit line after the operation of the amplifier is set to be equal to or higher than the power supply voltage.

[0014]

According to the present invention, the level of the bit line selection signal is set to a level higher than 1/2 power supply voltage + reading potential difference and lower than the power supply voltage, and before the operation of the amplifier for amplifying the information read from the memory cell. Sets the level of the bit line selection signal to 0 V only for the unselected bit lines.
The level of the bit line selection signal for the selected bit line is set to the power supply voltage or more after the operation of the amplifier. As a result, the transconductance g _{m of the} transistor to which the bit line selection signal is supplied is reduced, the on-resistance is increased, the capacitance of the bit line appears small, and the operation of the shared sense amplifier is accelerated.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. The parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. In FIG. 1, 2A is a buffer circuit 1.
Of the delay circuit 8 and the output of the delay circuit 8 which will be described later, the bit line selection signal generating circuit generating bit line selection signals S1L and S1R based on an address signal from the outside (not shown). Is a bit line selection signal generation circuit 2A after delaying the sense drive signal from the sense drive circuit 6 by a predetermined amount.
To the bit line selection signal generation circuit 2A.
Is the level of the bit line selection signals S1L and S1R after the operation of the shared sense amplifier 10 is Vcc + α1 (the value of α1 is the threshold level Vt of the transistors 11 to 14).
(It is set to h or higher).

Further, the bit line selection signal generation circuit 2A changes the level of the bit line selection signals S1L and S1R for a while after the external row address strobe signal RAS changes from the high level (standby state) to the low level. Vs is 1/2 Vcc + reading potential difference (word line WL
It is set to a level not higher than Vcc and higher than the potential difference of the bit line when the information of the memory cell is read by the upper word line selection signal SW and when the information is not read.

In the present embodiment as well, which is not shown, the memory cell array 7 is assumed to be composed of an array having a part of the structure shown in FIG. Also, the bit line selection signal generation circuit 2
A and the delay circuit 8 constitute a first selection signal generating means,
The word line selection signal generation circuit 4 and the delay circuit 3 form a second selection signal generation means, and the sense drive circuit 6 and the delay circuit 5 form a drive means.

Next, the operation will be described with reference to FIG. FIG. 2 now being supplied to the buffer circuit 1.
When the external row address strobe signal RAS bar shown in (a) goes low, the bit line selection signals S1L and S1R as shown in FIG. 2 (b) are output to the output side of the bit line selection signal generation circuit 2A. It is generated and supplied to each gate electrode of the transistors 11 to 14 in the memory cell array 7. At this time, which of the left and right bit line pairs is selected is determined by an address signal externally supplied to the bit line selection signal generation circuit 2A.

Therefore, from the bit line selection signal generation circuit 2A, as shown in FIG. 2B, the bit line selection signal S1L or S1R for the selected bit line pair is the above-mentioned V.
The bit line selection signal S1L or S1R corresponding to the unselected bit line pair is set to 0s and output at 0V. Therefore, in this state, a pair of transistors 11 and 12 or 13 and 14 to which a line selection signal of Vs level is supplied as a gate signal and a pair of transistors to which a bit line selection signal of 0V level is supplied as a gate signal. Both the transistors 11 and 12 or 13 and 14 maintain the off state.

The output of the buffer circuit 1 is delayed by a predetermined amount in the delay circuit 3 and supplied to the word line selection signal generating circuit 4. At this time, which of the left and right word lines is selected is determined by an address signal externally supplied to the word line selection signal generation circuit 4. Therefore, from the word line selection signal generation circuit 4, on the selected word line WLn, as shown in FIG. 2C, Vcc + α2 (this α2
Is set to a threshold level Vth of the transistor of the memory cell or higher), and a word line selection signal SW of 0V is generated on the word line WLn which is not selected (not shown). The signal SW is generated. Then, the transistor 15 or 17 connected to the word line WL in which the word line selection signal SW of the level of Vcc + α2 is generated is turned on, and the data of the corresponding memory cell is read onto the bit line BL.

On the other hand, the output of the word line generation circuit 4 is delayed by a predetermined amount in the delay circuit 5 and supplied to the sense drive circuit 6,
The sense drive circuit 6 supplies the sense drive signal ST as shown in FIG. 2D to the shared sense amplifier 10 in the memory cell array 7 and the delay circuit 8. As a result, the shared sense amplifier 10 is driven,
Further, as shown in FIG. 2B, the bit line selection signal generation circuit 2A, after a predetermined time has elapsed since the shared sense amplifier 10 is driven, causes the bit line selection signal S1L or the bit line selection signal S1L for the bit line pair selected as described above. Set the S1R level to V
The level of s is boosted to the level of Vcc + α1, which turns on the corresponding transistors 11 and 12 or 13 and 14. Then, the shared sense amplifier 10 amplifies the level of the bit line pair having the minute potential difference to the level of 0 V and Vcc, as shown in FIG.

[0022]

As described above, according to the present invention, memory cells arranged in a matrix between bit lines and word lines, a memory cell array including an amplifier for amplifying information read from the memory cells, First selection signal generating means for generating a bit line selection signal for selecting a bit line;
A second selection signal generating means for generating a word line selection signal for selecting a word line; and a driving means for generating a driving signal for driving an amplifier based on the output of the second selection signal generating means, Set the potential of the bit line selection signal to a level higher than 1/2 power supply voltage + reading potential difference and lower than the power supply voltage so that the potential of the bit line selection signal of the selected bit line becomes higher than the power supply voltage after the operation of the amplifier. Therefore, the transconductance g _{m of the} transistor to which the bit line selection signal is supplied becomes small, the on-resistance becomes large, and the capacitance of the bit line appears small. Therefore, the shared sense amplifier operates faster, This has the effect of enabling quick reading.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG.

FIG. 3 is a block diagram showing a conventional semiconductor memory device.

FIG. 4 is a circuit diagram representatively showing a part of an example of a specific circuit configuration of a memory cell array.

FIG. 5 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 2A Bit line selection signal generation circuit 3, 5, 8 Delay circuit 4 Word line selection signal generation circuit 6 Sense drive circuit 7 Memory cell array

Claims (1)

[Claims] 1. A memory cell arranged in a matrix between bit lines and word lines, a memory cell array including an amplifier for amplifying information read from the memory cell, and a bit line selection signal for selecting the bit line. A first selection signal generating means, a second selection signal generating means for generating a word line selection signal for selecting the word line, and an amplifier based on an output of the second selection signal generating means. And a drive means for generating a drive signal for driving the bit line selection signal, and the level of the bit line selection signal is set to a level higher than ½ power supply voltage + reading potential difference and lower than the power supply voltage and selected after the operation of the amplifier. A semiconductor memory device characterized in that the level of the bit line selection signal of the bit line is set to a power supply voltage or higher.