JPH05274388A - Input pattern generation method for logic circuit simulation - Google Patents

Abstract

PURPOSE:To generate an input pattern without erroneous input in a short time. CONSTITUTION:The input pattern generation method for logic circuit simulation generates or edits an input pattern to be inputted to the logic circuit simulator to be used for the inspection whether or not the designed logic circuit exhibits the required performance. A given input pattern is selected (S1 and S2) based on the stored input pattern, performing edition for the input pattern (S3 and S4). The edited input pattern is collated with the definition rule stored in advance, checking whether or not it is legal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit simulation input pattern generation method for generating or editing an input pattern to be input to a logic circuit simulation for verifying a logic circuit at a design stage.

[0002]

2. Description of the Related Art Conventional generation of this kind of input pattern is
There are a type of inputting an input waveform using an input device such as a stylus pen or a mouse while confirming an input waveform displayed on a display device such as a graphic display, and a type of generating an input waveform according to a definition rule using a text editor.

[0003]

However, in the method of using the input device and the display device, there are restrictions on the device. In addition, the method of creating with a text editor requires a great deal of labor and time to generate an input pattern with thousands of lines, so erroneous input is inevitable and the development period delay increases. ..

The present invention has been made in view of the above circumstances, and an object thereof is to provide an input pattern generation method for logic circuit simulation, which can generate an input pattern without erroneous input in a short time.

[0005]

An input pattern generation method for logic circuit simulation according to the present invention should be input to a logic circuit simulator used for verifying whether a designed logic circuit exhibits desired performance. An input pattern generation method for logic circuit simulation for generating or editing an input pattern, wherein an arbitrary input pattern is selected from pre-stored input patterns, editing work is performed on the input pattern, and the input after editing is performed. The pattern is checked against a pre-stored definition rule to check whether it is valid or not.

[0006]

1 is a flow chart showing the operation of an input pattern generation method for logic circuit simulation according to an embodiment of the present invention, and FIG. 2 is a schematic configuration of an apparatus to which this input pattern generation method for logic circuit simulation is applied. Figure,
FIG. 3 is an explanatory diagram showing an example of an input pattern, FIG. 4 is an explanatory diagram of a structure in the case of outputting an input pattern and the like, and FIG. 5 is an example of a display shown on a display means during editing work.

The input pattern generation method for logic circuit simulation according to the present embodiment generates an input pattern to be input to a logic circuit simulator used for verifying whether or not a designed logic circuit exhibits desired performance. A method for generating an input pattern for logic circuit simulation to be edited, in which an arbitrary input pattern is selected from pre-stored input patterns, an edit operation is performed on the input pattern, and the edited input pattern is stored in advance. It is checked whether it is legitimate according to the definition rules.

As shown in FIG. 3, the input pattern is such that the input signal for each pin of the logic circuit is "0" in the order of input time,
It is indicated by "1". Further, the absolute time in the input pattern means the accumulated time after the input of the input pattern is started, and is shown on the left side in FIG.
On the other hand, the relative time in the input pattern is the time between adjacent input signals, that is, the time until the next input signal is output, and it is shown in parentheses next to the absolute time. ing. Each input pattern is given a unique signal name.

The editing command is input by the keyboard 310, the stylus pen 320, the tablet board 330 or the mouse 34.
0 or the like is used. Which one to use is left to the operator's free choice. A graphic display or a character terminal is used as the display device 100 for displaying the editing work.

The storage means 200 stores various input patterns. The input patterns include those created in the past and those currently being created. In addition, a part of the storage unit 200 stores a definition rule regarding generation of an input pattern in advance. Further, a part of the storage means 200 is used as an instruction storage means,
Editing commands in editing work are stored in the order of input.

In this storage means 200, the input patterns are stored as input signals arranged in the order of absolute time. The stored content is a structure in which signal names are sorted in alphabetical order (see FIG. 4B), or a structure in which input signals of all or input patterns arbitrarily designated by the operator are sorted by time (FIG. 4A). reference)
Can be output with. Note that FIG. 4C is an input pattern shown in a table format.

The processing section 400 is connected to the keyboard 310, the storage means 200 and the display means 100. That is, the input pattern is transferred from the storage unit 200 to the processing unit 400 according to the designation of the operator, and the editing work is performed.

The operation of the logic circuit simulation input pattern generation method according to this embodiment will be described below. First, it is searched whether or not a desired input pattern is stored in the storage means 200 (see S _{1 in} FIG. 1). Here, when the desired input pattern is stored in the storage means 200, this input pattern is stored in the storage means 200 in a structure as shown in FIG. If the desired input pattern is not stored in the storage means 200, the process directly goes to the editing work (see S ₃ and S _{4 in} FIG. 1).

Next, when the input pattern is destroyed due to power failure or system down, it is judged whether or not the input pattern is restored (see S _{2 in} FIG. 1). When the input pattern is restored, the edit command stored in the storage means 200 is executed for the input pattern before the start of the editing work to restore the input pattern to the state before the destruction (see S _{6 in} FIG. 1). ). On the other hand, if there is no need to restore, that is, if the input pattern is not destroyed due to system down or the like, the editing operation is directly performed (see S ₃ and S _{4 in} FIG. 1). The editing commands are described in the input order in a text file created at the start of the editing work.

Next, the input pattern is edited using the keyboard 310 or the like. The functions and editing commands used for this input pattern editing work are as follows. When this editing work is performed, it is also checked whether the edited input pattern is valid according to the definition rule.

Input command: A new input pattern is generated, which is generated by arranging input signals in time order. At the same time, the signal name is also given.

The delete command has two functions. The first is to erase the specified absolute time and the input pattern pointed to by the absolute time.
The second is to erase all the designated signal name and the input pattern pointed to by the signal name. If the former is deleted, it is necessary to recalculate the absolute time and relative time after the deleted absolute time, but only the relative time is recalculated while retaining the absolute time and the absolute time. The operator can arbitrarily select whether to recalculate the relative time. In the case of this deletion, not only one absolute time but also a plurality of absolute times can be designated at the same time. If the specified absolute time does not exist, a warning message to that effect is output and the deletion command is canceled.

On the other hand, the latter deletion erases all the input patterns designated by the signal names. In case of this deletion, 1
Not only one signal name but also multiple signal names can be specified at the same time. Also in this case, if the designated signal name does not exist, a warning message to that effect is output and the deletion instruction is canceled.

The copy command has two functions. The first is to generate the input pattern pointed to by the specified absolute time at the newly specified absolute time, and the second is to specify the specified signal name. An input pattern that is the same as the pointing input pattern is newly generated. In the case of the former copying, it is necessary to recalculate the absolute time and the relative time after the generated absolute time. If there is no absolute time designated as something to be copied, or if a newly generated absolute time already exists, a warning message to that effect is output and the copy command is canceled. ..

On the other hand, in the latter case, the input pattern is designated by the signal name, and at the same time, the signal name of the newly generated input pattern is designated. Here, if there is no signal name designated as the one to be copied, or if there is already an input pattern with the same signal name as the signal name of the input pattern to be newly copied and generated, a message to that effect is given. A warning message is output and the copy command is canceled.

Change command has four functions. The first changes the designated absolute time or the relative time pointed to by the designated absolute time, and the second changes the designated signal name. The third is to specify an input signal of a specific input pattern by the signal name and absolute time, and change only the input signal. Further, the fourth is to change the designated absolute time or relative time to n times.

First, in the first case, it is necessary to recalculate the absolute time and relative time after the changed time (absolute time or relative time), but only the relative time is recalculated while holding the absolute time. Both the absolute time and the relative time can be recalculated. If there is a contradiction in absolute time during recalculation, a warning message to that effect is output and the change command is canceled.

In the second case, the signal name to be changed and the signal name after the change are input. In this case, if the signal name to be changed does not exist, or if the changed signal name already exists, a warning message to that effect is output and the change command is canceled.

In the third case, an input signal of a specific input pattern is designated by the signal name and time, and the input signal is changed to the newly input input signal. The validity is checked by matching the newly input signal with the definition rule. If not, a warning message to that effect is output, and the change command is canceled.

In the fourth case, when an absolute time to be multiplied by n is specified, the absolute time is multiplied by n. When specifying the relative time, the absolute time indicating the relative time is input. In the case of this change, not only one time but a plurality of times can be designated at the same time. In this case, in order to prevent the occurrence of inconsistency in time recalculation, the time shall be continuous. Then, the absolute time and the relative time after the changed time are recalculated. In this case,
In order to prevent the occurrence of inconsistencies, recalculation is performed over the entire time. If there is no designated absolute time, a warning message to that effect is output and the change command is canceled.

Replacement command Replaces the input pattern designated by the signal name or the input signal designated by the absolute time. Specifically, the designated input pattern is "101010", and "1"
When is replaced with “0”, the input pattern after the replacement becomes “000000”. The same applies when the absolute time is specified. The signal name and the absolute time may be designated as one or plural. If the designated signal name and absolute time do not exist, a warning message to that effect is output and the replacement instruction is canceled.

Inversion instruction The input pattern designated by the signal name or the input signal designated by the absolute time is reversed. Specifically, if the designated input pattern is "101010", the inverted input pattern will be "010101". The same applies when the absolute time is specified. The signal name and the absolute time may be designated as one or plural. If the designated signal name and absolute time do not exist, a warning message to that effect is output and the inversion instruction is canceled. The inversion instruction includes not only inverting “0” to “1” and inverting “1” to “0” but also changing the High level of the input pattern to be edited to Low level and vice versa. ..

Further, in order to facilitate the editing work, it is possible to display only the input pattern of the pin arbitrarily selected by the operator. Also, when the input signals are displayed in order of input time, any time sequence can be displayed in any combination.

When a desired input pattern is edited by repeating the above-described editing command, the input pattern is newly stored in the storage means 200 and used as an asset for the subsequent input pattern editing work. Then, the input pattern is output for the logic circuit simulation (see S _{7 in} FIG. 1).

[0030]

As described above, since the input pattern generating method for logic circuit simulation according to the present invention can edit the entire input pattern and the input signals forming each input pattern, the input pattern can be easily edited. A desired input pattern can be obtained. In particular, in the method using the conventional text editor, it is possible to add an input signal that requires a long time in a short time by making full use of an edit command such as a copy command. Further, since it is possible to easily correct the time by adding or deleting at the same time as the editing work, erroneous input is eliminated. Further, during the editing work, the definition rule is checked to check whether it is valid, so that an accurate input pattern can be generated.

[Brief description of drawings]

FIG. 1 is a flowchart showing an operation of an input pattern generation method for logic circuit simulation according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of an apparatus to which the logic circuit simulation input pattern generation method is applied.

FIG. 3 is an explanatory diagram showing an example of an input pattern.

FIG. 4 is an explanatory diagram of a structure for outputting an input pattern or the like.

FIG. 5 is an example of a display displayed on a display unit during editing work.

[Explanation of symbols]

 100 display device 200 storage means 400 processing unit

Claims (3)

[Claims] 1. A logic circuit simulation input pattern generation method for generating or editing an input pattern to be input to a logic circuit simulator used for verifying whether or not a designed logic circuit exhibits desired performance. Select an arbitrary input pattern from the stored input patterns, edit the input pattern, and check whether the edited input pattern is valid by comparing it with the pre-stored definition rules. An input pattern generation method for logic circuit simulation characterized by: 2. The input pattern generation method for logic circuit simulation according to claim 1, wherein the editing work is performed by applying various editing commands to the input pattern. 3. The method for generating an input pattern for logic circuit simulation according to claim 1, wherein the editing commands input during the editing work are described in the input order in a text file created at the start of the editing work.