JPH0527150B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to components of an information processing system,
More specifically, the present invention relates to a symbol string matching device and its matching method for extracting a specific symbol string from a long symbol string.

(Prior art and its problems) The above-mentioned symbol string matching device extracts feature sequences in a pattern recognition system, extracts keywords from the original text file of sentences created with a word processor, supports language translation, and extracts abbreviations from correspondence. deciphering, shapes, images,
It is used to construct unstructured databases based on text, etc., and is indispensable for the formation of intelligent information processing systems.

Conventional symbol string matching requires sequential processing using software on a general-purpose computer, which requires an enormous amount of processing time and is limited to small-scale applications. In addition, matching targets were limited to structured symbol strings separated by words. As an example, n
To find out where a pattern consisting of m symbol strings is located in a text consisting of m symbol strings,
This requires m(n-m+1) matching processes. m = 10 ⁹ stored on a magnetic disk, optical disk, etc.
Searching for sentences with n = 10 ³ character strings from text with 3 character strings requires 10 ¹² matching processes. Therefore, it is impractical to search using a large amount of source information such as text, images, graphics, audio, etc., so it is not practical to search by adding keywords to the source information in advance or search for data structured in tabular format. It was limited. Another disadvantage is that the processing time is too long for flexible symbol string matching that allows variations in the constituent elements of symbol strings.

More specifically, the problems of the conventional symbol string matching device and its matching method will be explained.

FIG. 1 shows text that is the subject of symbol string matching. This text shows the beginning of the report as an example. A large number of such texts are stored in the file memory of the word processor. When searching for what is needed from such texts, it is required to be able to search directly using words that indicate the desired content.

For example, if the text in Figure 1 is memory,
In order to know whether a paper contains symbol strings such as bubble, etc. in the text,
It is necessary to search to see if there is a matching part in symbol strings such as memories and bubbles. Comparing such symbol strings with text would take a very long time if conventional computers and software were used.

A typical _A4 size English sentence is about 3000 characters long, including the spaces between words. on the other hand,
The length of the symbol string to be compared and matched is 6 characters in both memory and bubble cases. 6 characters and 3000
Matching between strings of characters generally requires comparing the characters a number of times on the order of their product. Even if the character comparison time in the microprocessor is 1 μsec, it takes 18 msec to search each symbol string.

The actual number of characters in the text to be searched is
10 ⁹ characters, and the number of characters in the symbol string to be matched is 100.
It is possible to exceed. The number of symbol strings to be matched is not just one, but dozens. In that case, the verification time would be several hundred hours. Therefore, such matching is practically impossible, and in reality, keywords are extracted manually in advance and matching is limited to the extracted keywords.

[Purpose of the invention]

The purpose of the present invention is to easily solve the drawbacks of the conventional symbol string matching devices and methods mentioned above, and to quickly and flexibly convert arbitrary symbol strings from unstructured symbol strings such as text, images, figures, etc. An object of the present invention is to provide a symbol string matching device capable of extraction and a matching method thereof.

Another object of the present invention is to provide a low-cost symbol string matching device that can arbitrarily set the length of a matching symbol string.

Another object of the present invention is to reduce the number of output terminals.
The object of the present invention is to provide a symbol string matching device that can be easily integrated into LSI.

(Structure of the Invention) Therefore, according to the present invention, a symbol string storage means for storing a plurality of collation symbol strings with bit patterns associated with each symbol, a first transmission means connected to each of the outputs, and each adjacent A plurality of first register arrays in which registers are connected by a first transmission means, a second register array in which adjacent registers are connected in series, and registers in each stage of the second register array. output means for selectively outputting the output of each first register array depending on the content;
The output of each first register array and the output of a register in the second register array are selectively transferred to the next first register array.
A symbol string matching device including a second transmission means for transmitting data to a register array, and a symbol string matching device in which an encoder or a shift register is added to the output means of the device are obtained.

(Embodiment) FIG. 2 is an explanatory diagram of the first embodiment of the present invention. This symbol string matching device sequentially inputs text that is a long symbol string, checks whether it contains a registered verification symbol string, and transmits it to the outside. A symbol string storage means 210 for storing, an AND gate circuit serving as a first transmission means 230 connected to each output, and a plurality of first
register array 240, a second register array 250 in which adjacent second registers 255 are connected in series, and a first register array 240 selected according to the contents of each register 255 of the second register array 250. Output means 260 for selectively outputting an output, and each first register array 240
and a second transmission means 270 for selectively transmitting the output of the register 255 in the second register array 250 to the next first register array 240.

In the illustrated example, the first register array 240 located at the upper stage includes six first registers 245, and the first register array 240 at the lower stage includes five registers 245.
first registers 245 . Each first register array 240 is connected by an OR gate circuit 270 and an AND gate circuit 230. When using a collation symbol string with six or fewer symbols, "1" is stored in the first second register 255 of the second registers. In this case, the first second
Second communication means 270 leading to register 255
supplies the contents of the second register 255, that is, "1", to the AND gate circuit without passing the output of the first register array 240. Therefore, the input and output of each first register array 240 located in the upper and lower stages are separated. Further, the first register array 240 in the upper stage is outputted to the outside as a verification output via the output means 260.

On the other hand, for a collation symbol string having seven or more symbols, "0" and "1" are stored in the second registers 255 in the first and second stages of the second register array 250, respectively. . In this case, the second transmission means 270 passes the output of the first register array 240 in the upper stage and supplies it to the AND gate circuit 230. Therefore, the upper and lower first register arrays 240 are connected. Further, the output means 260 passes the output of the first register array 240 in the lower stage as a verification output. In this way, for a collation symbol string consisting of seven or more symbols, the first register arrays 240 are used in conjunction with each other. This concatenation can be controlled by the contents of second register array 250.

Each symbol of the verification symbol string is stored in each bit of the symbol storage means 210 in a bit pattern associated with the symbol. In this bit pattern, only the address selected by the symbol is set to "1". In the example shown in FIG. 2, the 11-bit symbol storage means 210 stores a collation symbol string consisting of five symbols "ABABB". In other words, the first and third addresses designated by the symbol “A”
"1" is stored only in the 2nd, 4th, and 5th bits of the address specified by the bit and the symbol "B", and "0" is stored in the other bits. However, the symbol string storage means 21
The 6th bit of 0 causes "1" to be stored in all addresses. Therefore, AND gate circuit 2 connected to it
30 is the content Q5 of the fifth first register 245
is supplied as is to the sixth first register 245.

Further, "1" is stored in the first second register of the second register array 250, and the output Q6 of the first register array 240 in the upper stage is outputted to the outside via the output means 270.

As explained above, the address of the symbol storage means 210 corresponds to the type of symbol, and the read output of the first and third bits becomes "1" only when the symbol "A" is input, and the read output of the second and fourth bits becomes "1" only when the symbol "A" is input. , the read output of 5 bits becomes "1" only when "B" is input. Further, the read output of the sixth bit always generates "1".

The symbols constituting the text to be compared are sequentially applied to the address input 211 of the symbol storage means 210, and the contents of the address corresponding to the symbol are read out. The read output of the first bit of the symbol storage means 210 is stored as an internal symbol in the first register array 2.
40 first-stage registers 245. The other read output is supplied to an internal signal transmission means 230 composed of an AND gate circuit, and determines whether or not to transmit the internal signal accumulated in the register 245 at each stage in the register array 240 to the register 245 at the next stage. control. The registers 245 at each stage in the register array 240 take in internal signals using the same clock signal 241 applied each time a symbol is input. The internal signal passes through the registers in each stage of the register array 240 only when the symbol string "ABABB" is input to the address input 211 of the symbol storage means 210, and the contents of a specific register are collated and output via the output means 270. It is output from terminal 280.

FIG. 3 is an explanatory diagram of the operation of the symbol string matching device shown in FIG. 2. As shown in FIG. 2, this is the first register array 240 when the collation symbol string "ABABB" is stored in the symbol storage means 210 and the symbol string "ABABAABBABABBAB" is input to the address input 211. The outputs Q1 to Q6 of each stage are shown. The output Q1 of the first stage of the first register array 240 becomes "1" only when the symbol "A" is input, and the output Q2 of the second stage becomes "1" only when Q1 is 1 and the symbol "B" is input. It becomes “1”. In this way, Q6 output to the verification output terminal 280 becomes "1" when a symbol string equal to the verification symbol string "ABABB" appears in the text. In this example, since Q6 becomes "1" at time T14, it can be seen that the underlined symbol string input one time before that is equal to the matching string.

In this example, only the collation symbol string "ABABB" stored in the symbol storage means 210 is detected, but even if part of the symbol string in the text is duplicated or missing, it may be detected if there is no confusion. It is possible.
For example, if the head of the verification symbol string can be the symbol "Z", by storing "1" also at the address specified by the symbol Z of the 0th bit of the symbol storage means 210, "ABABB ” and “ZBABB”
Both symbol strings can be extracted.

This symbol string matching device also makes it possible to match symbol strings that do not have delimiters such as spaces for each symbol string that has a meaning such as a word. It is also possible to match different symbol strings that have similar meanings. English words, especially nouns, often have different final letters in their singular and plural forms. For example, “memory” becomes “memories” in plural form. In this case, the collation symbol strings are “memory” and “memori”, that is,
By memorizing a symbol string with both “y” and “i” added to the end of “memor”, “memory”
and “memories” can be matched.

This symbol string matching device can be easily integrated into LSI, resulting in low cost. Also, since it is possible to match a single symbol in approximately the cycle time of a symbol string storage means, such as an IC memory, it is possible to create high-speed symbol strings. Enables matching. Furthermore, it is possible to handle collation symbol strings of various symbol string lengths. In addition, the number of output pins that generate verification output is reduced, making it easier to
Enables LSI conversion.

FIG. 4 is an explanatory diagram of another embodiment of the symbol string matching device according to the present invention. This symbol string matching device can match multiple matching symbol strings of arbitrary symbol string lengths in parallel. To make this possible, an OR gate circuit 470 and a first AND gate are provided, which correspond to the second transmission means 270, first transmission means 230, and output means 260 used in the symbol string storage device of FIG. Consisting of a circuit 430, a second AND gate circuit 460, a symbol string storage means 210, a first register array 440, a second register array 450, and an encoder 490 added to the AND gate circuit 460 as an output means. be done.

There are M first register arrays 440, each including N registers 445. Each register 445 in each first register array 440 is a first
are connected via an AND gate circuit 430, and each first register array 440 is connected to an OR gate circuit 4.
70 via a first AND gate circuit 430. Second register array 450 includes M registers corresponding to the number of first register array 440, which are connected in series.

The verification symbol string is stored in the symbol string storage means 210 in the form of a bit pattern associated with the symbol, as in FIG. That is, by writing "1" only to the address of the symbol string storage means 210 indicated by the symbol of the verification symbol string, that symbol is stored. The number of symbols in the collation symbol string is the register 4 of the first register array 440.
If the number N is less than 45, M verification symbol strings can be stored in the symbol string storage means 210 in correspondence with the first register array 440. At this time, "1" is stored in each register 455 of the second register array 450 as a marker that separates M collation symbol strings. The marker can be written in series by applying a marker write clock signal 452 to the second register array 450 along with a marker input signal 451. Also, the number of symbols in the matching symbol string and N
It is necessary to store "1" in all the bits of the symbol string storage means 210 corresponding to the difference between the two addresses. For example, when the number N of registers 445 in the first register array 440 is 8 and a 6-character collation symbol string "memory" is stored there,
"1" is stored in all addresses of the first and second bits of the symbol string storage means, and "m", "e", "m", and "o" are stored in the third to eighth bits, respectively. ”、
“1” is stored only in the addresses corresponding to the symbols “r” and “y”. When stored in this way, the first and second stage registers 445 in the first register array 440 have the symbol string input terminal 221
“1” is always held regardless of the symbol input from. As a result, only when a symbol string equal to the collation symbol string "memory" is input from the symbol string input terminal 221, an internal signal of "1" is transmitted to the final stage register 445 in the first register array 440, A verification output 480 is generated via the second AND gate circuit 460 . In other words, it is possible to match a verification symbol string having a symbol string length shorter than the number of stages N of the register 445.

On the other hand: for a collation symbol string whose symbol string length is greater than N, two or more first register arrays 440
Stores a collation symbol string across. For this purpose, the register 455 of the second register array 450 corresponding to the connection of the first register array 440 is made to store "0", which means that it is continuous. As a result, the OR gate circuit 470 connected to the register 455 of the second register array 450 that outputs "0" inputs the contents of the last stage register 445 of the first register array 440 to the next first register array 440. The signal is transmitted to an AND gate circuit 430 connected to . That is, 2
This means that the first register arrays 440 are connected in series. In this way, each first register array 440 can be connected in series or separated depending on the contents of the registers 455 in the second register array 450. That is, the first
The registers 445 in the register array 440 can be connected in units of N stages.

In this way, depending on the contents of the second register array 450, the internal signal in the final stage register 445 in any first register array 440 can be guided to the collation output 480, and the plurality of first register arrays 440 can be arbitrarily divided and connected. Therefore, a plurality of collation symbol strings having an arbitrary symbol string length can be stored in the symbol string storage means 210, and parallel verification of the collation symbol strings can be performed.

Further, the number of collation output terminals 480 is the number M of first register arrays 440, which is 1/N of the number of registers 445 in the plurality of first register arrays 440. Easy to integrate into LSI due to small number of output pins
This makes it possible to reduce the price.

Each matching output 480 is directed to an encoder 490, which generates a classification code 491 for the matched symbol string. If none of the matching outputs 480 has reached the encoder 490, the encoder 490 outputs an indiscernible signal 492. Such an encoder 490 is commercially available under the trade name Priority Encoder. Classification code 4
The number of bits of 91 becomes N bits when the number of collation outputs 480 is ^2N , and the number of output terminals of the symbol string collation device can be reduced and LSI implementation can be easily realized.

Also, instead of the encoder 490, the collation output 48
It is also possible to replace it with a shift register that inputs 0 signals in parallel and outputs them in series. In this case, the number of output terminals is one, which further facilitates LSI implementation.

Note that the first and second AND gate circuits 430,
460 and the OR gate circuit 470 have the functions of a first internal signal transmission means, an internal signal output means, and a second internal signal transmission means, respectively.
It is also possible to replace it with another gate circuit.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize a symbol string matching device that easily solves the problem of the conventional symbol string matching requiring too much matching time. It is also possible to perform verification that can flexibly deal with errors or changes in some symbols. Furthermore, multiple collation symbol strings with different symbol string lengths can be stored and collated in parallel. Therefore, by using hardware efficiently,
This results in lower prices and shorter matching times.

If the symbol string matching device of the present invention uses the current 256 kilobit RAM semiconductor technology and the symbol code length is 8 bits, it is possible to store 128 matching symbol strings with an average length of 8 symbols on one chip. , they can be matched in parallel.

The ability to classify symbol strings consisting of 256 types of signals into 128 classes with one chip means that up to 128 keywords (symbols This means that you can extract all columns in one go. In the past, it was difficult to search multiple keywords at the same time, so the above-mentioned chip has a great impact.

This symbol string identification device is also useful for classifying feature sequences in systems that perform pattern recognition, such as OCR devices and speech recognition devices. This one-chip LSI version of the symbol string identification device can also be used as a dictionary necessary for language translation. If a normal RAM is connected to this chip and translations of words are stored in correspondence with the classification code of each symbol string, translations of up to 128 words per chip can be obtained immediately upon completion of symbol string input. A typical RAM connected to a symbol string identification chip can store various types of information in accordance with the classification code of the symbol string, thereby achieving various symbol string information processing functions. . For example, if the part-of-speech code of a word, the number of occurrences of a symbol string, and processing instructions for a symbol string sentence are stored in correspondence with the classification code of the symbol string, it becomes easier to collect and organize knowledge information.

The processing speed of this symbol string extraction device is such that the cycle time Tc of the semiconductor RAM used as the symbol storage means approximately corresponds to the processing time of one symbol. Tc
If it is 100 ns, it will take 10 seconds to match the text of 10 ⁹ symbol strings with 10 ³ symbol strings.
Since matching using current software requires about 10 hours, the symbol string matching device of the present invention significantly shortens the matching time.

In summary, the drawbacks of long processing time and lack of flexibility caused by conventional symbol string classification using a combination of a microcomputer and software can be easily solved. Also, considering that the symbol string identification device of the present invention can be easily integrated into a single LSI chip, such an LSI can be used to extract keywords from original text files, electronic dictionaries for language translation, and feature series of pattern recognition systems. It becomes an indispensable functional element in classification.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a symbol string matching problem, FIG. 2 is an explanatory diagram of an embodiment of a symbol string matching device according to the present invention,
FIG. 3 is an explanatory diagram of the operation, and FIG. 4 is an explanatory diagram of another embodiment according to the present invention. 210... Symbol string storage means, 230... First transmission means, 240, 440... First register array, 245... Register, 250, 450...
Second register array, 255...Register, 2
60... Output means, 270... Second transmission means,
430...first AND gate circuit, 460...
Second AND gate circuit, 470...OR gate circuit, 490...Encoder.

Claims (1)

[Claims] 1. Symbol string storage means for storing a plurality of collation symbol strings with bit patterns associated with each symbol, a first transmission means connected to each of the outputs, and a first communication means between adjacent registers. A plurality of first register arrays connected by a transmission means, a second register array in which adjacent registers are connected in series, and a plurality of first register arrays connected by a transmission means; output means for selectively outputting the output of the register array; and a second output means for selectively transmitting the output of each first register array and the output of the register in the second register array to the next first register array. A symbol string matching device comprising: a transmission means. 2. The symbol string matching device according to claim 1, wherein the first transmission means and the output means are AND gate circuits, and the second transmission means is an OR gate circuit. 3 Symbol string storage means for storing a plurality of collation symbol strings with bit patterns associated with each symbol, a first transmission means connected to each of the outputs, and mutually adjacent registers connected by the first transmission means. A plurality of first register arrays, a second register array in which adjacent registers are connected in series, and an output of each first register array is selected based on the contents of the registers in each stage of the second register array. output means for selectively transmitting the output of each first register array and the output of the register in the second register array to the next first register array; A symbol string matching device characterized by comprising an encoder or a shift register added to the means. 4. The symbol string matching device according to claim 3, wherein the first transmission means and the output means are AND gate circuits, and the second transmission means is an OR gate circuit.