JPH05268272A - Signal identification system - Google Patents

Signal identification system

Info

Publication number
JPH05268272A
JPH05268272A JP4064049A JP6404992A JPH05268272A JP H05268272 A JPH05268272 A JP H05268272A JP 4064049 A JP4064049 A JP 4064049A JP 6404992 A JP6404992 A JP 6404992A JP H05268272 A JPH05268272 A JP H05268272A
Authority
JP
Japan
Prior art keywords
level
circuit
levels
identification
peak
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4064049A
Other languages
Japanese (ja)
Inventor
Yoshinori Okuma
義則 大隈
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4064049A priority Critical patent/JPH05268272A/en
Publication of JPH05268272A publication Critical patent/JPH05268272A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Optical Communication System (AREA)

Abstract

PURPOSE:To suppress the error of identification and to improve reliability by detecting the peaks of the levels '1' and '0' of an equalization wave-form inputted to an identification circuit and superimposing their average value to a constant identification level. CONSTITUTION:Peak detection circuits 12 and 13 respectively detect the peak levels in the signal levels '0b and '1', a first adding circuit 14 adds the peak levels in the signal levels '1' and '0', and a dividing circuit 15 divides the output value of the circuit 14 into two. Both of the circuits 14 and 15 obtains the average level of the peak level in the signal levels '0' and '1'. A second adding circuit 16 adds the constant identification level and the average value of the peak levels to control the identification level of the identification circuit 9. As the output of the circuit 15 is the instant value of the average value of the levels '1' and '0', the identification level is always the intermediate value between '0' and '1' even in the case of the code of which mark rate in not 1/2. Thus, data output generating few errors even to the signal with an optional mark rate is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、識別レベル制御方法に
関する。近年通信システムで取り扱われる情報は社会の
多方面に関連し、伝送断は言うに及ばず、信号伝送にお
ける僅かな誤りによって重大な社会的影響をもたらす場
合も少なくない。この為、通信システムの運用中発生す
ると想起される原因を事前に防止したシステム構成を導
入する要望がある。通信システムを運用中に予備パネル
の保守等の作業を実施する場合、現用回線の光ファイバ
に機械的衝撃を与えた場合に、瞬間的に等化波形に劣化
が発生し信号誤り率が急激に悪化するために、かかる等
化波形の劣化を惹起しない方策が要求されている。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discrimination level control method. Information handled by communication systems in recent years is related to many aspects of society, and it is often the case that a slight error in signal transmission causes a serious social impact, not to mention transmission interruption. For this reason, there is a demand to introduce a system configuration that prevents in advance the cause that may occur during operation of the communication system. When performing work such as maintenance of the spare panel during operation of the communication system, when the optical fiber of the working line is mechanically impacted, the equalized waveform is momentarily deteriorated and the signal error rate becomes sharp. Therefore, there is a demand for a measure that does not cause the deterioration of the equalized waveform.

【0002】[0002]

【従来の技術】図5に従来の光受信回路の構成例を示
す。図中、1は受光素子で、光信号を電気信号に変換す
るもの、2及び3は増幅器で、電気信号を所定のレベル
まで増幅するもの、4は分岐部で、一定レベルになった
電気信号を次の処理をするために各部に配分するもの、
5及び6はピーク検出回路で、それぞれ「0」及び
「1」の信号レベル中のピークレベルを検出するもの、
7は直流変換器で、受光素子1のバイアスを調整するも
の、8はタイミング抽出部で、電気信号からタイミング
信号を抽出するもの、9は識別回路で電気信号の「1」
のレベルと「0」のレベルとを判定するものであり、イ
は識別レベル設定のための端子、ロはデータ出力の端
子、ハはクロック出力の端子である。
2. Description of the Related Art FIG. 5 shows a configuration example of a conventional optical receiving circuit. In the figure, 1 is a light receiving element, which converts an optical signal into an electric signal, 2 and 3 are amplifiers, which amplify the electric signal to a predetermined level, 4 is a branching part, which is an electric signal having a constant level That is distributed to each part for the following processing,
Reference numerals 5 and 6 are peak detection circuits for detecting peak levels in the signal levels of "0" and "1", respectively.
Reference numeral 7 is a DC converter, which adjusts the bias of the light receiving element 1, 8 is a timing extraction unit, which extracts a timing signal from an electric signal, and 9 is an identification circuit, which is "1" of the electric signal.
Is a terminal for setting an identification level, b is a data output terminal, and c is a clock output terminal.

【0003】この構成では、「1」側のレベルを一定に
するため受光素子1(APD)のMを変化させるFullA
GC、同じく「1」側のレベルを一定にするため電気段
(即ち、増幅器)のゲインを変化させるEAGC及び
「0」側のレベルを一定にするDCFBの3つのループ
によって出力振幅を一定にしている。一方、各ループは
時定数は互いに干渉しあってループ動作が不安定となら
ないように少しずつループ時定数を変えてある。例え
ば、EAGC、DCFB、FullAGCの順に次第に時定
数を大きくする。
In this configuration, FullA for changing M of the light receiving element 1 (APD) in order to keep the level on the "1" side constant.
Similarly, the output amplitude is made constant by three loops of GC, EAGC that changes the gain of the electric stage (that is, amplifier) to make the level of "1" side constant, and DCFB that makes the level of "0" side constant. There is. On the other hand, the loop time constants of the loops are gradually changed so that the loop constants do not interfere with each other and the loop operation becomes unstable. For example, the time constant is gradually increased in the order of EAGC, DCFB, and FullAGC.

【0004】この場合、図6に示すような光入力レベル
の変動があると、変動時間とループ時定数との関係より
以下の3つの場合がある。第1の場合は変動時間が各ル
ープ時定数より十分長い場合で、各ループが十分応答す
るため、等化波形Aに示すように等化波形劣化は生じな
い。第2の場合は変動時間が各ループ時定数より十分短
い場合で、各ループは応答しないため、等化波形Bに示
すように「1」側及び「0」側からの対称な劣化を生じ
て、Aの場合に比較してエラーが発生し易くなる。第3
の場合は変動時間がフルAGCが応答せずDCFBが応
答する場合で、DCFBのみ動作して、「0」側のアイ
劣化は減少するが、「1」側からのアイ劣化が大きくな
り、エラー発生がBのときに比べて大きくなる。
In this case, when the optical input level fluctuates as shown in FIG. 6, there are the following three cases from the relationship between the fluctuation time and the loop time constant. In the first case, the fluctuation time is sufficiently longer than the time constant of each loop, and each loop responds sufficiently, so that the equalized waveform deterioration does not occur as shown in the equalized waveform A. In the second case, the variation time is sufficiently shorter than each loop time constant, and each loop does not respond, so that symmetrical degradation from the "1" side and the "0" side occurs as shown in the equalized waveform B. , A, an error is more likely to occur. Third
In the case of, when the fluctuation time is full AGC does not respond and DCFB responds, only DCFB operates and the eye deterioration on the "0" side decreases, but the eye deterioration from the "1" side increases and an error occurs. It is larger than when the occurrence is B.

【0005】[0005]

【発明が解決しようとする課題】従って、変動時間によ
ってはAGCの追従が適切でなく、エラー発生が大きく
なるといった問題があった。本発明は、このようなエラ
ー発生の頻度を抑えることを目的とする。
Therefore, there is a problem that the tracking of the AGC is not appropriate depending on the variation time and the error occurrence becomes large. An object of the present invention is to reduce the frequency of such error occurrence.

【0006】[0006]

【課題を解決するための手段】図1は、本発明の原理説
明図である。図中、1は受光素子で、光信号を電気信号
に変換するもの、20は増幅部で、電気信号を所定のレ
ベルまで増幅するもの、8はタイミング抽出部で、電気
信号からタイミング信号を抽出するもの、9は識別回路
で電気信号の「1」のレベルと「0」のレベルとを判定
するもの、20は増幅部で、図5の2、3、4、5、
6、7の機能を含むもの、30は識別レベル制御部で、
識別回路9の識別レベルを制御するもの、イは識別レベ
ル設定のための端子、ロはデータ出力の端子、ハはクロ
ック出力の端子である。識別レベル制御部30の出力は
「1」のレベルの瞬時値と「0」のレベルの瞬時値の平
均値を一定識別レベルに重畳した値であるため、識別レ
ベルが常に「1」と「0」の中間の値をとり、よりエラ
ー発生の少ないデータ出力が得られる。
FIG. 1 illustrates the principle of the present invention. In the figure, 1 is a light receiving element for converting an optical signal into an electric signal, 20 is an amplifying section for amplifying the electric signal to a predetermined level, 8 is a timing extracting section for extracting a timing signal from the electric signal 5 is a discrimination circuit for discriminating between "1" level and "0" level of an electric signal, and 20 is an amplifying section, which is 2, 3, 4, 5, in FIG.
Including the functions of 6 and 7, 30 is a discrimination level control unit,
A circuit for controlling the discrimination level of the discrimination circuit 9, a is a terminal for setting the discrimination level, b is a data output terminal, and c is a clock output terminal. Since the output of the discrimination level control unit 30 is a value obtained by superimposing the average value of the instantaneous value of the level "1" and the instantaneous value of the level "0" on the constant discrimination level, the discrimination levels are always "1" and "0". The intermediate value of “” can be taken, and the data output with less error can be obtained.

【0007】[0007]

【作用】本発明では、図1の如く増幅部20の出力の平
均値を検出して、一定の識別レベルを中心に、識別レベ
ルを増減する。例えば、図4に示すように、「1」のレ
ベルがXの如く、「0」のレベルがYの如く変動した場
合、識別レベルはZのようにXとYの中間に変わるの
で、「1」レベルと「0」レベルの区別が明確になり、
信号のエラー発生を抑制することが出来る。
In the present invention, as shown in FIG. 1, the average value of the output of the amplifying section 20 is detected, and the discrimination level is increased or decreased centering on a constant discrimination level. For example, as shown in FIG. 4, when the level of "1" changes as X and the level of "0" changes as Y, the identification level changes between X and Y like Z, so "1" The distinction between "level" and "0" level became clear,
It is possible to suppress the occurrence of signal errors.

【0008】[0008]

【実施例】図2は本発明の第1の実施例である。図中、
1は受光素子、2及び3は増幅器、4は分岐部、5及び
6はピーク検出回路、7は直流変換器、8はタイミング
抽出部、9は識別回路、10は平均値検出回路で、識別
回路に入力される等化波形の平均値を検出するもの、1
1は加算回路で、固定した識別レベルに平均値検出回路
出力を加えるものでり、図1の識別レベル制御部の1構
成例である。イは識別レベル設定のための端子、ロはデ
ータ出力の端子、ハはクロック出力の端子である。
FIG. 2 shows a first embodiment of the present invention. In the figure,
1 is a light receiving element, 2 and 3 is an amplifier, 4 is a branching section, 5 and 6 are peak detecting circuits, 7 is a DC converter, 8 is a timing extracting section, 9 is an identification circuit, 10 is an average value detection circuit, and identification is performed. Detecting the average value of the equalized waveform input to the circuit, 1
Reference numeral 1 denotes an adder circuit, which adds the average value detection circuit output to a fixed discrimination level, and is one example of the constitution of the discrimination level control unit in FIG. B is a terminal for setting a discrimination level, B is a data output terminal, and C is a clock output terminal.

【0009】本実施例の場合には、平均値検出回路10
の出力は、識別回路(9)に入力される等化波形の平均
値である為、図4に示す如く識別レベルが常に「1」
(X)と「0」(Y)の中間の値(Z)をとり、よりエ
ラー発生の少ないデータ出力が得られる。図3に本発明
の第2の実施例を示す。図中、12および13は共にピ
ーク検出回路で、それぞれ「0」及び「1」の信号レベ
ル中のピークレベルを検出するもの、14は第1の加算
回路で、「0」及び「1」の信号レベル中のピークレベ
ルを加算するもの、15は割り算回路で、第1の加算回
路の出力値を2分の1にするもの、14と15の両者に
より「0」及び「1」の信号レベル中のピークレベルの
平均値が得られる、16は第2の加算回路で、一定の識
別レベルと、「0」及び「1」の信号レベル中のピーク
レベルの平均値との加算を行い、識別回路9の識別レベ
ルを制御するものである。その他の記号に付いては、こ
れまでに説明したものと同じである。
In the case of the present embodiment, the average value detection circuit 10
Since the output of is the average value of the equalized waveform input to the discrimination circuit (9), the discrimination level is always "1" as shown in FIG.
By taking an intermediate value (Z) between (X) and "0" (Y), data output with less error occurrence can be obtained. FIG. 3 shows a second embodiment of the present invention. In the figure, 12 and 13 are both peak detection circuits for detecting the peak levels in the signal levels of "0" and "1", respectively, and 14 is a first addition circuit for the "0" and "1". Addition of peak levels in the signal level, 15 is a division circuit that reduces the output value of the first addition circuit to 1/2, and signal levels of "0" and "1" by both 14 and 15. The second addition circuit 16 obtains the average value of the peak level of the inside, and adds a constant identification level and the average value of the peak levels among the signal levels of "0" and "1" to identify It controls the discrimination level of the circuit 9. Other symbols are the same as those described above.

【0010】本実施例の場合には、「1」ピーク検出回
路(13)の出力は「1」のレベルの瞬時値であり、
「0」ピーク検出回路(12)の出力は「0」のレベル
の瞬時値であり、割り算回路(15)の出力は、「1」
及び「0」のレベルの平均値の瞬時値であるため、マー
ク率が1/2でない符号のばあいにおいても、識別レベ
ルが常に「1」と「0」の中間の値をとる。このため、
マーク率の任意の信号に対しても、エラー発生の少ない
データ出力が得られる。
In the case of this embodiment, the output of the "1" peak detection circuit (13) is an instantaneous value of the level "1",
The output of the "0" peak detection circuit (12) is an instantaneous value of the level of "0", and the output of the division circuit (15) is "1".
And the average value of the levels of "0", the discrimination level always takes an intermediate value between "1" and "0" even in the case of a code whose mark ratio is not 1/2. For this reason,
Data output with few errors can be obtained even for an arbitrary signal of the mark ratio.

【0011】[0011]

【発明の効果】以上説明した様に、本発明によれば、通
信システムを運用中の作業等によって与えられる予期せ
ぬ機械的衝撃等に起因して信号レベルが急変しても、識
別回路の識別レベルが瞬時的に最適値に調整され、識別
の誤りを抑制する効果を奏し、光通信回線の信頼性の向
上に寄与するところが大きい。
As described above, according to the present invention, even if the signal level suddenly changes due to an unexpected mechanical shock or the like given by work while operating the communication system, the discrimination circuit The identification level is instantaneously adjusted to the optimum value, which has the effect of suppressing identification errors and contributes greatly to the improvement of the reliability of the optical communication line.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の原理説明図である。FIG. 1 is a diagram illustrating the principle of the present invention.

【図2】本発明の第1の実施例構成図である。FIG. 2 is a configuration diagram of a first embodiment of the present invention.

【図3】本発明の第2の実施例構成図である。FIG. 3 is a configuration diagram of a second embodiment of the present invention.

【図4】識別回路の動作説明図である。FIG. 4 is a diagram illustrating the operation of the identification circuit.

【図5】従来の構成例である。FIG. 5 is a conventional configuration example.

【図6】等化波形の応答例である。FIG. 6 is a response example of an equalized waveform.

【符号の説明】[Explanation of symbols]

1 ホトダイオード 2、3 増幅器 4 分岐部 5、13 「1」のピーク検出回路 6、12 「0」のピーク検出回路 7 直流変換器 8 タイミング抽出部 9 識別回路 10 平均値検出回路 11、14、16 加算回路 15 割り算回路 20 増幅部 30 識別レベル制御部 イ 識別レベル設定のための端子 ロ データ出力の端子 ハ クロック出力の端子 1 Photodiode 2, 3 Amplifier 4 Branching section 5, 13 “1” peak detection circuit 6, 12 “0” peak detection circuit 7 DC converter 8 Timing extraction section 9 Discrimination circuit 10 Average value detection circuit 11, 14, 16 Adder circuit 15 Divider circuit 20 Amplification unit 30 Discrimination level control unit a Terminal for setting the discrimination level b Data output terminal Ha clock output terminal

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】光受信機の増幅部の等化波形出力とタイミ
ング抽出部出力とを識別回路に入力し、与えられた一定
の識別レベルを基準に、等化波形が1レベルか0レベル
かを判定して、データを出力する信号識別方法に於い
て、 該一定の識別レベルに、等化波形の平均値を重畳するこ
とを特徴とする信号識別方法
1. An equalization waveform output of an amplification section of an optical receiver and a timing extraction section output are inputted to a discrimination circuit, and whether the equalization waveform is 1 level or 0 level based on a given constant discrimination level. In the signal identification method for determining the above and outputting data, the average value of the equalized waveform is superimposed on the constant identification level.
【請求項2】請求項1に於いて、識別回路に入力される
等化波形の1レベルのピークと0レベルのピークとを検
出し、該1レベルのピークと0レベルのピークとの平均
値を一定の識別レベルに重畳することを特徴とする信号
識別方法
2. The average value of the 1-level peak and the 0-level peak is detected by detecting the 1-level peak and the 0-level peak of the equalized waveform input to the discrimination circuit. Discrimination method characterized by superimposing a signal on a certain discrimination level
JP4064049A 1992-03-19 1992-03-19 Signal identification system Withdrawn JPH05268272A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4064049A JPH05268272A (en) 1992-03-19 1992-03-19 Signal identification system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4064049A JPH05268272A (en) 1992-03-19 1992-03-19 Signal identification system

Publications (1)

Publication Number Publication Date
JPH05268272A true JPH05268272A (en) 1993-10-15

Family

ID=13246854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4064049A Withdrawn JPH05268272A (en) 1992-03-19 1992-03-19 Signal identification system

Country Status (1)

Country Link
JP (1) JPH05268272A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010118433A (en) * 2008-11-12 2010-05-27 Furukawa Electric Co Ltd:The Optical module and method for controlling the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010118433A (en) * 2008-11-12 2010-05-27 Furukawa Electric Co Ltd:The Optical module and method for controlling the same

Similar Documents

Publication Publication Date Title
JP4532563B2 (en) Optical receiver and identification threshold value generation method thereof
US5822104A (en) Digital optical receiving apparatus
JPH10163828A (en) Level identification circuit
US7382987B2 (en) Identification level control method and optical receiver
EP1815617A1 (en) Optical receiver having transient compensation
KR100445910B1 (en) Optical signal receiving apparatus and method having suitable receiving performance in spite of change of intensity of the optical signal
JPH05268272A (en) Signal identification system
JPH11346194A (en) Optical receiver
JP4137120B2 (en) Preamplifier circuit, clock switching circuit, and optical receiver using the same
JPH10107555A (en) Optical reception circuit and its control method
JPH0736500B2 (en) AGC control method
JP3232622B2 (en) Optical signal input disconnection detection circuit
US5633690A (en) Automatic gain control circuit of a video processing system and method therefor
JP2600462B2 (en) Optical receiving circuit
JPH05122153A (en) Photodetecting circuit
JP2837209B2 (en) Optical receiver and optical communication system including the optical receiver
JPH0340539A (en) Device for detecting disconnection of optical signal input
US20220216841A1 (en) Transimpedance Amplifier
JPH0379141A (en) Optical signal input break detecting circuit
JPH0340538A (en) Device for detecting disconnection of optical signal input
JPH1155194A (en) Bias control system for optical receiver
JPH02288640A (en) Optical reception circuit
JP2616680B2 (en) Optical receiving circuit
JPH11127122A (en) Optical receiver
JP2838935B2 (en) Optical receiver

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990608