JPH05268085A - A/d converter - Google Patents

Abstract

PURPOSE:To provide a selecting device transmitting either of high order or low order bit of code of the calculation result of an accumulation adder and sending it to an information transmission line while selecting the high order bit when the absolute value at the RF level is required when transmission bit capacity (n) on the information transmission line is smaller than bit capacity (m) of the accumulation adder and selecting the low order bit when the fluctuation information on noise level is required. CONSTITUTION:When a code 13 after accumulation addition added by the prescribed number by an accumulation adder 3 is taken as high-order bit (for example 8 bits) representing the average RF level and the low order bit (for example 5 bits) representing the noise fluctuation level, (m) is equal to 13. When transmission capacity of the code 14 on the information transmission line is (n)=8 bits, the transmission can be performed by only selecting either high-order or low order bit. A selecting device 4 selects the high-order or low order bit of the (m) bit at its transmission to the information transmission line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and particularly when the RF level of an input microwave or the like is A / D converted, the RF level is extremely low and noise level fluctuations are considerably mixed. The present invention relates to an A / D converter that can output information such as the average value level of microwaves or noise level fluctuations.

[0002]

2. Description of the Related Art Conventionally, an A / D converter of this type is shown in FIG. An A / D converter 2 for converting and transmitting an L-bit (for example, parallel code having an 8-bit configuration) conversion code 12, and this conversion code 1
2 is input a predetermined number of times and added, and the result of the addition is divided into an average level of the RF signal and a noise fluctuation level. And a cumulative adder 3 for outputting two pieces of code information of an average level and a noise fluctuation level as a code 13 after addition. Code 13 after addition
Are transmitted as they are to an information transmission line having a transmission capacity of n bits. Here, the relationship between L, m, and n is L ≦ m, m ≧
n was common.

[0003]

In this conventional A / D converter, since the output result information of the cumulative adder is sent to the information transmission line as it is, the transmission capacity of the information transmission line is m> n.
In such a case, there is a drawback in that it is limited to either the absolute value of the RF level of the information that can be transmitted or the noise fluctuation level.

[0004]

An A / D converter according to the present invention comprises an A / D converter main body for inputting a low-level analog signal containing a fluctuation component such as noise fluctuation, converting it into a digital code, and outputting it. In an A / D converter having a cumulative adder for continuously adding the digital code of the A / D converter main body a predetermined number of times, either the upper bit or the lower bit of the code of the calculation result of the cumulative adder is selected. Then, a selector for transmitting the information to the information transmission path is provided.

[0005]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. Figure 1
2, the same reference numerals as those in the conventional example of FIG. 2 have the same functions. That is, in this embodiment, the output of the cumulative adder 3 is added with the selector 4 described later.

Next, the operation of this embodiment will be described. As described above, the code 13 after the cumulative addition that has been added a predetermined number of times by the cumulative adder 3 is the upper bit (e.g. 8 bits) representing the average level of the RF level and the lower bit (e.g. 5 bits) representing the noise fluctuation level. Then, m = 13. Now, assuming that the transmission capacity of the code 14 of the information transmission line is n = 8 bits,
Transmission is possible by selecting either the upper bit or the lower bit. The selector 4 selects the upper bits or the lower bits of the m bits and sends them to the information transmission line. Although the present embodiment shows an example in which two pieces of information are selectively output for an RF signal having a lot of noise components, other information may be set in the upper bits and the lower bits and selected. Applicable.

[0007]

As described above, according to the present invention, by adding the selector, the absolute value of the RF level is required when the transmission bit capacity n of the information transmission path is smaller than the bit capacity m of the cumulative adder. If the upper bit is selected and transmitted, and if fluctuation information such as noise level is required, the A / D converter having the selection function of selecting and transmitting the lower bit is provided. is there.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional A / D converter.

[Explanation of symbols]

 1 Detection circuit 2 A / D converter 3 Cumulative adder 4 Selector

Claims (2)

[Claims] 1. An A / D converter main body for inputting a low-level analog signal including a fluctuation component such as noise fluctuation, converting the digital code, and outputting the digital code, and a digital code of the A / D converter main body a predetermined number of times. An A / D converter having a cumulative adder for continuous addition includes a selector for selecting either the upper bit or the lower bit of the sign of the calculation result of the cumulative adder and sending it to the information transmission path. An A / D converter characterized by the above. 2. When the selector sets the upper bits to m1 bits, the lower bits to m2 bits, and the transmission capacity of the information transmission path to n bits, m1 ≦ n and m2.
The A / D converter according to claim 1, wherein the A / D converter is selected after confirming that ≤n.