JP2872424B2 - Digital signal mixing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal mixing circuit applied to a digital signal processing circuit.

[0002]

2. Description of the Related Art As a conventional circuit of this type, there is a circuit using a ROM (Read Only Memory) for mixing digital signals. The circuit shown in FIG. 3 is the conventional digital signal mixing circuit, and has two ROs, ROM1 and ROM2.
M and an adder FA.
The input signal B is input to the ROM 2 and the input coefficient K is R
OM1 and ROM2 are commonly input.

The contents of ROM1 and ROM2 are respectively as shown in FIG. 4. ROM1 is written in advance with the values of input coefficient K and input signal A, and ROM2 is written in advance with the values of input coefficient K and input signal B. Output contents Ak, B
Read as k. The values of the output data Ak and Bk are obtained by multiplying the input signals A and B by the coefficient by the value of the input coefficient K as shown in FIG. In addition, ROM
1, the contents of the ROM 2 are values obtained by rounding off the decimal places of the multiplication results. Conversion output signals Ak and R of ROM 1
The converted output signal Bk of OM2 is input to the adder FA,
The addition result is output as a mixed output signal C.

In this conventional circuit, the mixing ratio of the input signals A and B is as shown in FIG. 5 depending on the value of the input coefficient K.
According to this example, the mixing ratio of the input signal has five stages, and the ratio of the input signal A being included increases as the value of the input coefficient K increases. That is, when the value of the input coefficient K is the minimum “0”, the mixed output signal C becomes equal to the input signal B, and the component of the input signal A is not included at all. That is, the mixing ratio of the input signals A and B is A: B = 0: 1. When the value of the input coefficient K is “1”, the mixing ratio of the input signals A and B is A: B = 1: 3, and when the value of the input coefficient K is “2”, the mixing ratio of the input signals A and B is Is A: B =
When the input coefficient K is "3", the mixing ratio of the input signals A and B is A: B = 3: 1. further,
When the value of the input coefficient K is the maximum “4”, the mixing ratio of the input signals A and B is A: B = 1: 0, the mixed output signal C is equal to the input signal A, and the component of the input signal B is completely Not included.

[0005]

As described above, the conventional digital signal mixing circuit uses a ROM to output a value obtained by multiplying the input signal by a coefficient corresponding to the input coefficient. R for all combinations of input coefficients
Since the data must be written in the OM, the circuit scale becomes large. Further, when testing whether the function is functioning properly, all combinations of the input signal and the input coefficient must be read from the ROM and compared with expected values, which increases the cost required for the test. turn into. In FIG. 4, when the input signal A = “F”, the input signal B = “F”, and the input coefficient K = “2”, the ROM 1,
The output of each ROM 2 is Ak = “8”, Bk =
It becomes "8". At this time, the value of the mixed output signal C in FIG. 5 is C = Ak + Bk = “10”. In this example, since the data width is 4 bits, an overflow occurs and a correct result cannot be obtained. Therefore, according to the present invention, the circuit scale is small, the test is easy, and the input signal A =
The present invention proposes a digital signal mixing circuit capable of obtaining a correct result even when “F”, input signal B = “F”, and input coefficient K = “2”.

[0006]

According to the present invention, there is provided a digital signal mixing circuit for mixing and outputting a value of a first input signal and a value of a second input signal. A first conversion circuit that outputs a plurality of values obtained by converting the value of the input signal at a predetermined rate; and a second conversion circuit that outputs a plurality of values obtained by converting the value of the second input signal at a predetermined rate A first circuit that outputs a first mixture ratio signal in which the mixture ratio of the first input signal is changed by selecting a value output from the first conversion circuit based on a value of the third input signal; A mixing ratio conversion circuit; and performing a rounding correction value prepared in accordance with the mixing ratio of the first input signal to perform rounding correction after the decimal point on the first mixing ratio signal. And a first correction circuit for selecting the first correction ratio And selecting a value output from the second conversion circuit according to the value of the third input signal to output a second mixture ratio signal in which the mixture ratio of the second input signal is changed. And a rounding correction value prepared according to the mixing ratio of the second input signal in order to perform rounding correction after the decimal point on the second mixing ratio signal. By selecting the second
And a adder for adding the rounded signal obtained from the first and second mixture ratio conversion circuits to obtain an output signal. Then, the first and second input signals each have a maximum value.
And the first and second signals selected by the third input signal.
When the mixing ratio signals are both 1/2 mixing ratio, the first and second
The correction value of one of the correction circuits is set to 0.

Further , in the present invention, the first and second conversion circuits are
It consists of a footer.

[0008]

The digital signal mixing circuit according to the present invention has a large circuit size, is relatively small in circuit size without using a ROM having many test items, and is composed of a shifter, a selector, an adder, etc. which can easily perform a test. I have. As a result, the chip area becomes smaller and the test can be performed in a short time, so that the cost can be reduced. In addition, a correct value can be obtained regardless of input conditions.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital mixing circuit according to the present invention.

In this figure, 1 and 2 are the first and second
Generates 1x, 1 / 2x and 1 / 4x of input signals A and B
And output from the output terminals 1a to 1c and 2a to 2c, respectively.
The first and second shifters to force. And one time
By outputting the input signal without conversion
１ ／ times and ４ times the input signal
Shift the signal one or two bits to the right in the shifter
It is created by In other words, these systems
The converter converts the input signal at a specified rate and outputs it.
It can be called a circuit. And each of these shifters has their own
Selectors 3 to 5 and 6 to 8 are connected corresponding to the input terminals
Have been. These selectors are connected to the above output terminals.
Input terminal n separately from the input₁, N_FourLogical value is "0" from
Level signal in common, and input terminal n₀From
As shown in FIG.
Outputs of footers 1 and 2 and input terminal n₁, N_FourInput from
It is designed to select and output. In addition, input terminal
n_Two, N_ThreeAnd n_Five, N₆Input to selectors 3 and 6
Data A₀, A₁And B₀, B₁Converts the input signals A and B
Correction terms for 1/4, 1/2, and 3/4 times
You. Especially in the case of 3/4, A₀, A₁Either one of
If "1", then "1" and B₀, B₁Either one of
If it is "1", it becomes "1". By adding this correction term
This is equivalent to rounding off the decimal point. 9 and 1
0 is the output of each of the selectors 3 to 5 and the selector 6
8 are added to each other, and an added output A shown in FIG.
k and Bk, which are first and second adders.
To convert the mixing ratio of the output from each shifter together with the
I'm doing it. 11 is the output of both adders 9 and 10
Are added and output as a mixed output signal C of the input signals A and B.
Adder. The present invention is configured as described above.
Therefore, the input signals A and B are the first and second shifters 1
Input terminal n₀Enter
When the force coefficient K is given, each of the selectors 3 to 5 and 6
2 operates according to the value of the input coefficient K, as shown in FIG.
Select the outputs of the first and second shifters 1 and 2
Output. Then, at this time, each of the input signals A and B and 1 /
In case of 4 times, 1/2 times and 3/4 times, four decimal places
It is necessary to round off, but at this time, selectors 3 and 6
Force terminal n_Two, N_ThreeAnd n_Five, N₆More correction term A₀, A₁And B
₀, B₁And output.Now, A is 4-bit data
And A = [A _Three A _Two A ₁ A ₀ ]. here,A
₀ Is LSB, A _Three Is the MSB. In this way, A
/ 4 is to shift A to the right by 2 bits
A / 4 = [00A _Three A _Two A ₁ A ₀ And A ₁ A
₀ Deviates from [] and becomes a number after the decimal point. Now, A ₁ But
If it was "1",A out of [] ₁ Is 0.
5 and rounding down to the decimal point [00A
_Three A _Two ] Is incremented by one. Realize this addition
Therefore, in FIG. 2, when K = 1, the selector 3
Is A ₁ Is output to A / 4 in the first adder 9.
Added. In the above, A ₁ Is "1", but A ₁
Is “0”, A / 4 = [00A _Three A _Two A ₁ A ₀ In
And A, the first decimal place ₁ Is "0", rounded
It is even "0". Therefore, when K = 1, A ₁ The celebrity
There is no problem even if the output is added from the rectifier 3. Next, A / 2
Since A is shifted rightward by one bit, A
/ 2 = [0A _Three A _Two A ₁ A ₀ Becomes In this case, A ₀ Is small
Since it is the first place of several points, as shown in FIG.
From A ₀ Is output. In FIG. 2, K = 3
, A / 2 from selector 4 and A /
4 is output and added by the adder 9.
When the correction term is A / 2, A ₀ , A / 4, A ₁ Met
From, A ₀ And A ₁ Is a correction term, but A ₀ And A ₁ Either
If one is “1”, the correction term is “1”. Toes
A ₀ And A ₁ Even if both are “1”, the correction term is
It is "1". As can be seen from FIG.
The correction terms are output for both A and B because their values are
1, corresponding to the maximum output of the second shifters 1 and 2
A / A smaller than A and B is performed in the selector.
2, A / 4, B / 2, B / 4
Is not output.However, input coefficient K = “2”, input
When the signal A = [F], the output of the selector 3 is set to “0”.
Or input coefficient K = “2” and input signal B = [F]
Sometimes, the output of the selector 6 is set to “0”. This
Selector 3, selector 4, selector
By adding the three outputs of the rectifier 5 with the first adder 9,
An addition output Ak is obtained. Selector 6, selector
7. Addition of the three outputs of the selector 8 by the second adder 10
By doing so, Bk is obtained. Further, each addition output Ak, B
k in the third adder 11 to add the input signal A and the input signal
A mixed output signal C obtained by mixing B is obtained. Where
Force coefficient K = “2”, input signal A = [F], input signal B =
In the case of “F”, the addition output Ak = “7” and the addition output B
k = “8” or addition output Ak = “8”, addition output B
k = “7”, and in any case, the mixed output signal C =
In addition, in the present invention, the addition outputs Ak and B are obtained.
A × 1 to obtain A × 1/2 and B × 1/2 of the value of k
/ 4 + A × １ ／, B × １ ／ + B × １ ／
Good, and to get A and B, A × 1/2 + A × 1/2, B
× 1/2 + B × 1/2 may be used. Also, the input signal
The bit widths of A, B and input coefficient K are not limited to those in the above embodiment.
Any value is acceptable.

[0011]

Since the present invention is constructed as described above, a ROM is not used as in the prior art, and therefore all combinations of the input signal and the input coefficient are used in testing the function as in the prior art. Does not require a complicated operation such as reading from the ROM and comparing with the expected value. Further, according to the present invention, the circuit scale is relatively small, and the test can be easily performed. The chip area can be further reduced by using the shifter, the selector, the adder, and the like, and the test can be performed in a short time. Moreover, the rounding correction does not perform an operation, but the first,
Since it is only necessary to select and add the rounding correction value prepared in accordance with the second mixture ratio signal based on the value of the third input signal, the processing is quick. Also, for example, if the input signal A =
[F], input signal B = “F”, input coefficient = “2”
It is possible to obtain a correct result also in.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a digital signal mixing circuit according to the present invention.

FIG. 2 is a diagram provided to explain the output of each selector and the content of its added output in the mixing circuit.

FIG. 3 is a block diagram illustrating a conventional digital signal mixing circuit.

FIG. 4 is a diagram provided to explain the contents of each ROM in the conventional circuit.

FIG. 5 is a diagram provided for explaining outputs of respective ROMs and the contents of addition of the outputs in the conventional circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st shifter 2 2nd shifter 3,4,5,6,7,8 Selector 9 1st adder 10 2nd adder 11 3rd adder

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 7/38-7/54 G06F 11/00

Claims (2)

(57) [Claims] 1. A method for mixing and outputting a value of a first input signal and a value of a second input signal, wherein a plurality of values obtained by converting the value of the first input signal at a predetermined ratio are output. A first conversion circuit that outputs a value, a second conversion circuit that outputs a plurality of values obtained by converting the value of the second input signal at a predetermined ratio, and a value that is output from the first conversion circuit. A first mixing ratio conversion circuit that outputs a first mixing ratio signal in which the mixing ratio of the first input signal is changed by selecting the first mixing ratio signal according to the value of the input signal of 3; A first round-off correction value prepared according to the mixing ratio of the first input signal is selected based on the value of the third input signal and added to the first mixing ratio signal in order to perform the following rounding correction. And a value output from the second conversion circuit is converted to a value of the third input signal. A second mixture ratio conversion circuit that outputs a second mixture ratio signal in which the mixture ratio of the second input signal is changed by selecting the second mixture signal, and performs rounding correction of the second mixture ratio signal to a decimal place. A second correction circuit for selecting a rounding correction value prepared according to a mixing ratio of the second input signal based on the value of the third input signal and adding the selected value to the second mixing ratio signal; An adder for adding the rounded signals obtained from the first and second mixing ratio conversion circuits to obtain an output signal, and wherein the first and second input signals are respectively maximum.
First and second selected by a third input signal
When the mixing ratio signals of both are 1/2 mixing ratio, the first and second
2 is configured so that one correction value of the correction circuit is 0.
Digital signal mixing circuit. 2. The digital signal mixing circuit according to claim 1, wherein said first and second conversion circuits are constituted by shifters.