JPH05268070A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make economical IC and LSI of dissimilar specifications by releasing the coupling of first and second logic circuits of a program logic array (PLA) at the time of writing through a control circuit and controlling the writing operation. CONSTITUTION:A logic circuit LG1 is a PLA having a plural logic function decision elements M11, antiM11-Mnn, and antiMnn made up of nonvolatile memory such as programmable FAMOS transistors. A logic circuit LG2 to which the output of the circuit 1 is inputted takes the similar construction. For example, when writing programs in the circuit LG1, coupling means FETTR12 and FETTR13 are turned off through a control circuit CC, separating the circuit LG1 from a circuit LG2. At the same time, shift register SR1 parallel-serial converting program data, output driving circuit, and program writing order or the like are controlled. The driving circuit and the shift register are controlled by a small number of external terminals, economically preparing IC and LSI with different specifications.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device for logic, for example, a semiconductor integrated circuit device which is particularly suitable for a small quantity and a large variety of custom or semi-custom semiconductor integrated circuit devices.

[0002]

2. Description of the Related Art Custom or semi-custom IC, L
A master slice technique and a gate array technique are known as a technique for manufacturing a small amount and a large variety of ICs and LSIs such as SI.

This kind of technology is disclosed in, for example, Nikkei Electronics (1981.4.13.122 to 144 to 144,
Pp. 203-212), and Electronic Technology (Vol. 22, No. 4, pp. 133-140). According to this type of technique, appropriate circuits and elements are formed in advance on a semiconductor substrate, and then a wiring layer pattern made of an aluminum layer for connecting these circuits and elements is determined.

[0004]

However, when an IC or the like is to be manufactured by such a method, a mask for determining a wiring pattern or the like is newly manufactured and the mask is used even when the specification is changed slightly. It must be processed after the manufacturing process used.

Therefore, even in the case of manufacturing a very small variety of ICs having a very slight difference in specifications, it is necessary to make another mask for each specification, and it takes time to manufacture. It took. Also, the cost was relatively high.

In the following description, the master slice type semiconductor integrated circuit device has a plurality of specifications by performing most of the steps in common and performing some steps, for example, an Al wiring step, with desired individual specifications. It means all the semiconductor integrated circuit devices that are held.

Therefore, an object of the present invention is to provide a low-cost IC having different specifications for each semiconductor integrated circuit,
It is to provide LSI.

Another object of the present invention is to provide an IC and an LSI capable of selecting optimum characteristics in response to variations and defects caused by the process.

Another object of the present invention is to provide a master slice type IC or LSI capable of selecting optimum characteristics in response to variations and defects caused by processes.

It is another object of the present invention to provide a semiconductor integrated circuit which can respond to a change in specifications quickly and has desired characteristics.

Another object of the present invention is to provide means for easily manufacturing semiconductor integrated circuits having different specifications from the same wafer.

Another object of the present invention is to provide a manufacturing technique which can apply the semiconductor integrated circuit to a wider field.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0014]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, a plurality of logical function determining elements are provided, a plurality of such logical function determining elements are constituted by a programmable non-volatile memory element, and a plurality of logical function determining elements are provided. A second logic circuit having a plurality of logic function determining elements composed of programmable non-volatile memory elements and receiving the output of the first logic circuit as an input; the output of the first logic circuit and the second logic circuit An input of the first logic circuit and an input of the second logic circuit at least when the programmable non-volatile memory element of the first logic circuit and the second logic circuit is programmed. A serial data signal via a common external data terminal to the non-volatile memory element of the first logic circuit. A first shift register for forming a parallel data signal to be input, and a first drive circuit for forming a write voltage to be supplied to the first logic circuit according to a control signal and a parallel data signal of the first shift register. A second shift register for receiving a serial data signal via the external data terminal to form a parallel data signal to be written to the non-volatile memory device of the second logic circuit, a control signal and the second shift register A second drive circuit that forms a write voltage to be supplied to the second logic circuit in response to the parallel data signal, and an external voltage for a write operation instruction and an external clock signal via an external terminal, The serial data signal from the external data terminal is transferred to the first
A clock signal for sequentially loading the shift register and the second shift register, and the first control signal and the second control signal for controlling the operation of the first drive circuit and the second drive circuit. A semiconductor integrated circuit device including at least a control circuit including a sequential circuit to be formed.

[0016]

According to the above-mentioned means, the control circuit can be used to control the drive circuit, the shift register and the like with a small number of external terminals.

[0017]

EXAMPLES The present invention will be described below with reference to examples.
FIG. 2 is a flowchart showing an outline of the manufacturing process of the semiconductor integrated circuit device according to the present invention.

In the figure, a common pre-process 1 shows a process from the surface oxidation to the process before forming Al wiring in a general two-layer polycrystalline Si wiring process. The formation of Al wiring shows the steps from the vapor deposition of Al to the step of removing unnecessary Al. In this step, by photoetching using a mask having each individual pattern, an IC having desired operation characteristics can be obtained from a wafer which has undergone the same step.

Further, as the wiring material at this time, in addition to Al, a material other than Al such as molybdenum or silicide may be used. The common pre-process 2 shows processes such as final passivation formation and hole formation in the pad portion. Individual IC in wafer state after drilling Al bonding pads
In order to examine the electrical characteristics of the IC, an electrical test is performed in a wafer state for each IC.

In this embodiment, a part of the logic circuit is MOSF.
Since it is composed of an EPROM using ET, it is necessary to program it so as to perform a desired operation before executing a test. This program or EPROM
Write to the prober (measuring instrument) that performs wafer test
It is convenient to write by. After measuring the electrical characteristics, the previously written program is erased. Erasure is by ultraviolet light.

The common post-processes are from the process of cutting the wafer into chips to the packaging process. After this step, predetermined program information is written in the EPROM section again to perform a desired logical operation, and at the same time, a final test, that is, a test of electric characteristics of the IC is performed to obtain a final product.

FIG. 1 is a circuit diagram of this embodiment. In the figure, LG ₁ and LG ₂ are logic circuits. Logic circuit L
G ₁ is a programmable logic function determining element M ₁₁ arranged in a matrix, bars M ₁₁ to M _nm , bar M _nm, and a plurality of input lines (word lines) W ₁ , bars W ₁ to W _m , bar W. _m and a plurality of output lines (data lines) D ₁ to D _n . Similarly, the logic circuit LG ₂ includes a plurality of programmable logic function decision elements m ₁₁ to m _nm.
And input lines w ₁ to w _n and a plurality of output lines d ₁ to d _m .

The logic function determining elements in the logic circuits LG ₁ and LG ₂ are not particularly limited, but in this embodiment, they are FAMOS transistors. FAMOS
The transistor has a relatively low threshold voltage in advance,
A high threshold voltage is obtained by applying a write voltage during programming as described later. A FAMOS transistor with a high threshold voltage remains off when a voltage with a read level is applied to its gate, and is therefore equivalent to its absence. The logic circuits LG ₁ and LG _{2 form} a PLA (Programmable Logic Array).

DR ₁ to DR _n are output line driving circuits, and when desired data is to be written in the FAMOS transistor in the logic circuit LG ₁ , a low level of approximately 0 volt or a high level of approximately the write voltage V _pp is set. Output. The output line drive circuits DR ₁ to DR _n are the logic circuits L
When the normal output level signal should be output from G ₁ ,
A load element for applying a bias voltage to the output lines D ₁ to D _n is included. The load element is a switch MOSFET T ₇ connected in series between the power supply terminal V _cc and the output line D ₁ , as shown in the output line drive circuit DR ₁ , for example.
Depletion MO that combines the gate and source
SFETT ₆ and.

DW ₁ , bar DW ₁ to DW _m , bar D
W _m is an input line drive circuit, which is an FA in the logic circuit LG ₁ .
When the desired data is to be written to the MOS transistor, a low level of approximately 0 V or a high level of approximately the write voltage V _pp is output, and when a normal output level signal is to be output from the logic circuit LG ₁ , it is approximately 0. It outputs a low level of volt or a high level of approximately the level of the power supply voltage _Vcc .

MOSFETs arranged on the input side of the input line drive circuit DW ₁ , bars DW ₁ to DW _m , and bar DW _m
T ₂₅ to T _{28 form} a switching gate. When the logic circuit LG ₁ should output a signal of a normal output level, the control signal bar WE is set to a high level so as to turn on the MOSFETs T ₂₅ to T ₂₆ .

Therefore, at this time, the signals output from the signal forming circuit (not shown) formed on the same semiconductor chip are the terminals I ₁ to I _m and the MOSFETs T ₂₅ to T.
It is supplied to the input line drive circuit via ₂₆ . Logic circuit LG
_When the threshold voltage of the FAMOS transistor in ₁ is to be appropriately controlled or changed, the control signal WE is set to low level so as to turn on the MOSFETs T ₂₇ to T ₂₈ . At this time, the output signal of the shift register SR ₂ is supplied to the input line drive circuit.

Output lines D ₁ to D of the logic circuit LG _1
n is coupled to the input lines w ₁ to w _n of the logic circuit LG ₂ via switch MOSFETs T ₁₂ to T ₁₃ . The switch MOSFETs T ₁₂ to T ₁₃ are switch-controlled by the control signal φ _{co and} are turned on when the logic circuit LG ₁ should output a signal of a normal level. The switch MOSFETs T ₁₂ to T ₁₃ are turned off when the threshold voltage of the FAMOS transistors of the logic circuits LG ₁ and LG ₂ should be controlled.

[0029] The to no input lines w ₁ of the logic circuit LG ₂ w _n, to no driving circuit dw ₁ are bonded dw _n, the to the output line d ₁ without d _m, the drive circuit dr ₁ through dr _m
Are combined. The drive circuits dr ₁ to dr _m are switch MOSFETs for supplying the output lines d ₁ to d _m with a bias voltage substantially at the level of the power supply voltage V _cc when the logic circuit LG ₂ should output a normal level signal.
It includes a load element consisting of T ₁₄ and depletion MOSFET T ₁₆ .

The input line w ₁ and bar w ₁ of the logic circuit LG ₁ are paired, and similarly w _m and bar w _m are paired. When a normal level signal should be output from the logic circuit LG ₁ , the input line drive circuit D should be connected to each pair of input lines.
Signals of true and complementary levels corresponding to the signals supplied to the terminals I ₁ to I _m via W ₁ , bars DW ₁ to DW _m , and bar DW _m are supplied.

Each FAMOS transistor as a logic function determining element in a logic circuit has its threshold voltage controlled by a write operation as will be described later. When the output line D ₁ should only correspond to the signal on terminal I ₁ , only _one of M ₁₁ and M ₁₁ is left at a high threshold voltage and the other is left at a low threshold voltage. .. The remaining FAMOS transistors coupled to output line D ₁ are brought to a high threshold voltage.

In this case, the high threshold voltage is the input line w ₁ ,
By making the values of the read levels applied to the bars w ₁ to w _m and w _m larger than the high level,
The FAMOS transistor having the high threshold voltage maintains the off state and does not perform the switch operation. The low threshold voltage FAMOS transistor is switched by a signal applied to its gate.

Therefore, when only one of M ₁₁ and M ₁₁ is set to the low threshold voltage as described above, the output line D ₁ is connected to the terminal I.
_It is set to low level only when the ₁ signal is set to a predetermined level. Similar to a general address decoder, in order to bring the output line D ₁ to the low level only when a predetermined combination of the signals applied to the terminals I ₁ to I _m is used, M ₁₁ and the bars M ₁₁ and M _1m are set. One of the pair of FAMOS transistors, such as bar M _1m , is left at the low threshold voltage and the other at the high threshold voltage.

When the logic circuits LG ₁ and LG ₂ are normally operated, the output levels of the output lines D ₁ to D _n of the logic circuit LG ₁ are almost 0 volt depending on the signals of the terminals I ₁ to I _m . Low level or almost power supply voltage V _cc
Of the output lines d ₁ to d _m of the logic circuit LG ₂ are similarly set to the low level or the high level in response to the signal supplied from the logic circuit LG ₁ .

The circuit of the illustrated embodiment is based on the logic circuit LG ₁ ,
In order to control the threshold voltage of the FAMOS transistor of LG ₂ , the control circuit CC, the shift registers SR ₁ , SR ₂ , Sr ₁ ,
It includes Sr ₂ and flip-flop circuits F ₁ and F ₂ .

The shift registers SR ₂ and Sr ₂ include:
A data signal for controlling the threshold voltage of the FAMOS transistor is supplied via the external terminal D _{in of the} IC. The serial data signal supplied to the external terminal D _in is converted into a parallel data signal by the shift register SR ₂ or Sr ₂ . According to this configuration, it becomes possible to prevent a large increase in the number of external terminals of the IC, and the FAM
It is possible to speed up the control operation of the threshold voltage of the OS transistor, that is, the writing operation.

The control circuit CC receives the write voltage V _pp and the periodic pulse via the external terminal of the IC. Control circuit C
C is a pulse signal φ _OR that keeps the shift registers SR ₁ and Sr ₂ in a reset state when the write voltage V _pp is not supplied, and flip-flop circuits F ₁ and F.
_The pulse signals R for maintaining the ₂ in the reset state are output.

At this time, the pulse signal φ _wt ,
φ _wt is maintained at low level, and pulse signals φ _LC , φ _CO ,
The bar WE is maintained at the high level. Therefore, at this time, the MOSFE in the output drive circuit DR ₁ is
TT ₂ and T ₃ are maintained in the off state.

Input drive circuit DW ₁ , bars DW ₁ to D
W _m , DW _m depletion MOSFET T ₉
Is favorably turned on by the inverted signal (bar Q) output from the flip-flop circuit F ₁ . Therefore, the output of the inverter circuit composed of the input drive circuit DW ₁ , the bars DW ₁ to DW _m , and the MOSFETs T ₁₀ and T ₁₁ in the bar DW _m is input via the MOSFET T ₉ to the corresponding input line W ₁ , bar W ₁ to W ₁ . It is supplied to DW _m and bar DW _m .

The control circuit CC also includes a detection circuit for detecting the write voltage V _pp and an appropriate sequential circuit whose operation is controlled by the detection circuit. In response to this, the control circuit CC receives the synchronization signal φ when the write voltage V _pp is supplied.
_It forms various pulse signals synchronized with _SS .

Next, the write operation of the circuit shown in FIG. 1 will be described.

In the figure, when a write voltage such as approximately 25 volts is applied to the write voltage V _pp terminal, the control circuit CC detects the rising of the write voltage V _pp to detect the all set signal having a predetermined pulse width. To the shift register SR ₁ . At the same time, the write timing control clock φ _WT which is constantly set to the “0” level is set to the constant “1” level. In addition, the load control signal φ _LC is “0”
Be leveled. Also, the cutoff switch control signal φ
_CO is set to "0" level. Also, the bar WE is set to the low level.

Thereafter, writing to the logic circuit LG ₁ is first performed according to the following operating means.

(1) The control circuit CC outputs the shift pulse φ _S2 by supplying the data in series to the data input terminal D _in and supplying the synchronizing signal φ _SS synchronized with the data to the synchronizing terminal. As a result, the sequence data is set in the shift register SR ₂ .

(2) The output bar Q of the flip-flop circuit F ₁ is set to "0" in synchronization with the synchronizing signal φ _SS after data is set in all positions in the shift register SR ₂ , and the shift register Output of the first bit of SR ₁ Q ₁₁
Of the pulse signals S and φ _{S1 that} cause the control circuit C to go to "0"
It is output from C. As a result, either one of all word line pairs has a high potential, and the data line D ₁ can be selected.

(3) Write timing control pulse φ _WT in synchronization with an appropriate timing of the synchronizing signal φ _SS , for example, falling edge
To "0". Since the output Q ₁₁ of the first bit of the shift register SR ₁ is set to “0”, the data line D ₁ is
By _{setting the} pulse φ _WT to “0”, it is set to a high potential. As a result, all the memory cells set on the data line D ₁ are set to the desired state. That is, writing is performed.

(4) After the above, the series data to be written in the memory cell connected to the _second data line D ₂ is input to the shift register SR ₂ again.

(5) The output Q ₂ of the shift register SR ₁ is set to "0" by the same operation as the above (2).

(6) By the same operation as the above (3), writing to the memory cell connected to the data line D ₂ is performed.

(7) By repeating the same steps thereafter, writing to the memory cells connected to all the data lines is completed.

(8) After the completion of writing to all the memory cells in the logic circuit LG ₁ , the control circuit CC sets the synchronization signal φ.
When _SS is supplied again set signal to the flip-flop F _1, and outputs the all-reset signal to the shift register SR _1. The write timing control clock φ _WT is constantly set to the “0” level, and the bar WE is set to the high level.

(9) After the above, the writing to the logic circuit LG ₂ is performed by the same operation as the logic circuit LG ₁ .

[0053] (10) When the write voltage V _pp is the low level, by the falling edge is detected, the output bar Q ₂ of the shift register SR ₂ is set, the shift register S
The outputs q ₁₁ to q _{1m of} r ₁ are reset.

(11) When the write timing control clock φ _WT is constantly set to "0" and the cutting MOSFET is turned on, reading is possible. Here, the read operation is performed by the input terminals I ₁ to I _m and the output terminals O ₁ to O _{m as in the case} of the normal PLA.

That is, the potentials of the data lines D ₁ to D _n of the logic circuit LG ₁ are determined by the signals applied to the input terminals I ₁ to I _m, and the potentials are determined by the logic circuit LG _2.
Is output to. In the logic circuit LG ₂ , similarly, the potentials of the data lines d ₁ to d _m are determined and output from the output terminals O ₁ to O _m as the output signals of the two-stage ROM.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above embodiments, the FAMOS has been mainly described as an example of the non-volatile memory, but not only the EPROM by the MOSFET but also the fuse ROM which is a bipolar IC or the PROM of the PN junction destruction type may be used. May be a combination of.

In the above description, the case where the invention made by the present inventor is mainly applied to a one-chip microcomputer, a gate array, a master slice logic IC and the like, which are the fields of use thereof, has been described, but the present invention is not limited thereto. For example, bipolar linear IC or logic I
C, DA / AD conversion IC, voice synthesis IC, MOSRA
The present invention can be applied to a semiconductor integrated circuit device having a PROM at least on a chip such as M, and having different specifications or circuits for each chip, and its manufacturing.

[0059]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

According to the present invention, a master slice type IC
It is possible to easily and quickly produce a large amount of a small number of products. That is, for example, in the case of a one-chip microcomputer, the specifications of the greatest common divisor are built in by the conventional master slice process, and various specifications are finally desired in the EPROM built on the chip. It can be realized by writing the information of.

In the embodiment of the present invention, since the double-layer polycrystalline silicon process is used, a high speed dynamic RAM, a highly accurate capacitor, a high capacity stacked capacitor, a CCD, etc. are added to the chip by an extra process. It can be easily created without adding.

Further, by adding some steps, EEPRO
It is also possible to mount M on the chip. In this case, the information and the specification of the semiconductor device itself can be electrically changed easily, which is very useful.

The write sequence is performed in parallel for each data line as described in the embodiment, so that the write time can be greatly reduced compared to the case where the write is performed for each bit. it can.

Further, in the manufacturing method of the present invention, after measuring the parameters easily influenced by the process in the wafer test, it is possible to freely select the optimum condition in accordance with the process variation.

For example, a plurality of diffused resistors having different resistance values are prepared in advance, and the optimum diffused resistor is taken into the circuit in the writing / step 2 of FIG. 2 based on the result of the wafer test, or unnecessary ones are cut off. Since such processing can be easily performed, it is effective for manufacturing ICs and LSIs that require high precision.

Further, according to the manufacturing method of the present invention, it is possible to provide a means suitable for manufacturing ICs having different specifications on one wafer, which has been difficult in the past.

That is, when integrated circuit chips having different specifications are manufactured on one wafer by a conventional exposure apparatus of, for example, 1: 1, the mask of at least one step is set to 1 in accordance with the desired specifications even if the specification difference is small. There are different patterns on the two mask substrates, which is a problem in manufacturing the mask.

Further, when a similar multi-specification IC is manufactured using a reticle such as 10: 1 reduction exposure, it is necessary to replace the reticle according to a plurality of specifications during stepping, and throughput is lowered. I had no choice. However, according to the present invention, since the final specification can be determined after the IC, LSI, etc. are divided into chips, the above-mentioned manufacturing problems do not occur.

Further, according to the present invention, it is possible to inexpensively supply ICs made of the same wafer, which have never been considered in the past, and which have different specifications even if any one of them is viewed. Yes, for example I for electronic door locks
It can be applied to C, game ICs, and the like.

Conventionally, when the specifications of individual products are different, it is often the case that they are individually written to an externally mounted or on-chip EPROM, but with this method, for example, door lock number information is relatively easy. Could have been known to a third party.

However, in the case of the present invention, it is relatively easy to set the write circuit itself so that it does not operate after the writing and two steps of FIG. A lock IC can be provided.

By incorporating the IC according to the present invention into a cash card or the like, the same effect as the electronic lock can be obtained.

[Brief description of drawings]

FIG. 1 is a PLA using an EPROM which is an embodiment of the present invention.
FIG. 3 is a configuration diagram of a main part of the write circuit.

FIG. 2 is a flow chart of a manufacturing process showing an embodiment of the present invention.

[Explanation of symbols]

CC control circuit LG ₁ logic circuit LG ₂ logic circuit T ₁₂ switch MOSFET T ₁₃ switch MOSFET

Claims (1)

[Claims] 1. A first logic circuit comprising a plurality of logic function determining elements, wherein the plurality of logic function determining elements are programmable non-volatile memory elements, and a plurality of logic function determining elements. A second logic circuit having a plurality of programmable logic function determining elements each composed of a programmable non-volatile memory element and receiving the output of the first logic circuit as an input; the output of the first logic circuit and the second logic circuit Is provided between the first logic circuit and the second logic circuit.
A coupling means controlled to disconnect the output of the first logic circuit and the input of the second logic circuit when the programmable non-volatile memory element of the logic circuit is programmed; and a common external data terminal. A first shift register for receiving a serial data signal via the first shift register to form a parallel data signal to be written to the non-volatile memory element of the first logic circuit, and a control signal and a parallel data signal of the first shift register And a first drive circuit that forms a write voltage to be supplied to the first logic circuit, and a serial data signal is received via the external data terminal and written to the nonvolatile memory element of the second logic circuit. A second shift register for forming a parallel data signal to be supplied to the second logic circuit according to a control signal and the parallel data signal of the second shift register. A second drive circuit for forming a write voltage, and an external voltage for instructing a write operation and an external clock signal via an external terminal, and receiving a serial data signal from the common external data terminal, the first shift register, the A clock signal for sequentially loading the second shift register,
And a control circuit including a sequential circuit for forming at least the first control signal for controlling the operation of the first drive circuit and the second drive circuit, and the second control signal. Semiconductor integrated circuit device.