JPH05267582A - Manufacture of semiconductor wafer and semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area of a resistive block and also the area of a chip by forming desired resistive elements through high-energy ion implantation in the region, where no element is formed, of a master slice system semiconductor wafer, where elements other than the resistive elements are previously built-in. CONSTITUTION:Other elements excepting resistive elements are formed on a silicon wafer and a region(resistive block) 23, in which the resistive elements are expected to be formed, is provided in an area within the range of 50X50-500X500mum<2>. Then, an insulating film 7 is formed all over the surface so that a master wafer is completed, an aluminum film 9 is formed on the wafer, and a desired pattern is formed on the basis of the content of an order received from a user. Subsequently, a P-type diffused layer 8 is selectively formed in the N<->-type epitaxial layer 2 obtained by high-energy ion implantation so that the resistive elements 24 are formed. After that, holes are made in the predetermined places of the insulating film 7 so that the elements are connected by a wiring, and a passivation film is formed all over.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type semiconductor wafer (hereinafter referred to as a master wafer) in which an element to be used is prefabricated and a method of manufacturing a semiconductor device, and more particularly to a master used in an analog master slice type. The present invention relates to a wafer and a semiconductor device manufacturing method using the same.

[0002]

2. Description of the Related Art FIG. 3 shows a sectional view (A) and a plan view (B) of a semiconductor device using a conventional analog master slice type master wafer, and FIG. 4 shows a manufacturing method using this master wafer.

An N ⁻ type epitaxial layer 2 is grown on a P type substrate 1 with an N ⁺ type buried layer 3 in between, and a P ⁺ type epitaxial layer 2 is formed.
The mold element isolation diffusion layer 11 is formed (element isolation step). Next, in the transistor block 12, the N ⁺ type collector diffusion layer 4, the P ⁻ type base diffusion layer 5, and the N ⁺ type emitter diffusion layer 6 are formed.
To form a transistor (transistor forming step). Next, the P-type diffusion layer 8 is formed in the resistance block 13 to form the resistance elements 14 and 16 (resistance formation step). Next, the master wafer is entirely covered with the insulating film 7 (insulating film forming step) to be completed and stocked.

Then, an opening is formed at a predetermined position of the insulating film 7 of the master wafer stocked according to the order contents (specified contents) from the user, and the necessary elements 14 are connected by the wiring 15 such as aluminum (insulating film). Opening process / wiring forming process). Next, a passivation film is entirely formed (cover film forming step) to form an integrated circuit device.

[0005]

This conventional manufacturing method,
In the manufacturing system, as shown in FIG. 3B, many resistor elements 16 that are not used to select only the necessary resistor element 14 from the many resistor elements 14 and 16 that have already been formed are generated. There is a problem that the area becomes large and the yield of pellets from one wafer decreases.

[0006]

A feature of the present invention is that in a master-slice semiconductor wafer in which an element to be used is prefabricated, the prefabricated element is an element other than a resistance element, and A semiconductor wafer has a region of a predetermined area in which elements are not formed and in which a resistance element is required in order to obtain a semiconductor device from the semiconductor wafer.

Another feature of the present invention is a step of preparing a master slice type semiconductor wafer in which elements other than a resistance element are pre-fabricated and having a region where the element is not formed, and a user. And a step of forming a desired resistance element by ion implantation of high energy in a region of the master slice type semiconductor wafer where the element is not formed by designation.

From the practical viewpoint, it is preferable that the area where the element is not formed is within the range of 50 × 50 μm ^{2 to} 500 × 500 μm ² .

[0009]

The present invention will be described below with reference to the drawings. FIG. 1 shows a sectional view (A) and a plan view (B) of a semiconductor device using an analog master slice type master wafer of one embodiment of the present invention, and FIG. 2 shows a manufacturing method using this master wafer.

First, elements other than resistance elements such as NPN transistors, PNP transistors, and MOS transistors are formed on a silicon wafer, and a region (resistance block) 23 for forming future resistance elements is provided. Then, an insulating film 7 having a thickness of about 500 nm (nanometer) is formed on the entire surface by C
It is formed by the VD method to complete the master wafer.

Referring to FIGS. 1 and 2, the N ⁻ type epitaxial layer 2 is grown on the P type substrate 1 with the N ⁺ type buried layer 3 in between to form the P ⁺ type element isolation diffusion layer 11. (Device isolation step). Next, the N ⁺ type collector diffusion layer 4, the P ⁻ type base diffusion layer 5, and the N ⁺ type emitter diffusion layer 6 are formed in the transistor block 22 to form a transistor (transistor forming step). Next, the master wafer is entirely covered with the insulating film 7 (insulating film forming step) to be completed and stocked.

In this case, the area of the region (resistor block) 23 in which a resistive element is formed in the future is 50 × from a practical point of view.
It is preferably in the range of 50 μm ^{2 to} 500 × 500 μm ² . Further, it is effective to select a master wafer having a resistance block area required by the user by preparing several kinds of master wafers having different resistance block areas within this range.

Then, on the stocked master wafer, an aluminum film 9 having a film thickness of about 1 μm, which serves as a mask at the time of ion implantation, is formed, and the photolithography technique is carried out based on the order contents (specified contents) from the user. Thus, a desired pattern is formed on the aluminum film 9. Next, using an ion implantation method, boron 10 is implanted into the portion where the aluminum film 9 is removed through the insulating film 7 at a high energy of 300 to 500 keV to selectively form the P-type diffusion layer 8 on the N ^- type epitaxial layer 2. Then, the resistance element 24 is formed (a resistance forming step by high energy ion implantation).

Thereafter, according to the contents of the order (specified contents) from the user, an opening is formed in a predetermined portion of the insulating film 7 by the photolithography technique, and the element is connected by a wiring such as aluminum ( Insulating film opening process / wiring formation process). Finally, a plasma silicon nitride film having a film thickness of about 0.5 μm is entirely formed as a passivation film (cover film forming step) to form an integrated circuit device.

[0015]

As described above, according to the present invention, when a manufacturer or a user completes an integrated circuit device by performing the latter half of the manufacturing process by a master slice method, for example, an analog master slice method, the resistance of the minimum area required. By selecting the block 23 and using the ion implantation technique with high energy of 300 to 500 keV, it is possible to form the required number of resistance elements 24 having a free pattern before forming the wiring such as aluminum. Therefore, as compared with the conventional integrated circuit device in which the resistance block has a large area due to the existence of the unnecessary resistance element, the area of the resistance block forming the resistance element can be significantly reduced, and the chip area can be further reduced. Has the effect that can. Further, it has a great effect that it can promptly deal with a customer who needs a large resistance change.

[Brief description of drawings]

1A and 1B are diagrams showing a master wafer according to an embodiment of the present invention, in which FIG. 1A is a sectional view and FIG. 1B is a plan view.

FIG. 2 is a diagram showing a flow of a manufacturing method according to an embodiment of the present invention.

FIG. 3 is a diagram showing a prior art master wafer,
(A) is a cross-sectional view and (B) is a plan view.

FIG. 4 is a diagram showing a flow of a conventional manufacturing method.

[Explanation of symbols]

1 P-type substrate 2 N ^- type epitaxial layer 3 N ⁺ type buried layer 4 N ⁺ type collector diffusion layer 5 P ⁻ type base diffusion layer 6 N ⁺ type emitter diffusion layer 7 Insulating film 8 P type diffusion layer 9 Aluminum film 10 Boron 11 P ⁺ type element isolation diffusion layer 12,22 Transistor block 13,23 Resistance block 14,16,24 Resistance element 15 Aluminum wiring

Claims (5)

[Claims] 1. A master slice type semiconductor wafer in which an element to be used is pre-fabricated, the pre-fabricated element is an element other than a resistance element, and a region having a predetermined area in which the element is not formed. A semiconductor wafer having a region requiring a resistance element in order to obtain a semiconductor device from the semiconductor wafer. 2. The area of a predetermined area where the element is not formed has an area of 50 × 50 μm ^{2 to} 500 × 500 μm ^2.
The semiconductor wafer according to claim 1, having an area within the range. 3. A step of preparing a semiconductor wafer of a master slice method in which elements other than a resistance element are preliminarily formed and which has a region in which the element is not formed, and the master slice method is specified by a user. A step of forming a desired resistance element by ion implantation with high energy in a region of the semiconductor wafer on which the element is not formed. 4. A plurality of types of semiconductor wafers having different areas of regions in which the elements are not formed are prepared, and one type of semiconductor wafer is selected from the plurality of types of semiconductor wafers by the user's designation, and 4. The method for manufacturing a semiconductor device according to claim 3, wherein a resistance element is formed on the selected semiconductor wafer, and then wiring is formed. 5. The area of the region in which the element is not formed is within the range of 50 × 50 μm ^{2 to} 500 × 500 μm ² 3.
A method of manufacturing a semiconductor device according to item 1.