JPH05265410A - Data-side driving device for semiconductor device for multi-output driving and liquid crystal display panel - Google Patents

Abstract

PURPOSE:To provide the data-side driving device for the semiconductor device for multi-output driving and liquid crystal display panel which saves the space and makes the output level of a driving signal multistage. CONSTITUTION:A unit output circuit which is adaptive to an eight-gradation display has the holding output part 1 consisting of a 3-bit input shift register 4 and a latch circuit 5 composed of D-type flip-flops 10 and 9, a selector 2 equipped with analog switches 8a, 8b, and 8c which select a weighted reference voltage 12 for gradations according to the parallel data signal outputted from the output part 1, and the voltage addition and amplification part 3 consisting of resistances 7a, 7b, 7c, and 6 and an operational amplifier 15 which add and amplify the selected reference voltage for gradations.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-output driving semiconductor device and a data side driving device of a liquid crystal display panel.

[0002]

2. Description of the Related Art A liquid crystal display panel, which is a typical flat panel type display device, is used as a display device for a liquid crystal television or OA, and it is roughly classified into a simple matrix type and an active matrix type in terms of its display mechanism. .. Among them, the active matrix type liquid crystal display panel has a feature that high display quality can be obtained because high gray scale display is possible. Such an active matrix type (T
The schematic configuration of the FT) liquid crystal display panel is, for example, as shown in FIG. 6, in which the data signal lines 46 and the scanning signal lines 47 are orthogonal to each other in a matrix type, and a TFT is provided for each display pixel at the intersection.
A (thin film transistor) 48 and a capacitor 49 are arranged, and the voltage applied across the liquid crystal 50 is output to the data side drive circuit 43 and the scan side drive circuit 44 based on the gradation display signal SP1 and the display control signal SP2. The alignment state of the liquid crystal 50 is controlled by controlling while adjusting the timing. Here, the data side driving circuit 43 and the scanning side driving circuit 44 are configured as a semiconductor integrated circuit, and several tens to one hundred and several tens of unit output circuits so that the alignment state of each liquid crystal 50 can be individually controlled. Have. In the TFT liquid crystal display panel 45 having such a configuration, the gradation display is performed by utilizing the fact that the degree of alignment of the liquid crystal 50 changes according to the voltage applied to the liquid crystal 50.
That is, the level of the drive signal output from the data side drive circuit 43 is changed based on the gradation display signal SP1.

Therefore, a unit output circuit corresponding to 8-gradation display shown in FIG. 7 is formed on the data side drive circuit side of the conventional liquid crystal display panel. In the unit output circuit for 8-gradation display shown in this figure, the transferred 3-bit display input data 61 is taken in by the holding output unit 62 and output as a parallel data signal in synchronization with the latch pulse. .. Here, the hold output unit 62 is a flip-flop that takes in and transfers the 3-bit display input data 61 in synchronization with a clock pulse, and includes three flip-flops and a 3-bit input shift register 63. It has a D-type flip-flop 64 and a latch circuit 66 which outputs a parallel data signal corresponding to the 3-bit display input data 61 transferred from the 3-bit input shift register 63 to a comparison circuit 67 in synchronization with a latch pulse. ..
The comparator circuit 67 compares the counter output 68 of the 3-bit binary counter and creates a sampling pulse. This sampling pulse is applied to the level shifter 6
In the sampling and holding circuit 70, the analog switch 71 samples a predetermined voltage of the eight stepped waves based on the level-converted sampling pulse, and the capacitor 72 stores Hold on. This is impedance-converted from the operational amplifier 73 of the voltage follower and output from the output terminal as a gradation display voltage signal. In the liquid crystal display panel, the alignment state of the liquid crystal is controlled based on this output signal, and 8-gradation display is performed.

[0004]

However, in the data side driving device of the conventional liquid crystal display panel, the circuit configuration of the unit output circuit becomes complicated as the number of display gray scales increases, so that the display becomes high gray scale. There is a problem that there is a limit to improving the display quality. For example, when the unit output circuit shown in FIG. 7 is changed from the 8-gradation display type to the 16-gradation display type, either the D-type flip-flop 6 of the 3-bit input shift register 63 or the latch circuit 66 is changed.
Not only 4 and 4, 74, respectively, but also the counter output signal line 75 and the exclusive OR (EXOR) circuit 76.
There are also four, and the 3-input NAND 77 has a 4-input NA.
Become ND. Furthermore, since the sampling time in the sampling and holding circuit 70 is shortened to 1/2, it is necessary to take measures to improve the accuracy of the sampling and holding circuit 70. Here, the exclusive OR circuit 76 shown in FIG. 8A is generally composed of two inverters 78 and three NANDs 79 as shown in FIG. 8B, or the exclusive OR circuit 76 shown in FIG. ), It is composed of two inverters 78 and two analog switches 80. Therefore, even if only one exclusive OR circuit 76 is added, the number of logic elements is increased from four to five.

In addition to the unit output circuit shown in FIG. 7, the unit output circuit shown in FIG. 9 may be employed. Similarly, as the number of display gradations increases, the unit output circuit also increases. However, there is a problem in that there is a limit to improving the quality of display because the configuration of (3) becomes complicated. That is, this unit output circuit is composed of three D-type flip-flops 91 and 92.
The parallel data signals output from the bit input shift register 93 and the latch circuit 94 are transferred to the decoder 98 configured by the 3-input NAND 96 and the inverter 97 via the level shifter 95, and the analog data is output based on the data output from the decoder 98. The selector 100 using the switch 99 is configured to select any of the eight gradation signals 101. For this reason, when the display for 8 gradations is changed to the display for 16 gradations, the level shifter 95
In addition, the number of three-input NANDs 96, inverters 97, and analog switches 99 that compose the decoder 98 and the selector 98 is doubled. Moreover, since these circuit elements are high-voltage systems, it is necessary to secure the withstand voltage. As a result, the element occupying area becomes large. It is doubled and is not suitable for higher gradation than the unit output circuit shown in FIG.

In view of the above problems, the object of the present invention is to
It is possible to increase the number of output levels of the multi-output driving signal while keeping the increase in the number of constituent elements of the unit output circuit to a minimum. For example, in a liquid crystal display panel, a multi-output driving semiconductor capable of high gradation display. It is to realize a device and a data side driving device of a liquid crystal display panel.

[0007]

Means for Solving the Problems In order to solve the above-mentioned problems, means taken in a semiconductor device for multi-output driving according to the present invention is to hold a fetched data signal as parallel data in synchronization with a latch signal. An output unit, a selector for selecting each weighted reference voltage based on the parallel data output from the holding output unit, and a voltage corresponding to the data signal obtained by performing an operation on each reference voltage selected by this selector. That is, a unit output circuit including a calculation unit that outputs a signal is provided.

Here, the arithmetic unit sets a predetermined difference between the sum of the reference voltages selected on the non-inverting input side and the sum of the reference voltages selected on the inverting input side among the selected reference voltages. It is possible to employ a differential amplification section that amplifies with the amplification degree of and outputs a voltage signal.

Further, the arithmetic unit is a voltage adding unit for adding each selected reference voltage and outputting as a voltage signal, preferably, the reference voltage is added as this voltage adding unit and is amplified with a predetermined amplification degree. A voltage addition amplification unit can be adopted. In this case, output voltage adjusting means for inputting the offset adjusting voltage to the output voltage adding section is provided so that the voltage signal output from the voltage adding section (voltage adding amplification section) can be offset. It is preferable to keep it.

The multi-output driving semiconductor device having such a structure includes a shift register which, in the holding output section, fetches a gradation display signal as a data signal in synchronization with a clock signal and transfers a parallel data signal, By providing a parallel data signal transferred from the shift register in synchronization with a latch signal whose timing with the scanning side is to be adjusted, the latch circuit can be used as a data side driving device of a liquid crystal display panel.

[0011]

The operation of the multi-output driving semiconductor device according to the present invention having the above means will be described by taking as an example the case where it is used in a data side driving device of a liquid crystal display panel to enable display of 8 gradations. .. In the data side driving device according to the present invention, the selector, for example, weights the unit voltage level X (v) on the basis of the parallel data signal output from the holding output unit, to select each reference voltage 0 (v), X (v). v), 2X (v),
A predetermined reference voltage is selected from 4X (v). Then, the arithmetic unit performs an arithmetic operation on these selected reference voltages and outputs it as a voltage signal.

For example, in the present invention, when the arithmetic unit is configured as a differential amplification unit having an amplification factor of 2, the reference voltage on the non-inverting input side is set to 4X (v) and selected, while the inverting operation is performed. When 0 (v) reference voltage is selected on the input side,
The output voltage is represented by the following formula and is 8X (v).

V _out = 2 (4X-0) On the other hand, the reference voltage on the inverting input side is X (v), 2X
When all of them are selected as (v), and a reference voltage of 0 (v) is selected on the non-inverting input side, the output voltage is represented by the following equation and becomes −6X (v).

V _out = 2 {0- (X + 2X)} That is, 8X (v) from -6X (v) to 2X (v).
Output voltage up to.

Further, in the present invention, when the arithmetic unit is configured as a voltage adding unit, the selector is arranged to have the reference voltage 0 weighted to the unit voltage level X (v), for example.
A predetermined reference voltage is selected from among (v), X (v), 2X (v), and 4X (v), and the voltage adding unit adds these selected reference voltages. As a result, the voltage signal output from the voltage adder has any value from 0 (v) to 7X (v).

As described above, since the reference voltage is increased by the arithmetic section such as the differential amplifier section or the voltage adder section (voltage adder / amplifier section), the circuit up to the selector can be constituted by a low-voltage space-saving circuit element. Therefore, it is possible to realize multi-steps of the signal output level, that is, high gradation of the liquid crystal display panel, without increasing the number of constituent elements of the unit output circuit to a minimum and increasing the space.

[0017]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

[Embodiment 1] FIG. 1 is a schematic configuration diagram of a unit output circuit in a data side driving device of a liquid crystal display panel according to Embodiment 1 of the present invention.

In the figure, the unit output circuit has a schematic structure in which a gradation display signal 13 (data signal) fetched in synchronization with a clock pulse is a 3-bit parallel data signal 16.
The holding output unit 1 that outputs a, 16b, and 16c in synchronization with the latch pulse, and the weighted grayscale reference voltage 12 (based on the parallel data signals 16a, 16b, and 16c output from the holding output unit 1 ( A selector 2 for selecting a reference voltage) and a voltage addition amplifier 3 for adding and amplifying the gradation reference voltage 12 selected by the selector 2.
(Computing unit, voltage adding unit).

Here, the hold output unit 1 is a gradation display signal 1 which is digitized in synchronization with a clock pulse.
3 bit input shift register 4 that takes in and transfers 3 as output data 14, and output data 14 transferred from this 3 bit input shift register 4 in parallel data in synchronization with a latch pulse whose timing with the scanning side should be adjusted. The latch circuit 5 outputs the signals 16a, 16b, 16c, and the 3-bit input shift register 4 and the latch circuit 5 are both configured by D-type flip-flops 10, 9. The selector 2 has analog switches 8a, 8b and 8c corresponding to the parallel data signals 16a, 16b and 16c sent from the latch circuit 5, respectively.
a, 8b, 8c are parallel data signals 16a, 16b, 1
Based on 6c, either the weighted gradation reference voltage 12 or the reference voltage 11 is selected. Further, the voltage adder 3 includes the analog switches 8
resistors 7a, 7b, 7c serially connected to a, 8b, 8c
And an operational amplifier 15 having a resistor 6 that regulates the amplification of the voltage level generated at the output terminal by the balance with these resistors 7a, 7b, 7c.

Here, the resistance values of the resistors 7a, 7b, 7c are R _i , the resistance value of the resistor 6 is R _f , and the gradation reference voltage 12c.
The voltage applied from the (reference voltage line) to the resistor 7a is V
₀ (v), the voltage applied from the gradation reference voltage 12b to the resistor 7b is V ₁ (v), and the voltage applied from the gradation reference voltage 12a to the resistor 7c
Is a voltage applied to V ₂ (v), and the voltage applied from the reference voltage 11 (reference voltage line) to the + input of the operational amplifier 15 is 0.
If v, the output voltage obtained from the output terminal is the output voltage V _OUT = − (R _f / R _i ) · (V ₀ + V ₁ + V
₂ ) required.

Therefore, in the data side driving device having the unit output circuit having such a structure, the output voltage of eight stages is output by the switching operation to each of the analog switches 8a, 8b and 8c. The truth table used for this purpose is the input data (parallel data signals 16a, 16b, 1) that controls the analog switches 8a, 8b, 8c.
6c) is D1, D2 and D3, respectively, as shown in Table 1.

[0023]

[Table 1]

That is, the analog switches 8a, 8b,
Based on the input data D1, D2, D3 controlling 8c, any one of the output voltages V1 to V8 is obtained from the output terminal.

For example, the resistance value (R _i ) of the resistors 7a, 7b and 7c is 10 kΩ, and the resistance value (R _f ) of the resistor 6 is 20 k.
Ω, the voltage applied from the gradation reference voltage 12c to the resistor 7a is V ₀ (v) is 1v, the voltage applied from the gradation reference voltage 12b to the resistor 7b is V ₁ (v) is 2v, the gradation reference voltage 12a is the resistance The voltage applied to 7c is V ₂ (v) is 4v,
When the voltage applied from the reference voltage 11 to the + input of the operational amplifier 15 is 0v, the output voltage obtained from the output terminal is
It means that 8 steps of voltage levels can be selected by 2v from -14v to 0v. Further, with the resistance value (R _i ) of the resistors 7 a, 7 b, and 7 c set to 10 kΩ and the resistance value (R _f ) of the resistor 6 set to 20 kΩ, the reference voltage for gradation 1
The voltage applied from 2c to the resistor 7a is V ₀ (v) is 4v, and the voltage applied from the gradation reference voltage 12b to the resistor 7b is V
Obtained ₁ (v) 3 v, the voltage applied to the resistor 7c from the gradation reference voltage 12a V ₂ a (v) 1 v, the voltage applied from the reference voltage 11 to the positive input of the operational amplifier 15 from 5v Then, the output terminal The output voltage can be selected from 8v voltage levels of 2v from 5v to 19v.

Then, corresponding to these voltage levels,
In the active matrix (TFT) liquid crystal display panel shown in FIG. 6, the data signal line 46 and the scanning signal line 4
The voltage applied to both ends of the liquid crystal 50 is controlled for each display pixel at the intersection with 7. As a result, the degree of the alignment state of the liquid crystal 50 changes based on the applied voltage, so that the display state in each display pixel is displayed in 8 gradations.

As described above, in the data side driving device of the liquid crystal display panel provided with the unit output circuit of this example, the holding device including the 3-bit input shift register 4 and the latch circuit 5 including the D-type flip-flops 10 and 9 is provided. An analog switch 8a for selecting the weighted gradation reference voltage 12 based on the output unit 1 and the parallel data signals 16a, 16b, 16c output from the holding output unit 1.
Selector 2 including 8b and 8c, and this selector 2
Resistor 7a for adding and amplifying the reference voltage selected by
An output voltage of 8 stages can be obtained by the voltage addition amplification unit 3 composed of 7b, 7c, 6 and the operational amplifier 15.
Unlike the conventional data side driving device, it does not have a NAND circuit or an inverter. Therefore, the occupied area of the data side drive device corresponding to 8-gradation display can be small. Further, in order to increase the voltage to a high voltage system by the voltage addition amplification unit 3,
A low voltage system is sufficient for all the gradation reference electrodes 12. Therefore, it is not necessary to mount a level shifter and the like, and the region in which the withstand voltage is to be taken into consideration is extremely narrow, which is advantageous in saving space in the data side driving device. Further, even when the circuit configuration is changed to support 16 gradations, it is only necessary to change the unit output circuit shown in FIG. 1 to the circuit configuration shown in FIG. That is, the D-type flip-flops 10 and 9 are added to the 4-bit input shift register 25 corresponding to 4 bits and the holding output unit 24 including the latch circuit 26, and the analog switches 8a, 8b and 8c are added to the analog switch 8d. And a selector 27 that can select a voltage from four levels of gradation reference voltage 29 and a resistor 7
a, 7b, 7c, 7d, 6 and the voltage addition amplification unit 28 including the operational amplifier 15
16 levels of output voltage can be obtained. Therefore, even when the liquid crystal display panel has a high gradation, it is possible to minimize the increase in the number of elements constituting the unit output circuit of the data side driving device.

[Embodiment 2] FIG. 3 is a schematic configuration diagram of a unit output circuit in a data side driving device of a liquid crystal display panel according to Embodiment 2 of the present invention. Here, the configuration of the unit output circuit of the present example is substantially the same as the configuration of the unit output circuit according to the first embodiment, and therefore, corresponding parts will be denoted by the same reference numerals and description thereof will be omitted.

In the figure, in the unit output circuit of this example, in addition to the added voltage (reference voltage) from the selector 22 with respect to the-input of the operational amplifier 15 (voltage addition amplification section 21), the voltage output from the output terminal The added voltage for offset from the output voltage adjustment signal 23 can also be input via the resistor 7 for the purpose of adding an offset to the signal. Other configurations are the same as the unit output circuit according to the first embodiment, and the holding output unit 1 including the 3-bit input shift register 4 and the latch circuit 5 including the D-type flip-flops 10 and 9, and this holding output unit. Analog switches 8a, 8 for selecting the weighted gradation reference voltage 12 based on the parallel data signals 16a, 16b, 16c output from
selector 22 including b and 8c, and this selector 2
It is possible to obtain an 8-step output voltage by including the resistors 7a, 7b, 7c, 6 for adding and amplifying the gradation reference voltage selected by 2 and the voltage addition amplification section 21 having the operational amplifier 15. ing.

Therefore, an offset can be added to the output voltage from the output terminal only by adding the output voltage adjustment signal 21 and the resistor 7 to the unit output circuit of the first embodiment, and therefore, with a simple structure, An output signal level corresponding to another configuration of the liquid crystal display panel can be obtained. Further, similar to the unit output circuit of the first embodiment, the holding output unit 1 including the 3-bit input shift register 4 including the D-type flip-flops 10 and 9 and the latch circuit 5, and the analog switches 8a, 8b and 8c are provided. Equipped selector 2
2, and the voltage addition amplification unit 21 including the resistors 7a, 7b, 7c and the operational amplifier 15 can obtain an output voltage in eight stages, and as a data side driving device corresponding to 8-gradation display,
It occupies a small area. In addition, the voltage addition amplification unit 2
In order to increase the voltage to 1 in the high voltage system, it is sufficient for the gradation reference electrode 12 to be in the low voltage system. Therefore, it is not necessary to mount a level shifter and the like, and the region in which the withstand voltage is to be taken into consideration is extremely narrow, which is advantageous in saving space in the data side driving device. Further, even when the unit output circuit corresponding to the 8-gradation display is changed to the 16-gradation display, the holding output section 1 and the gradation reference voltage 12 correspond to 4 bits, and an analog switch and All you have to do is add a resistor.

[Embodiment 3] FIG. 4 is a schematic configuration diagram of a unit output circuit in a data side driving device of a liquid crystal display panel according to Embodiment 3 of the present invention. Here, among the configurations of the unit output circuit of the present example, the configurations of the holding output section and the selector section are the same as the configurations of the unit output circuit according to the first embodiment, and therefore, corresponding parts are denoted by the same reference numerals. I am doing it.

In the figure, the unit output circuit has a schematic structure in which the gradation display signal 13 fetched in synchronization with a clock pulse is converted into 3-bit parallel data signals 16a, 16b, and 1.
6c, a hold output section 1 that outputs in synchronization with the latch pulse, and a weighted gradation reference voltage 12 (reference voltage) based on the parallel data signals 16a, 16b, 16c output from the hold output section 1 Selector 3 to select
7 and. Further, in the unit output circuit in the data side drive device of the liquid crystal display panel of the present example, the gradation reference voltage 12 selected by the selector 37 is operated to generate the voltage signal corresponding to the gradation display signal 13. As an arithmetic unit for outputting, there is provided a differential amplifier unit 31 for subtracting and summing the sum of the voltages selected on the inverting input side from the sum of the voltages selected on the non-inverting input side. Here, as in the first embodiment, the holding output unit 1 takes in the gradation display signal 13 which is digitalized in synchronization with the clock pulse as the output data 14 and transfers the 3-bit input shift register 4.
And the output data 14 transferred from the 3-bit input shift register 4 in parallel with the latch pulse for adjusting the timing with the scanning side, the parallel data signals 16a, 16b,
16c and a latch circuit 5 for outputting as 16c, and these 3-bit input shift register 4 and latch circuit 5 are
Both are composed of D-type flip-flops 9 and 10. Further, the selector 37 has analog switches 8a, 8b, 8c corresponding to the parallel data signals 16a, 16b, 16c sent from the latch circuit 5, and the analog switches 8a, 8b, 8c are parallel data signals 16a. , 16b, 16c, one of the weighted gradation reference voltage 12 and the reference voltage 11 is selected.

The differential amplifier 31 includes resistors 7a, 7 connected in series to the analog switches 8a, 8b, 8c.
b, 7c, a resistor 36 connected to the reference voltage 11, and an operational amplifier 15 having a resistor 6 that defines the amplification degree of the voltage level generated at the output terminal. Of which, resistance 7
The a and 7b are connected to the inverting input side of the operational amplifier 15, and the resistor 7c is connected to the non-inverting input side of the operational amplifier 15. A resistor 7e for matching the number of differential inputs is also connected to the non-inverting input side of the operational amplifier 15, and the resistor 7e is connected to the reference voltage 11.

Here, the resistance values of the resistors 7a, 7b, 7c and 7e are R _i , the resistance values of the resistors 6 and 36 are R _f, and the voltage applied from the gradation reference voltage 12c to the resistor 7a is V.
₀ (v), the voltage applied from the gradation reference voltage 12b to the resistor 7b is V ₁ (v), and the voltage applied from the gradation reference voltage 12a to the resistor 7c
The voltage applied to V ₂ (v), the reference voltage 11 to the resistance 7
Assuming that the voltage applied to e and 36 is 0v, the output voltage obtained from the output terminal is the output voltage V _OUT = (R _f / R _i ) · {V ₂ − (V ₀ + V
₁ )}.

Therefore, in the data side driving device having the unit output circuit having such a configuration, the output voltage of eight stages is output by the switching operation of each analog switch 8a, 8b, 8c. The truth table used for that purpose is the input data (parallel data signals 16a, 16b, 1) that control the analog switches 8a, 8b, 8c.
6c) are D1, D2 and D3, respectively,
It is the same as the truth table of Table 1 used for the explanation. That is,
Based on the input data D1, D2, D3 for controlling the analog switches 8a, 8b, 8c, any one of the output voltages V1 to V8 is obtained from the output terminal.

For example, the resistance value (R _i ) of the resistors 7a, 7b, 7c and 7e is 10 kΩ, and the resistance value (R _i ) of the resistors 6 and 36 (R
_f ) is set to 10 kΩ and the reference voltage for gray scale 12 c
The voltage applied to a is 2.5 V for V ₀ (v), and the voltage applied to the resistor 7b from the gradation reference voltage 12b is V ₁ (v).
0 v, the voltage applied to the resistor 7 c from the gradation reference voltage 12 a is V ₂ (v) 4.0 v, the reference voltage 11 to the resistor 7 e,
Assuming that the voltage applied to 36 is 0v, the output voltage obtained from the output terminal can be selected from 8v voltage levels of 0.5v from 0.5v to 4.0v. Also,
The voltage applied from the gradation reference voltage 12c to the resistor 7a for the purpose of alternating current, with the resistance value (R _i ) of the resistors 7a, 7b and 7c being 10 kΩ and the resistance value (R _f ) of the resistors 6 and 36 being 10 kΩ. V ₀ (v) is 2.0 v, gradation reference voltage 12 b
From the voltage applied to the resistor 7b to V ₁ (v) is 1.0v, and the voltage applied from the gradation reference voltage 12c to the resistor 7c is V
₂ (v) 0.5v, the reference voltage 11 to the resistors 7e, 36
Assuming that the voltage applied to the output terminal is 0v, the output voltage obtained from the output terminal can be selected from eight voltage levels of 0.5v from -3.0v to 0.5v. Further, the output voltage can be set to a predetermined level by changing the resistance value of the resistor 6 of the differential amplification section 31 relatively and changing the resistance ratio thereof to change the amplification factor thereof. Corresponding to these voltage levels, in the active matrix (TFT) liquid crystal display panel shown in FIG. 6, both ends of the liquid crystal 50 are displayed for each display pixel at the intersection of the data signal line 46 and the scanning signal line 47. The voltage applied to is controlled. As a result, the degree of the alignment state of the liquid crystal 50 changes based on the applied voltage, so that the display state in each display pixel is displayed in 8 gradations.

As described above, in the data side driving device of the liquid crystal display panel including the unit output circuit of this example, the parallel data signals 16a, 16 output from the holding output section 1 are output.
a selector 37 including analog switches 8a, 8b, 8c for selecting the weighted gradation reference voltage 12 based on b and 16c, and a differential amplifier section 31 for differentially amplifying the reference voltage selected by the selector 37. An output voltage of 8 stages can be obtained by and. Therefore, the occupied area of the data side drive device corresponding to 8-gradation display can be small. In addition, since the differential amplifying unit 31 increases the voltage to a high voltage system, the gray scale reference electrode 12 may be a low voltage system. Therefore, it is not necessary to mount a level shifter and the like, and the region in which the withstand voltage is to be taken into consideration is extremely narrow, which is advantageous in saving space in the data side driving device. Further, even when the circuit configuration is changed to support 16 gradations, it is only necessary to change the unit output circuit shown in FIG. 4 to the circuit configuration shown in FIG. That is, similar to the unit output circuit shown in FIG. 2, the D-type flip-flops 9 and 10 are additionally provided to provide a 4-bit input shift register 25 and a latch circuit 26, which correspond to the parallel data signal 1
The holding output section 24 capable of outputting 6a, 16b, 16c, 16d, and the analog switch 8d added to the analog switches 8a, 8b, 8c are added to the parallel data signals 16a, 16
b, 16c, 16d, a selector 35 capable of selecting a voltage from four gradation reference voltages 39, and a resistor 7
16-level output voltage is obtained by adopting a differential amplifier 32 to which a resistor 7d connected to the gradation reference voltage 39 is added in addition to a, 7b, 7c, 6, 36 and the operational amplifier 15. You can Therefore, even when the liquid crystal display panel has a high gradation, it is possible to minimize the increase in the number of elements constituting the unit output circuit of the data side driving device. In addition, the selected gradation reference voltage 12
Since the differential amplifiers 31 and 32 are employed as the arithmetic units for performing the arithmetic operation on and outputting the voltage signal corresponding to the gradation display signal 13, the resistance ratio and the reference voltage are set to predetermined conditions. It is also possible to generate a negative high voltage.

In each of the first to third embodiments, the case where the unit output circuit is used as the data side driving device of the liquid crystal display panel has been described, but another flat type semiconductor device for driving multiple outputs is used. The display device may be used, and its use is not limited.

[0039]

As described above, in the unit output circuit of the multi-output driving semiconductor device and the data side driving device of the liquid crystal display panel according to the present invention, weighting is performed based on the parallel data output from the holding output section. It is characterized by having a selector for selecting the selected reference voltage and an operation unit such as a differential amplification unit or a voltage addition unit which performs an operation on the reference voltage selected by this selector and outputs it as a voltage signal. Since it has, it has the following effects.

Since the selected weighted reference voltage is increased in voltage in the arithmetic units such as the differential amplifier and the voltage adder, the circuit up to the selector can be configured with low-voltage space-saving circuit elements. It is possible to save space.

When the arithmetic unit is composed of a differential amplifier, a negative high voltage can be generated by setting a reference voltage and a resistance ratio corresponding to each resistance.

Since it is not necessary to convert the signal into a high voltage system by the level shifter, the number of elements that form the unit output circuit can be reduced.

In increasing the signal level in multiple stages,
Since the number of elements to be added is small, it is possible to easily realize high gradation display of a liquid crystal display panel, for example.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a unit output circuit in a data side driving device corresponding to 8-gradation display of a liquid crystal display panel according to a first embodiment of the present invention.

2 is a schematic configuration diagram in a case where a unit output circuit in the data side driving device of the liquid crystal display panel shown in FIG. 1 is modified to support 16 gradation display.

FIG. 3 is a schematic configuration diagram of a unit output circuit in a data side driving device corresponding to 8-gradation display of a liquid crystal display panel according to a second embodiment of the present invention.

FIG. 4 is a schematic configuration diagram of a unit output circuit in a data side driving device corresponding to 8-gradation display of a liquid crystal display panel according to a third embodiment of the present invention.

5 is a schematic configuration diagram in the case where the unit output circuit in the data side driving device of the liquid crystal display panel shown in FIG. 4 is modified to support 16 gradation display.

FIG. 6 is a schematic configuration diagram of a typical active matrix type liquid crystal display panel.

FIG. 7 is a schematic configuration diagram of a unit output circuit in a data side driving device corresponding to 8-gradation display of a conventional liquid crystal display panel.

FIG. 8A is an explanatory diagram showing a symbol of exclusive OR;
(B) is a circuit diagram of an exclusive OR circuit, and (c) is a circuit diagram of another exclusive OR circuit.

FIG. 9 is a schematic configuration diagram of a unit output circuit in a data side drive device corresponding to another eight-gradation display of another conventional liquid crystal display panel.

[Explanation of symbols]

1, 24 ... Holding output section 2, 22, 27, 35, 37 ... Selector 3, 21, 28 ... Voltage addition amplification section (arithmetic section) 4 ... 3-bit input shift register 5, 26 ... Latch circuit 6,7,7a, 7b, 7c, 7d, 7e, 36 ... Resistance 8a, 8b, 8c, 8d ... Analog switch 9,10 ... D-type flip-flop 11 ... Reference voltage 12, 12a, 12b, 12c, 29, 39 ... Gray scale reference voltage (reference voltage) 13 ... Gray scale display signal 15 ... Operational amplifier 16a, 16b, 16c, 16d ... Parallel data Signal 23 ... Output voltage adjustment signal 25 ... 4-bit input shift register 31, 32 ... Differential amplifier (arithmetic unit)

Claims (6)

[Claims] 1. A holding output section for outputting the fetched data signal as parallel data in synchronization with a latch signal, and each weighted reference voltage is selected based on the parallel data outputted from the holding output section. A multi-output drive characterized by having a plurality of unit output circuits including a selector and an operation unit that performs an operation on each reference voltage selected by the selector and outputs a voltage signal corresponding to the data signal. Semiconductor device. 2. The calculation unit according to claim 1, wherein among the selected reference voltages, a sum of reference voltages selected on the non-inverting input side and a sum of reference voltages selected on the inverting input side. The multi-output driving semiconductor device is a differential amplifying unit that amplifies the difference between 1 and 2 by a predetermined amplification degree and outputs the voltage signal. 3. The multi-output driving semiconductor device according to claim 1, wherein the arithmetic unit is a voltage adding unit that adds the selected reference voltages and outputs the voltage signal. 4. The voltage adding unit according to claim 3,
A multi-output driving semiconductor device comprising: a voltage addition amplification unit that adds the reference voltage and amplifies it with a predetermined amplification degree to output the voltage signal. 5. The output voltage adjusting means according to claim 3, further comprising: an output voltage adjusting unit for inputting an offset adjusting voltage for adding an offset to the voltage signal output from the voltage adding unit. A characteristic multi-output driving semiconductor device. 6. A data side driving device of a liquid crystal display panel, comprising a multi-output driving semiconductor device as defined in any one of claims 1 to 5, wherein the holding output section is
A shift register that takes in a gradation display signal as the data signal and transfers the parallel data signal in synchronization with a clock signal, and adjusts the timing of the parallel data signal transferred from the shift register with the scanning side. And a latch circuit which outputs the latch signal in synchronism with the latch signal to be driven, on the data side of the liquid crystal display panel.