JPH0526427B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase control device that controls the firing phase of a thyristor constituting a multiphase power converter that converts alternating current power into direct current power.

An example of a conventional device of this type is shown in FIG. In FIG. 1, 1 is a converter in which six thyristors U, X, V, Y, W, and Z are connected in a three-phase bridge to convert AC power into DC power and supply it to a load (not shown); 2 is a transformer connected between an AC power source and the converter 1 (not shown);
Reference numeral 3 denotes a synchronous circuit consisting of a transformer whose primary side is connected to an AC power supply (not shown), which outputs a phase voltage with a phase delay of 30 degrees with respect to the phase voltage of the transformer 2. 4 is a pulse generation circuit that obtains the gate signal of the thyristor, and includes integrators IN ₁ to IN ₆ that shape the input waveform, integrate it, and send out a triangular waveform output signal; It consists of comparators CP ₁ to _{CP 6} that compare the phase angle signal Vα and send out a pulse signal at the point where both coincide. The second diagram illustrates this operation for one phase.
This will be explained with figures. A synchronous circuit 3 receiving an AC power supply (not shown) sends a sinusoidal output voltage to a pulse generating circuit 4, as shown in FIG. 2a. In response to this, the integrators IN ₁ to IN ₆ of the pulse generation circuit 4 shape the input into a rectangular wave (Fig. 2 b), integrate this, and send out a triangular wave-shaped output voltage (Fig. 2 c). .
The comparators CP ₁ to _{CP 6} compare the outputs of the integrators IN ₁ to IN ₆ with the DC voltage phase angle signal Vα (Vα in Fig. 2), and send out a pulse signal when the two match (the second signal Vα).
Figure d). The pulse signals of these comparators CP ₁ to CP ₆ are the first
The firing pulse signal is supplied as a firing pulse signal to a gate circuit (not shown) that sends out gate signals for each of the thyristors U, X, V, Y, W, and Z shown in the figure.
They fire sequentially with a 60° phase difference, converting AC power to DC power and outputting it. This method, the so-called phase-by-phase control method, has the advantage that the basic circuit configuration is simple when the number of rectified phases is small. An integrator and a comparator corresponding to several minutes are required, which increases the number of parts and complicates the configuration, and also requires time and effort to adjust the CR time constants of the integrators. Furthermore, it is easily affected by three-phase imbalance or waveform distortion of the AC power supply, and cannot respond to changes in the power supply frequency.Changes in the power supply frequency cause fluctuations in the phase angle, which reduces reliability. .

To improve this, we created one phase reference pulse that synchronized the thyristor gate signal with one cycle of the power supply frequency, and generated phase pulses for each rectified phase at regular intervals based on this pulse. A so-called constant pulse interval control method has also been proposed. This will be explained with reference to FIG. In Fig. 3, 5 is a synchronous circuit that detects the zero point of the input frequency f synchronized with the AC power supply with a 30° phase delay (i.e., the point corresponding to the phase angle Vα = 0).
a pulse generator PU that sends out a pulse signal;
It consists of a frequency multiplier FM which sends out an oscillation frequency n·f which is multiplied by n times this signal. 6
is a pulse generation circuit that obtains a gate signal to be sent to the thyristor of the converter, and it generates a signal mf (n f × m /n), and the signals m and f of this frequency divider FD are counted and shifted every 2π/m from output terminals Q ₁ to Q _n corresponding to the number of rectification phases m.
A ring counter RC that sends out a rectangular wave signal with a width of 2π/m, and a signal n of the frequency multiplier FM mentioned above.
A so-called n-ary counter C that is reset by a signal from a pulse generator PU every time f is counted n times, and a digital-to-analog converter D/A that converts this signal into analog and sends it out.
, a comparator CP that sends out a signal obtained by comparing this signal with the phase angle signal Vα, and a differentiating circuit D that sends out a pulse signal at the rising edge of this comparison signal.The frequency is divided by the signal of the differentiating circuit D. At the same time, the ring counter R is reset so that the signal at the output end _Q1 is at the "H" level and the signals at _Q2 to _Qn are at the "L" level. I'm getting older.

The operation will be explained with reference to Fig. 4.
A pulse generator PU receiving an input frequency f (Fig. 4a) synchronized with the power frequency of an AC power supply (not shown)
detects the zero point and sends out a pulse signal (Fig. 4b). In response to this, the frequency multiplier FM outputs the pulse signal at an oscillation frequency n·f which is multiplied by n times (Fig. 4c). This is calculated by counter C.
Each time it counts, it is reset by the signal f from the pulse generator PU and outputs the count number to the digital-to-analog converter D/A. The digital-to-analog converter D/A converts the input signal into analog and sends it to the comparator CP. The comparator CP receiving this compares it with the phase angle signal Vα (FIG. 4 d) and sends it to the differentiating circuit D for a rectangular wave comparison signal (FIG. 4 e).
Differentiating circuit D uses a pulse signal as a reset signal at the rising edge of the input and sends it as a phase reference pulse to ring counter RC and frequency divider FD (Fig. 4g). On the other hand, the frequency divider FD divides the signal n·f of the frequency multiplier FM by m/n and sends m·f to the ring counter RC (Fig. 4h).
counts this at the falling edge of the input, and sequentially sends out a rectangular wave output signal with a width of 2π/m shifted every 2π/m from the output terminals Q ₁ to Q _n (Fig. 4 Q ₁ to Q _n ), when receiving the reset signal of the differential circuit D, only the output terminal _Q1 is set to "H" level, and the other terminals _Q2 to _Qn are set to "L".
It becomes a level signal, and is counted again at the fall of the next frequency divider FD signal, and output signals are sent out in sequence. In this way, the firing pulse signal for sending out the gate signal is obtained from the output signal of the ring counter RC. According to this method, the number of rectification phases is increased (e.g. 12 phases, 24 phases).
It has the advantage that it is easy to use and is not easily affected by three-phase unbalance of the AC power supply voltage and waveform distortion. However, it generates one phase reference pulse per cycle of the power supply frequency, and uses it as a reference at fixed intervals ( Since the pulse signal is generated at 2π/m), 1
It has a major drawback in that it cannot follow changes in the phase angle signal Vα within a cycle and cannot provide high-speed response. Furthermore, phased locked loop so-called PLL circuits are generally widely used in synchronous circuits, but in order to stabilize the oscillation of voltage controlled oscillators, the time constant of the loop filter is changed to several times the power supply frequency. It is set to several tens of times,
Due to this time constant, when controlling the phase using a generator or the like as a power source, there is a problem that the response is delayed because it cannot cope with sudden changes in the power supply frequency, and solving this problem would complicate the configuration. This also has the problem of being expensive.

The present invention has been made in view of the above-mentioned points, and its purpose is to have a simplified configuration and to be able to cope with sudden changes in power supply frequency.
It is also an object of the present invention to provide a device that can accurately perform high-speed, high-precision phase control.

An example in which the present invention is applied to a converter having 12 rectification phases will be described below with reference to FIGS. 5 to 7. Fifth
The figure shows an example of a converter in which the number of rectification phases is 12. In the figure, 7 indicates 12 thyristors U ₁ ,
This is a converter in which X ₁ ... Z ₂ are connected in a three-phase bridge. It is connected to an AC power source (not shown) via transformers 8a and 8b, and converts AC power into DC power by timely conduction and disconnection of the thyristor. The power is supplied to a load (not shown). FIG. 6 shows an embodiment for obtaining a gate signal to be sent to the gate of the thyristor of the converter 7. In the figure, reference numeral 9 denotes a pulse signal with an oscillation frequency obtained by multiplying the power frequency of an AC power supply (not shown) supplied to the converter 7 by a multiplier n (for example, 768) determined from the resolution of the phase control. This is a synchronous multiplier circuit designed to transmit signals. This is connected to the above-mentioned AC power supply (not shown) via a transformer (not shown),
Input a synchronous power source with a frequency that is synchronized with the power frequency of the AC power source and has a phase delay of 30 degrees,
a zero point detector ZPD that detects and outputs this input zero point (i.e., phase angle 0° of synchronous power supply frequency f);
A multivibrator MB sends out a one-shot pulse signal at the rising edge of this output, an oscillator OSC oscillates at a high frequency (e.g. 20MHz), and this oscillation frequency is counted and divided by 1/n (e.g. 1/768). , an n-ary frequency divider FD ₁ that is reset when the pulse signal of the multivibrator MB is received with a slight time delay (for example, 100 ns) via the delay circuit TD, and this frequency divider FD ₁ . Multivibrator MB pulse signal delay circuit
The up counter UC is reset at the rising edge of its input as a reset signal via TD, and counts up until the next reset signal rises, and the count number immediately before this up counter UC is reset is determined by the pulse of the multivibrator MB. A latch counter LC consists of a latch circuit L that uses a signal as a latch command to latch and output at the rising edge of the input, and the value of the output data of this latch counter LC is sequentially counted down by the output pulse of the oscillator OSC. It is formed by a down counter DC which sends out an output when the count number reaches 0 and inputs this output as a preset command signal. If the power frequency of the AC power source (hereinafter simply referred to as power frequency) is fHz, and the output frequency of the oscillator OSC is f ₀ Hz, then the period of the output pulse of the multivibrator MB is 1/f seconds, and the period of the output pulse of the oscillator OSC is 1/f seconds. The period is 1/f ₀ seconds, and since the frequency is divided by 1/n, the period of the output pulse of the frequency divider FD ₁ is 1/f ₀ × n/1=n/f ₀ seconds. Therefore, the count number immediately before the up counter UC of the latch counter LC is reset is 1/f×f ₀ /n=f ₀ /f·n, and this data is latched and output from the latch counter LC. , the down counter DC is preset to the value of f ₀ /f・n, and decreases by 1 every 1/f ₀ seconds due to the countdown, so that f ₀ /f・n×1/f ₀ = 1/f・n After a second, the count number becomes 0, the output is sent out, the count value is again preset to f ₀ /f・n, the countdown is repeated, and the count number becomes 0 after 1/f・n seconds. The count number is sent out as an output signal.
That is, it is preset to the down counter DC.
The value of f ₀ /f・n is output from the latched counter LC that is latched every cycle in synchronization with the power supply frequency, so if the power supply frequency suddenly changes, the power supply frequency will change in the next cycle. The value of f ₀ /f·n corresponding to the sudden change in is preset in the down counter DC. The output signal of the down counter DC is then sent out as the output signal of the synchronous multiplier circuit 9, and its frequency is n·fHz, which is n times the power supply frequency fHz. 10 is synchronized with the above power supply frequency and sequentially sends out output signals from the same number of output terminals as the number of rectification phases with a constant pulse width (2π/3=120° in phase angle) and a phase difference determined by the number of rectification phases. This is a timing generation circuit. This is formed by a frequency divider FD ₂ and a shift register SR ₁ , and the frequency divider FD ₂ connects the clock input terminal CK to the output terminal of the down counter DC of the synchronous multiplier circuit 9, and connects the above multivibrator to the reset input terminal R. Connect the output end of MB to down counter DC
Count the output pulses (n・fHz), divide the frequency by m/n (where m: integer phase number, m=12 in this example), and output (n・f×m/n=m・fHz, in this example (m・f = 12fHz), and is reset by the output pulse of the multivibrator MB. In addition, the shift register SR ₁ has the same number of output terminals Q ₁ , Q ₂ as the number of rectification phases...
Q ₁₂ , and the above frequency divider FD ₂ is connected to the clock input terminal CK.
Connect _the output terminal of the multivibrator MB to _the preset input terminal PE, and connect the output terminal of the multivibrator MB to the preset input terminal _PE . In order to send out an output signal, predetermined data is set to a preset data input (not shown) (in this example, _the
Q ₁₀ , Q ₁₁ , and Q ₁₂ are set by preset so that the output signal becomes "H" level), and the output terminals Q ₄ and Q ₈ are connected to the data input terminal D by a NOR circuit.
Multivibrate by connecting via NOR ₁
It is preset at the rising edge of the MB output pulse to invert the output signals of the output terminals Q ₁ , Q ₁₀ , Q ₁₁ , and Q ₁₂ to “H” level, and thereafter every time one output pulse of the frequency divider FD ₂ is input. (i.e., the output pulse of the frequency divider FD ₂ is input every 1/m・f seconds, so the phase angle is shifted every 2π/m, in this example, every 2π/12 = 30°). The output signals from the output terminals Q ₂ to _{Q 12} are sent out sequentially, and the pulse width of the "H" level output signal is determined by the output signals from the output terminals Q ₄ and Q ₈ to the NOR circuit NOR _1. Since the data is input to the data input terminal D via (2π/3=120° in this example)
It is becoming more and more like this. 11 is a phase pulse generation circuit for sending out a phase pulse signal that determines the firing phase of the thyristor of the converter 7, which is connected to the synchronous multiplier circuit 9 and the timing generation circuit 10;
(In this example, the number of rectification phases m = 12, so 12/3 = 4) Pulse generators 11a, 11b, 1
It is formed from 1c and 11d. The pulse generator 11a includes a timing generation circuit 10.
A differentiator circuit D ₁ is connected to the output terminal Q ₁ of the shift register SR ₁ and generates a pulse signal at the rising edge of the input.
The preset input terminal PE is connected to the output terminal of this, and the clock input terminal CK is connected to the output terminal of the down counter DC of the synchronous multiplier circuit 9 _.
The down counter _C1 is preset at the rising edge of the output pulse of the down counter, counts down the output pulse of the down counter DC, outputs the counted number in a binary code, and is automatically preset when the counted number exceeds 0. , the output signal of this down counter _C1 is inputted to input terminal A, and the phase angle signal Vα, in which the control phase angle is binary-coded via an analog-to-digital converter (not shown), is inputted to input terminal B, and these two inputs A and B
A digital comparator CP ₁ is designed to send out an "H" level output signal from the output terminal A < B during the period when A < B, and the input terminal is connected to the output terminal A < B of this digital comparator CP ₁ . Connect and
Differentiator circuit that generates a pulse signal at the rising edge of the input
_D5 , and the pulse signal of this differentiating circuit _D5 is sent out as a phase pulse signal of the pulse generator 11a. Also, pulse generator 1
1b to 11d are also formed similarly to the pulse generator 11a, and the differentiating circuits _D2 to _D4 provided at the input terminals of the pulse generators 11b to 11d are connected to the shift register _SR1.
are connected to the output terminals Q ₂ to Q ₄ of the differential circuits D _{2 to Q 4 respectively, and are preset at the rising edge of the output pulses of the differentiating circuits D 2} to _{D 4} to count down the output pulses of the down counter DC, and send out the counted number in binary code. The outputs of down counters _C2 to _C4 , which are automatically preset when the count exceeds 0, are compared with the phase angle signal Vα by digital comparators _CP2 to _CP4 , respectively, and the output signals are output from output terminals A<B. to the differentiating circuits D ₆ to _{D 8} , respectively.
The differentiating circuits _D6 to _D8 generate pulse signals at the rising edge of the input, and send the pulse signals to the pulse generator 11b.
~11d phase pulse signals are sent out. Therefore, in the pulse generators 11a to 11d of this phase pulse generation circuit 11, the down counters _C1 to _C4 output k/m·f×n·f/1=k·n at the rising edge of the input at the preset input terminal PE. /m (in this example, k = 4, therefore n/3, for example, if n is 768, 256) is preset to a count value of k/m·f seconds (in this example, 1/m).
After 3 f seconds), the count becomes 0 and is automatically preset, so in 1/f seconds (that is, during one cycle of the power supply frequency fHz), 1/f x m f/k = m/ It is preset k times (in this example, 3 times including automatic preset) and performs a countdown operation, and in response to this, the output signals of the digital comparators CP ₁ to _{CP 4} that are compared with the phase angle signal Vα are also m/k. The differentiator circuit
_D5 to _D8 pulse signals are also generated in m/k pieces (three in this example) in 1/f seconds, and the pulse signals from the pulse generators 11a to 1
1d each sends out m/k (3 in this example) phase pulse signals for 1/f seconds.

Note that the down counters C ₁ to _{C 4} can be preset by shift registers instead of automatic presets.
When using the output signal of SR ₁ , the differential circuit D ₁
~ D ₄ input terminal, D ₁ output terminal Q ₁ , Q ₅ , Q ₉ , D ₂
is Q ₂ , Q ₆ , Q ₁₀ , D ₃ is Q ₃ , Q ₇ , Q ₁₁ , D ₄ is
Just connect them to Q ₄ , Q ₈ , and Q ₁₂ respectively.

Reference numeral 12 denotes a distribution circuit which distributes and sends out an ignition pulse signal to a gate circuit (not shown) based on the phase pulse signal of the phase pulse generation circuit 11 and the output signal of the timing generation circuit 10. This is an AND circuit with the same number of rectification phases AND ₁ ~
AND ₁₂ is provided, and one of the input terminals of the AND circuits AND ₁ to AND ₃ is connected to the output terminal of the differential circuit D ₅ of the pulse generator 11a, and in the same manner, AND ₄ to AND ₆ are connected to the output terminal of the differential circuit D 5 of the pulse generator 11b. ₆ , AND ₇ to AND ₉ are connected to D ₇ of the pulse generator 11c, AND ₁₀ to AND ₁₂ are connected to D ₈ of the pulse generator 11 d, and the other input terminal of the AND circuit AND ₁ is connected to the shift register described above. Similarly, connect AND _{2 to} Q ₅ at the output terminal of SR ₁ , Q 1.
, AND ₃ to Q ₉ , AND ₄ to Q ₂ , AND ₅ to Q ₆
, AND ₆ to Q ₁₀ , AND ₇ to Q ₇ , AND ₈ to Q ₁₁
, AND ₉ to Q ₃ , AND ₁₀ to Q ₈ , AND ₁₁ to
Q ₁₂ and AND ₁₂ are connected to Q ₄ , respectively, and ignition pulse signals for the thyristors of the converter 7 are sent out from the output terminals of the AND circuits AND ₁ to AND ₁₂ according to the input signals. .

Next, its operation will be explained with reference to FIG. The synchronous multiplier circuit 9 receives an input synchronized with the power frequency fHz of an AC power supply (not shown) with a 30° phase delay (the input of ZPD in FIG. 7), and operates a zero point detector ZPD that detects the zero point of the input frequency fHz. At the rising edge of the output, the multivibrator MB sends out a pulse signal (output of MB in Figure 7). The period of this pulse signal is 1/
It becomes f seconds. On the other hand, the oscillator OSC that oscillates high frequency
Frequency divider receiving output pulse with oscillation frequency f ₀ Hz
Since FD ₁ divides the input pulse by 1/n, the period of the output pulse is 1/f ₀ ·n/1=n/f ₀ seconds. Up counter that counts up this input pulse
The count immediately before the UC is reset is 1/f・f ₀ /n=f ₀ /f・n, which is latched by the latch circuit L and sent from the latch counter LC to the down counter DC as preset data. Output. The down counter DC counts down the output pulse (f ₀ Hz) of the oscillator OSC until the count number is 0.
When it reaches , an output is generated and the count value of f ₀ /f・n is preset by the output, and the count value decreases by 1 every 1/f ₀ seconds due to the countdown, and f ₀ /f・n・After 1/f ₀ =1/f·n seconds, it becomes 0, and the operation of being preset to the count value of f ₀ /f·n again is repeated. At this time, if the power supply frequency suddenly changes, the value of f ₀ /f·n corresponding to this sudden change is preset in the down counter DC in the next cycle of the power supply frequency. And this down counter
The output pulse of DC becomes the output pulse of the synchronous multiplier circuit 9, and its output frequency becomes n·fHz, which is n times the power supply frequency fHz (output of DC in FIG. 7). That is,
An output pulse multiplied by n times in synchronization with the power supply frequency fHz can be obtained as a reference signal. The frequency divider FD ₂ of the timing generation circuit 10 that receives this input pulse (n·fHz) divides it by m/n (m: number of rectification phases, in this example, 12/n) and outputs the divided signal. The output pulse is (n・f×m/n=m・fHz, 12fHz in this example), and m pulses are generated per 1/f seconds (12fHz in this example).
(7th) pulse signals are generated.
Figure FD ₂ output). Shift register based on this
SR ₁ is preset by the output pulse of the multivibrator MB (every 1/f seconds), and this preset causes the output signals of the output terminals Q ₁ , Q ₁₀ , Q ₁₁ , and Q ₁₂ to become “H” level. . Next, the output signal of the output terminal Q ₂ is also shifted to “H” by the output pulse of the frequency divider FD ₂ inputted after 1/m・f (1/12・f) seconds.
(At this time, since _Q9 is at the "L" level, the output signal of the output terminal _Q10 , which has become the "H" level, is also shifted and inverted to the "L" level), and from then on, the clock input terminal Every time one output pulse of the frequency divider FD ₂ is input to CK, it is shifted and the output signals of the output terminals Q ₁₁ and Q ₁₂ are sequentially inverted to "L" level, and the output terminals Q ₃ , Q ₄ . . . Q ₁₂ output signals are set to "H" level one after another (output of SR ₁ in Figure 7). The "H" level output signals of these output terminals _Q1 to _Q12 change from "H" to "L" after the input signal of the data input terminal D changes from "H" to "L" after 3/m·f (1/4·f in this example) seconds. Since the output signal at the output end _Q1 is inverted from "H" to "L" level k/m·f seconds after being preset, and thereafter 1/m·f (1 /12·f) The output signals of the output terminals Q ₂ , Q ₃ , . . . Q ₁₂ are sequentially inverted from “H” to “L” level every second.
That is, the "H" level output signals of the output terminals Q ₁ to _{Q 12} have a phase difference of 2π/m (in this example, π/6) with the pulse width being 2π/3 as the phase angle. It becomes a signal. This output signal is the multivibrator above
It is preset and repeated by the output pulse of the MB, that is, every 1/f seconds.

On the other hand, the down counters C ₁ , C ₂ , C ₃ , and C ₄ of the pulse generators 11 a, 11 b, 11 c, and 11 d of the phase pulse generating circuit 11 count down the output pulses (n·fHz) of the down counter DC, and , k/m・f _× m・f/ ₁ =k・_n / _m (this example Then, the input pulse (n fHz) is preset to a count value of n/3) and counted down one by one.
This count is carried out three times in 1/f seconds (i.e., one cycle of the power supply frequency f), and this count is expressed in binary code by digital comparators CP ₁ , CP ₂ , CP ₃ , CP ₄
are sent to the input terminal A of each. The digital comparators CP ₁ , _{CP 2} , _{CP 3} , CP ₄ receiving this signal compare it with the binary coded phase angle signal Vα inputted to the input terminal B (see Fig. _{7 )} .
input), the period during which both inputs A and B become A<B,
An "H" level output signal is sent from the output terminal A<B (outputs of CP ₁ , CP ₂ , CP ₃ and CP ₄ in FIG. 7). Differentiating circuits D ₅ , D ₆ , D ₇ , and D ₈ that receive this generate pulse signals at the rising edge of the input signal, and send these as phase pulse signals to pulse generators 11a to 11d, respectively (Fig. 7D). ₅ , _D6 , _D7 , _D8 output).
That is, the pulse generator 1 of the phase pulse generation circuit 11
1a to 11d are digital comparators CP ₁ to _{CP 4}
Three phase pulse signals a, b, and c are sent out for 1/f seconds from the output end A<B of the differential circuit D ₅ to D ₈ , respectively.

Shift register of the above timing generation circuit 10
The distribution circuit 12 receives the output signal of SR ₁ and the phase pulse signals of the pulse generators 11a to 11d of the phase pulse generation circuit 11, and divides the pulse generators 11a to 11
AND circuit by the phase pulse signal a of d
The output signals of AND ₁ , AND ₄ , AND ₉ , and AND ₁₂ are sequentially inverted to "H" level, and the pulse generator 11a
The AND circuit is formed by the phase pulse signal b of ~11d.
The output signals of AND ₂ , AND ₅ , AND ₇ and AND ₁₀ are sequentially inverted to "H" level, and the pulse generator 1
The output signals of AND circuits AND ₃ , AND ₆ , AND ₈ , AND ₁₁ are sequentially inverted to "H" level by the phase pulse signals c of 1a to 11d, and these "H"
The level output signals are sent as ignition pulse signals to gate circuits (not shown), and the gate signals of the gate circuits cause the 12 thyristors of the converter 7 to be made conductive or disconnected as appropriate. In other words, by generating three phase pulse signals in one cycle of the power supply frequency using one set of pulse generators, three phases of the integer phase flow can be shared, and four sets of pulse generators are used. As a result, an ignition pulse signal for 12 rectified phases is obtained.

Then, the phase angle signal Vα is 1 of the power supply frequency.
Even if it changes within the cycle, the pulse generator 1
1a to 11b are digital comparators CP ₁ to _{CP 4}
Since three phases are compared in one cycle of the power supply frequency, a phase pulse signal of the corresponding phase is instantaneously generated via differentiating circuits D ₅ to D ₈ to obtain the phase angle signal Vα.
In response to the change in , an ignition pulse signal is sent to a gate circuit (not shown) via the distribution circuit 12 . In other words, like the constant pulse interval method, 1
Phase control with high-speed response is possible without causing cycle time delays.

FIG. 8 shows an embodiment in which the present invention is applied to a case where the number of rectification phases is six. In the same figure,
13 is a timing generation circuit formed in the same manner as described above, and the frequency divider FD ₃ divides the output pulse of the down counter DC of the synchronous multiplication circuit 9 by m/n, that is, 6/n, and outputs the divided signal. The input shift register SR ₂ has an output terminal Q ₁ corresponding to the 6 rectification phases.
~ Q ₆ are provided, and in order to send out an “H” level output signal with a constant pulse width (2π/3 in phase angle) from each output terminal Q ₁ to Q ₆ , the output terminals Q ₂ and Q _Four
is input to the data input terminal D via the NOR circuit NOR ₂ , and the preset data input (not shown) is set by the output pulse of the multivibrator MB input to the preset _input terminal _PE . The output signal is set to "H" level, and the shift register is set by the output pulse of the multivibrator MB.
SR ₂ is preset to make the output signals of output terminals Q ₁ and Q ₆ "H" level, and every time one output pulse (m・f=6fHz) of frequency divider FD ₃ is input, that is, 1/m・Shift every f seconds (every π/3 = 60 degrees for each phase) to make the output signals of output terminals Q ₂ to Q ₆ “H”
The pulse width of the "H" level output signal is set to the phase angle as described above.
2π/3=120°. Reference numeral 14 denotes a phase pulse generation circuit consisting of two sets of pulse generators 14a and 14b formed in the same manner as described above. The pulse generator 14a is connected to the output end _Q1 of the upper shift register _SR2 and generates a pulse signal at the rising edge of the input, _and is preset and synchronized at the rising edge of the input pulse signal. a down counter _C5 which counts down the output pulses of the down counter DC of the multiplier circuit 9 and sends out the counted number in a binary code, and which automatically presets and repeats the countdown when the counted number exceeds 0; Input the output of this to input terminal A and the phase angle signal Vα to input terminal B, respectively.
A digital comparator _CP5 outputs an "H" level output signal from the output terminal A<B during a period when both inputs A and B are in the relationship A<B, and a pulse signal is generated at the rising edge of this output signal. Differential circuit that occurs
D ₁₁ , and as described above, three phase pulse signals a, b, and c are sent out from the output terminal of the differentiating circuit D ₁₁ , which share the three rectified phases in one cycle of the power supply frequency. I'm looking forward to it. Also, pulse generator 1
4b is a differentiating circuit connected to the output terminal _Q2 of the shift register _SR2 , similar to the pulse generator 14a above.
D ₁₀ , down counter C ₆ , digital comparator CP ₆ , and differentiation circuit D ₁₂ .
Phase pulse signals a, b, and c, which share the three rectified phases, are sent from the output end of _D12 . 15 is a distribution circuit that sends an ignition pulse signal to a gate circuit (not shown);
AND circuits AND ₁₃ to AND ₁₈ are provided, and _the phase pulse signal of the pulse generator 14a is inputted to one of the input terminals of the AND circuits AND 13 to AND ₁₅ , and the phase pulse signal of the pulse generator 14a is inputted to one of the input terminals of the AND circuits AND ₁₆ to AND ₁₈ . The phase pulse signal of the pulse generator 14b is input, and the output of the output terminal Q1 of the shift register SR 2 is inputted to the other input terminal of the AND circuit AND ₁₃ , and the output terminal of the output terminal _Q1 of the shift register SR ₂ is inputted to the other input terminal of the AND circuit AND ₁₃ .
output of Q ₃ to AND ₁₅ , output of Q ₅ to AND ₁₆
Q ₄ output, AND ₁₇ with Q ₆ output, AND ₁₈ with Q ₂
In the same way as described above, the firing pulse signal for the thyristor of the converter with 6 rectification phases can be obtained from the output terminals of the AND circuits AND ₁₃ to AND ₁₈ sent by these two input signals. can.

That is, the timing generation circuit 13 uses the frequency divider FD ₃
The output pulse of the down counter DC (n・f
Hz) divided by m/n (6/n) and sends the output pulse (n・f×m/n=m・fHz) to the clock input terminal CK of shift register SR ₂ .
SR ₂ is preset by the output pulse of multivibrator MB, the output signals of output terminals Q ₁ and Q ₆ become "H" level, and the input signal of data input terminal D becomes "H" level after 1/m·f seconds. Since the output signal of the output terminal _Q1 is inverted from "H" to "L" level k/m·f (1/3·f in this example) seconds after being preset, , hereafter 1/
The output signals of the output terminals Q ₂ to _{Q 6} are inverted from "H" to "L" level every m·f (1/6·f) seconds. That is,
The H" level signal at the output terminals Q ₁ to _{Q 6} has a pulse width of 2π/m x 2 = 2π/3 = 12 with the phase angle as described above.
0°, the output signals are sent out with a phase difference of 60° from each other, and are preset and repeated every 1/f seconds.

Then, in the down counter _C5 of the pulse generator 14a of the phase pulse generation circuit 14, the differentiating circuit _D9 inverts the output signal of the output terminal _Q1 from "L" to "H" level by presetting the shift register _SR2 . This occurs in the pulse signal at the rising edge, so
By the rise of this pulse signal, the count value is preset to k/m・f×m・f/1=k・n/m (k=2, therefore n/3 in this example), and the input pulse (n・fHz) is counted down one by one, k/
When the count exceeds 0 after m·f seconds, it is automatically preset and the countdown operation is repeated again, and this operation is repeated three times for 1/f seconds (in one cycle of the power supply frequency) as described above. In addition, the down counter _C6 of the pulse generator 14b also changes from _C5 to 1/
It is preset after m·f seconds, and when the count exceeds 0 due to the countdown, it is automatically preset, and the countdown operation as described above is performed three times in 1/f seconds. The counts of the down counters C ₅ and C ₆ are converted into binary codes and sent to the input terminals A of digital comparators CP ₅ and CP ₆ , respectively, and the digital comparators CP ₅ and CP ₆ are converted into binary codes and input to the input terminals B of the digital comparators CP 5 and CP 6. phase angle signal
Compared with Vα (inputs of CP ₅ and CP ₆ in Figure 9), when both inputs A and B have a relationship of A<B, the output terminal A<
Since the output signal from B is inverted to "H" level, the differentiating circuits D ₁₁ and D ₁₂ generate pulse signals at the rising edge of their inputs, which are sent to the pulse generators 14a and 14a.
14b as a phase pulse signal. Therefore, the pulse generators 14a and 14b respectively send out three phase pulse signals a, b, and c during one cycle of the power supply frequency.

The phase pulse signals a, b, c of the pulse generators 14a, 14b are converted into rectified phases (thyristor ) U, V, W, and the pulse generator 14
Phase pulse signals a, b, c of b are rectified phases Z, X,
By assigning each to Y (Fig. 9 U~
Y), three phase pulse signals generated by one set of pulse generators share three rectified phases.

At this time, when the phase angle signal Vα changes within one cycle of the power supply frequency (Vα' → Vα), a phase pulse signal is sent out in response to this instantaneously (a' →a, b′→b, c′→
c) High-speed phase control becomes possible.

In the example, the number of rectification phases is 12 and 6.
Although we have explained phase control for phase converters, it is of course applicable to phase control for converters with a rectification phase number m of 24 or more if the pulse generator is set to have the relationship k = m/3. It is.

According to the present invention, the phase control range is 0 to 120 degrees, and a set of pulse generators generates a phase pulse signal that divides the entire period of one cycle of the power supply frequency into three rectified phases. Because there is
Even if the phase angle signal changes within one cycle, an instantaneous response can be made, and high-speed response phase control can be performed. Moreover, if you apply, for example, an 8-bit down counter and digital comparator that form the pulse generator, 120°/
256 = 0.47°, so the conventional phase control range is 360°
The resolution can be further improved compared to the case (360°/256=1.41°), and phase control can be performed with high accuracy. Also, one set of pulse generators can generate at least 3 pulses per cycle of the power supply frequency.
Since it is designed to generate three phase pulse signals and allocate them to the three rectified phases using the output signal of the timing generation circuit, one set of pulse generators can share the three phases. When the number of rectification phases is 12, only 4 sets of pulse generators are required compared to the 12 sets required in the conventional phase control method for each phase, and similarly, when the number of rectification phases is 6, 6 sets are required. However, it can be formed in two sets, making it easy to use multiple phases, and simplifying the circuit configuration.
Moreover, since the synchronous multiplier circuit is formed by frequency conversion, it is not necessary to form it with a so-called PLL circuit, and it is possible to respond immediately to sudden changes in the power supply frequency. This is a great advantage over those that use a generator or the like as a power source for phase control. Furthermore, the pulse generator can be formed without providing a time constant circuit such as an integrator to generate the phase pulse signal, eliminating the need for adjustment and allowing phase control to be performed without adjustment. , it has remarkable features such as being easily applicable to those in which phase angle control is performed by a microcomputer.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional example, Fig. 2 is a time chart explaining the operation of Fig. 1, Fig. 3 is a block diagram showing another conventional example, and Fig. 4 shows the operation of Fig. 3. The time chart diagram to explain, Figure 5 is 12
6 is a block diagram illustrating an example of a phase converter, FIG. 6 is a block diagram illustrating an embodiment in which the present invention is applied to a 12-phase converter, FIG. 7 is a time chart explaining the operation of FIG. 6, and FIG. The figure is a block diagram showing an embodiment in which the present invention is applied to a six-phase converter, and FIG. 9 is a time chart explaining the operation of FIG. 8. 9: Synchronous multiplier circuit, 10, 13: Timing generation circuit, 11, 14: Phase pulse generation circuit, 1
2, 15: Distribution circuit, 11a to 11d, 14a,
14b: Pulse generator, _C1 to _C6 : Down counter, _CP1 to _CP6 : Digital comparator, _D1 to
D ₁₂ : Differential circuit.

Claims (1)

[Claims] 1. In a phase control device that controls the firing phase of a thyristor constituting a multi-phase power converter that is connected to an AC power source and converts AC power into DC power, the power frequency is adjusted in synchronization with the power frequency of the AC power source. a synchronous multiplier circuit that outputs a pulse signal with an oscillation frequency that is multiplied by a multiplier n determined from the phase control separability for each cycle; /n
An output signal having a constant pulse width whose frequency is divided by (m: number of rectification phases) and which is sequentially shifted for each divided pulse with a phase difference determined by the number of rectification phases. A timing generation circuit that generates and sends out the same number of pulses as the number of rectification phases, a counter that is preset at the edge of the output signal of this circuit, counts the output pulses of the synchronous multiplier circuit, and outputs a count, and its output signal. and a phase angle signal, and a digital comparator that sends out an output signal, and a differentiating circuit that generates a pulse signal at the edge of the output signal of this comparator, and converts the pulse signal of the differentiating circuit into a phase pulse signal. A phase pulse generation circuit is provided with a plurality of pulse generators configured to send out signals as a signal, and each pulse generator of this phase pulse generation circuit is connected to the timing generation circuit, and the output signal of the timing generation circuit is connected to the phase pulse generation circuit. a distribution circuit that distributes the phase pulse signal to the corresponding phase and sends out an ignition pulse signal; A phase control device characterized in that the phase control device generates the signal within one cycle of the phase control device.