JPH05259749A - Transistor circuit - Google Patents

Abstract

PURPOSE:To appropriately compensate a temperature of an operating current of a silicon power TR by forming a temperature detection Tr on a same silicon chip as the silicon power TR and detecting a base-emitter voltage. CONSTITUTION:When a collector current of a silicon power TR 2 is increased, the temperature of a power TR chip 1 rises. A base-emitter voltage of a temperature detection TR 3 is decreased due to the rise in the chip temperature and a base-emitter voltage of a PNP type TR 4 is also decreased. A collector current of the TR 4 is decreased through the decrease in the base-emitter voltage of the TR 4 and a bias voltage of the TR 2 is decreased. A collector current of the TR 2 is going to be increased due to a temperature rise, but since a bias voltage is decreased, the collector current is kept constant. The temperature is compensated in a very small time and accurately since the TRs 2, 3 are formed on a same silicon chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor circuit for detecting the temperature of a silicon power transistor chip composed of a base region and an emitter region formed by a double diffusion process in a short time and keeping its operating current constant. ..

[0002]

2. Description of the Related Art In recent years, various improvements have been made to bias circuits of transistor circuits. An example of a transistor circuit configured by the above-described conventional bias circuit will be described below with reference to the drawings.

FIG. 4 shows an SEP having a conventional bias circuit.
It is a circuit diagram of a P circuit. In FIG. 4, 61
Is an NPN type silicon power transistor consisting of a base region and an emitter region formed by a double diffusion process, 6
2 is a PNP type silicon power transistor composed of a base region and an emitter region formed by a double diffusion process,
63 is a temperature detection transistor, 64 and 65 are constant current circuits, 66 is an input terminal, 67 is an output terminal, 68 is a multiplier circuit, and 69 is a resistor whose resistance value is R1.
Reference numeral 70 denotes a resistor whose resistance value is R2. The NPN type silicon power transistor 61 and the PNP type silicon power transistor 62 are separate bodies, and the temperature detection transistor 63, the constant current circuits 64 and 65, the multiplier circuit 68, and the resistors 69 and 70 are the NPN type silicon power transistor 61, It is mounted separately from the PNP silicon power transistor 62. Further, the temperature detection transistor 63 is thermally coupled to the power transistors 61 and 62.

The structure of the SEPP circuit configured as described above will be described below. By the multiplier circuit 68 of the temperature detection transistor 63, the collector-emitter voltage Vce3 of this transistor is fixed to a voltage of approximately Vbe3. (R1 + R2) / R2, where Vbe3 is the base-emitter voltage of this transistor. Vce3 is a power transistor 61,
Since it is the bias voltage of 62, the collector current corresponding to this Vce3 flows into the collectors of the power transistors 61 and 62. It is assumed that the SEPP circuit is in an equilibrium state at a certain temperature and the collector currents of the power transistors 61 and 62 have a certain value. Here, the power transistors 61 and 62 are input for some reason such as an input signal being input.
If the collector current of 1 increases, the increase of collector current leads to an increase of collector loss, and as a result, the chip temperature of the power transistors 61 and 62 rises.

As is generally known, the base-emitter voltage Vbe of a silicon transistor has a temperature characteristic of about -2 mV with respect to temperature, so that the same collector current flows as the chip temperature rises. Vbe goes down. Here, if Vbe3 is constant, the collector current further increases by the amount that Vbe of the power transistors 61 and 62 decreases, and the chip temperature of the power transistors 61 and 62 increases due to this increase.
Due to this circulation, the collector currents of the power transistors 61 and 62 increase more and more, and eventually the power transistors 61 and 62 are destroyed. However, since the temperature detection transistor 63 is thermally coupled to the power transistors 61 and 62, the increase in the chip temperature of the power transistors 61 and 62 is transmitted to the temperature detection transistor 63 and Vbe3 of the temperature detection transistor 63 also decreases. The collector currents of the power transistors 61 and 62 are kept constant.

[0006]

However, in the SEPP circuit provided with the conventional bias circuit as described above, the heat generated in the power transistor causes the temperature detection transistor 6 to operate.
Since there is a delay time before it is transmitted to No. 3, the collector current of the power transistors 61 and 62 temporarily increases during that time, and from the power transistor chip to the temperature detection transistor 63, Since there is a certain amount of thermal resistance, all of the increase in the chip temperature of the power transistors 61 and 62 is not transmitted to the temperature detection transistor 63, so that there is a problem that complete temperature compensation cannot be performed.

FIG. 5 is a sectional view of a silicon transistor having a base region and an emitter region formed by a double diffusion process. In FIG. 5, 71 is an emitter region, 72 is a base region, 73 is a collector high specific resistance region, 74 is a collector high impurity concentration region, and 75 is a collector back surface portion. As shown in FIG. 5, in a silicon power transistor including a base region and an emitter region formed by a double diffusion process, since there is no diffusion step for electrically completely separating individual devices, the collector electrode is common. Since the electrodes are arranged as electrodes, it is impossible to form a functional circuit in which a plurality of active elements or passive elements are combined, and the separate temperature detection transistor 63 cannot be formed on the power transistor chip.

In view of the above conventional problems, the present invention has been made for the purpose of providing a transistor circuit having a bias circuit capable of more completely temperature compensation in an extremely short time.

[0009]

In order to solve the above-mentioned problems, a transistor circuit according to the present invention comprises a silicon power transistor including a base region and an emitter region formed by a double diffusion process, and a silicon power transistor which is the same body as the silicon power transistor. An element formed by forming a transistor having a certain area composed of a base region and an emitter region, which is electrically insulated from the silicon power transistor, on silicon, and a device formed separately from the silicon. It is composed of a bias circuit that detects the base-emitter voltage of the transistor on the mounting substrate and controls the bias voltage of the power transistor, detects the chip temperature of the silicon power transistor in a short time, and keeps its operating current constant. It is characterized by keeping.

[0010]

According to the present invention, the temperature of the power transistor chip having the above-mentioned structure is used for detecting the temperature of the power transistor chip having a certain area consisting of a base region and an emitter region electrically insulated from the silicon power transistor. The base-emitter voltage of the transistor is detected to make the collector current of the power transistor constant. Since the transistor for temperature detection is on the same silicon as the power transistor chip, a transistor circuit having a bias circuit that can perform temperature compensation more accurately in an extremely short time becomes possible.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a transistor circuit having a bias circuit according to the present invention will be described in detail below with reference to FIGS.

FIG. 1 is a circuit diagram of an emitter follower circuit having a bias circuit according to the first embodiment of the present invention. In FIG. 1, 1 is an NPN type silicon chip having a base region and an emitter region formed by a double diffusion process, 2 is a power transistor part, 3 is a temperature detecting transistor part, 4 is a PNP type transistor, 5 is a diode, 6 is a constant current circuit which may use a constant current diode, 7 is an input terminal of this emitter follower circuit,
8 is an output terminal of this emitter follower circuit, 9 is an emitter resistor of a power transistor, 10, 11, 12, 1
Reference numerals 3 and 3 are resistors for absorbing variations in transistors or diodes, respectively. The power transistor section 2 and the temperature detecting transistor section 3 are the same NPN.
Formed on the silicon chip 1 of the P type, PNP type transistor 4, diode 5, constant current circuit 6, emitter resistor 9 of power transistor, resistors 10, 11, 12, 1
3 is mounted on a mounting board formed separately. The mounting board formed separately may be a hybrid integrated circuit mounting board or a printed board.

The base terminal of the temperature detecting transistor 3 is connected to its collector terminal and used as a diode. A constant current circuit 6 is connected to the emitter terminal in order to generate a voltage between the base and emitter of the temperature detecting transistor 3. The emitter and the base terminal of the PNP type transistor 4 are connected to the base and the emitter terminal of the temperature detecting transistor 3, respectively, and the base-emitter voltage of the temperature detecting transistor 3 is changed to the PNP type transistor 4.
Is converted into the collector current of. The diode 5 is connected to the collector of the PNP type transistor 4 in order to convert the collector current of the PNP type transistor 4 into a voltage between the anode and the cathode of the diode 5. The anode and cathode of this diode 5 are connected to the base and emitter of the power transistor 2, respectively, and the voltage between the anode and cathode of the diode 5 is used as the bias voltage of the power transistor 2.

The operation of the emitter follower circuit configured as described above will be described below.

First, it is assumed that the emitter-follower circuit is in a balanced state at a certain temperature and the collector current of the power transistor 2 has a certain value. If the collector current of the power transistor 2 increases for some reason such as an input signal is input, the increase in collector current leads to an increase in collector loss, and as a result, the temperature of the power transistor chip 1 rises. .. As the chip temperature rises, the base-emitter voltage of the temperature detecting transistor 3 decreases and the base-emitter voltage of the PNP transistor 4 also decreases. As the base-emitter voltage of the PNP transistor 4 decreases, the collector current of the PNP transistor 4 decreases, and the anode-cathode voltage of the diode 5, that is, the bias voltage of the power transistor 2 also decreases. The collector current of the power transistor 2 tends to increase as the temperature rises, but is kept constant because the bias voltage decreases. Since the power transistor 2 and the temperature detecting transistor 3 are formed on the same NPN type silicon chip 1, this temperature compensation is accurately performed in an extremely short time.

As described above, according to this embodiment, an emitter follower circuit equipped with a bias circuit capable of more accurately temperature compensating in an extremely short time becomes possible.

FIG. 2 is a circuit diagram of a SEPP circuit having a bias circuit according to the second embodiment of the present invention.

In FIG. 2, 21 is an NPN type silicon chip having a base region and an emitter region formed by a double diffusion process, 22 is a power transistor part, 23 is a temperature detecting transistor part, and 24 is a base region and an emitter region. Is a PNP type silicon chip formed by a double diffusion process, 25 is a power transistor part, 26 is a temperature detecting transistor part, 27 is a PNP type transistor, 28
Is an NPN type transistor, 29 and 30 are diodes, 3
1 is a constant current circuit, and a constant current diode may be used, 3
2 is the input terminal of this SEPP circuit, 33 is this SEPP circuit
This is the output terminal of the circuit. The power transistor section 2
2. The temperature detecting transistor section 23 is formed on the same NPN type silicon chip 21, and the power transistor section 25 and the temperature detecting transistor section 26 have the same P.
The PNP transistor 27, the NPN transistor 28, the diodes 29 and 30, and the constant current circuit 31 formed on the NP type silicon chip 24 are separate from the NPN type silicon chip 21 and the PNP type silicon chip 24. It is mounted on the formed mounting board.

The base terminal of the temperature detecting transistor 23 is connected to its collector terminal and used as a diode. A constant current circuit 31 is connected to the emitter terminal in order to generate a voltage between the base and emitter of the temperature detecting transistor 23. The emitter and base terminals of the PNP type transistor 27 are connected to the base and emitter terminals of the temperature detecting transistor 23, respectively, and the base-emitter voltage of the temperature detecting transistor 23 is converted into the collector current of the PNP type transistor 27. The base terminal of the temperature detecting transistor 26 is connected to its collector terminal and used as a diode. A constant current circuit 31 is connected to the emitter terminal in order to generate a voltage between the base and emitter of the temperature detecting transistor 26. The emitter and base terminals of the NPN type transistor 28 are connected to the base and emitter terminals of the temperature detecting transistor 26, respectively, and the base-emitter voltage of the temperature detecting transistor 26 is converted into the collector current of the PNP type transistor 28. The diodes 29, 30 are inserted between the collectors of the PNP type transistor 27 and the NPN type transistor 28 in order to convert the collector current of the PNP type transistor 27 and the NPN type transistor 28 into the voltage between the anode and the cathode of the diodes 29, 30. The anode of the diode 29 and the cathode of the diode 30 are respectively the base of the power transistor 22,
Connect to the base of power transistor 25 and diode 2
The voltage between the anode and the cathode of 9 and 30 is used as the bias voltage of the power transistor 22 and the power transistor 25.

The SEPP circuit configured as described above can also perform temperature compensation more accurately in an extremely short time, as in the first embodiment.

FIG. 3 is a circuit diagram of a grounded-emitter circuit having a bias circuit according to the third embodiment of the present invention.

In FIG. 3, 41 is an NPN type silicon chip having a base region and an emitter region formed by a double diffusion process, 42 is a power transistor section, 43 is a temperature detecting transistor section, 44 is a PNP type transistor,
45 is a diode, 46 is a constant current circuit and may be a constant current diode, 47 is an input terminal of this grounded-emitter circuit, 48 is an output terminal of this grounded-emitter circuit, 49 is a collector resistor of a power transistor, and 50 is It is an emitter resistor of a power transistor. The power transistor section 42 and the temperature detecting transistor section 43 are formed on the same NPN type silicon chip 41, and the diode 45, the constant current circuit 46, and the resistors 49 and 50 are the same as the NPN type silicon chip 41. Are mounted on a mounting board formed separately. The base terminal of the temperature detecting transistor 43 is connected to its collector terminal and used as a diode. This temperature detection transistor 4
A constant current circuit 46 is connected to the emitter terminal in order to generate a voltage between the base and emitter of No. 3. The emitter and base terminals of the PNP type transistor 44 are respectively connected to the base and emitter terminals of the temperature detecting transistor 43, and the base-emitter voltage of the temperature detecting transistor 43 is converted into the collector current of the PNP type transistor 44. The diode 45 is connected to the collector of the PNP type transistor 44 in order to convert the collector current of the PNP type transistor 44 into a voltage between the anode and the cathode of the diode 45. The anode and cathode of the diode 45 are connected to the base and emitter of the power transistor 42, respectively, and the voltage between the anode and cathode of the diode 45 is used as the bias voltage of the power transistor 42.

The grounded-emitter circuit configured as described above can also perform temperature compensation more accurately in an extremely short time, as in the first embodiment.

[0024]

As described above, according to the present invention, the temperature detecting transistor is formed on the same silicon as the silicon power transistor and the voltage between the base and the emitter thereof is detected, so that the heat generation of the silicon power transistor is extremely short. In addition, the temperature of the operating current of the silicon power transistor can be accurately compensated for, and the temperature of the operating current of the silicon power transistor can be appropriately compensated.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an emitter-follower circuit including a bias circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a SEPP circuit including a bias circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a grounded-emitter circuit including a bias circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a SEPP circuit including a conventional bias circuit.

FIG. 5 is a cross-sectional view of a silicon transistor in which a base region and an emitter region are formed by a double diffusion process.

[Explanation of symbols]

1 NPN type silicon chip in which base region and emitter region are formed by double diffusion process 2 Power transistor part 3 Temperature detecting transistor part 4 PNP type transistor 5 Diode 6 Constant current circuit 7 Input terminal 8 Output terminal 9 Power transistor Emitter resistor 10 Resistor 11 Resistor 12 Resistor 13 Resistor 21 NPN type silicon chip with base region and emitter region formed by double diffusion process 22 Power transistor part 23 Temperature detecting transistor part 24 Base region and emitter PNP type silicon chip 25 formed by double diffusion process 25 power transistor section 26 temperature detecting transistor section 27 PNP type transistor 28 NPN type transistor 29 diode 30 diode 31 constant current circuit 32 S Input terminal of EPP circuit 33 Output terminal of SEPP circuit 41 NPN type silicon chip in which base region and emitter region are formed by double diffusion process 42 Power transistor part 43 Temperature detecting transistor part 44 PNP type transistor 45 Diode 46 Constant current Circuit 47 Input terminal of grounded-emitter circuit 48 Output terminal of grounded-emitter circuit 49 Collector resistor of power transistor 50 Emitter resistor of power transistor 71 Emitter region 72 Base region 73 Collector high specific resistance region 74 Collector high impurity concentration region 75 Collector backside Department

Claims (6)

[Claims] 1. A silicon power transistor including a base region and an emitter region formed by a double diffusion process, and a base region and an emitter electrically insulated from the silicon power transistor on the same silicon as the silicon power transistor. A silicon power transistor which detects a base-emitter voltage of the transistor on an element formed by forming a transistor having a certain area consisting of a region and a mounting substrate formed separately from the silicon. And a bias circuit that controls the bias voltage of the silicon power transistor, and detects the chip temperature of the silicon power transistor in a short time to keep its operating current constant. 2. The bias circuit comprises a complementary transistor of the transistor, the base terminal of the transistor and the emitter terminal of the complementary transistor, and the emitter terminal of the transistor and the base terminal of the complementary transistor are connected. The transistor circuit according to claim 1, wherein: 3. The transistor circuit according to claim 2, wherein a resistor is inserted in the emitter terminal of each of the transistor and the complementary transistor of the transistor. 4. The transistor circuit according to claim 1, wherein the silicon power transistor is used as an emitter follower. 5. The silicon power transistor is SE
The transistor circuit according to claim 1, wherein the transistor circuit is used as a PP circuit. 6. The silicon power transistor is used as a grounded-emitter circuit.
The transistor circuit described.