JPH05259504A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize easy facedown bonding of a semiconductor chip and a substrate with high position accuracy. CONSTITUTION:A projection part 4 which is used solely for positioning is provided to an electrode surface side of a semiconductor chip 1. A recessed part 9 corresponding to the projection part of the chip is provided to a mounting circuit substrate side. Positioning is completed readily by fitting of the recessed and projecting parts. Thereby, the following can be realized; (1) Positioning of registration deviation of 3mum. (2) Easy adjustment of positioning and high precision positioning mounting in multilayer lamination. (3) Assembly of good position accuracy with a substrate pattern even if position deviation exists between a chip electrode pattern and a chip external shape.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, in order to mount a semiconductor chip on a circuit board with high accuracy and certainty, a projection or a mark and a recess or a through hole provided on the chip and the circuit board. Regarding pore structure.

[0002]

2. Description of the Related Art Semiconductor chips used in the ultra high frequency band,
Conventionally, a method called face-down bonding has been widely used to mount an optical element or the like that allows light to enter or exit from the surface of a chip on a package or a circuit board. That is, as shown in FIG. 1, a semiconductor chip 1 having a pn junction is placed on a circuit board 4 with its electrode surface facing downward, and a p electrode 2 and a circuit wiring pattern 5 and two n electrodes 3 of the chip are placed. After performing a positioning operation so that the positions of the circuit wiring patterns 6 match, the Au / Sn solder formed on the surfaces of the p and n electrodes of the chip is melted and the two are bonded and fixed.

Conventionally, in such face-down bonding, for example, "Hybrid integrated circuit", edited by Sugaguchi and Haradome, Industrial Research Committee (October 1968), No. 180-1
As disclosed on page 81, a positioning method using a half mirror is adopted.

[0004]

However, in the above-mentioned conventional method, it is extremely difficult to improve the alignment accuracy because of the indirect alignment with the half mirror interposed, and it is usually about ± 20 μm. The alignment accuracy was the limit.

Electronic devices used especially in the super high frequency band,
For example, in a back illuminated PIN photodiode,
In some cases, the electrode pattern size of the chip was less than 20 μm in diameter, and the alignment accuracy during face-down bonding was a problem.

It is an object of the present invention to easily and highly accurately realize face-down bonding of a chip by positioning by fitting concave and convex portions. Further, the object of the present invention is to
Even in the case of surface mounting with multiple layers, it is necessary to assemble with high accuracy.

[0007]

The object of the invention is to easily align an electronic component chip on a circuit board by fitting a convex portion or a concave portion of the electronic component chip with a concave portion or a convex portion of the circuit board. By doing so, high accuracy of alignment can be obtained. Further, by applying this method in the case of multi-layer surface mounting, the positioning accuracy can be improved even in multi-layer surface mounting.

[0008]

As shown in FIG. 2, on the surface electrode side of the chip 1,
A concave portion 9 dedicated to fitting position alignment is provided on the circuit board 4 at a position corresponding to one or more convex portions 8 dedicated to position alignment. When the chip 1 is placed on the circuit board 4, the fitting state of the convex portion of the chip and the concave portion of the circuit board is confirmed by observing the inclination of the chip from the periphery.

The diameter of the convex portion 8 on the chip is slightly smaller than the inner diameter of the concave portion 9 on the circuit board. This set value can be arbitrarily set depending on the required alignment accuracy. As described above, the concave-convex fitting mounting of the chip and the substrate is possible.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 describes an example in which a back illuminated PIN photodiode chip is applied to the connection with a circuit board.

FIG. 2 shows a back illuminated InP PIN photodiode chip and its substrate circuit. On the front surface side of the back illuminated InP PIN photodiode chip 1, a minute p-type electrode 2 having a diameter of 20 μm and two n-type electrodes 3 having a length of 150 μm and a width of 40 μm are formed on both sides thereof. In addition, the metallization structure of the tip electrode is
Ti / Pt / Au / Sn (0.1 / 0.2 / on InP
(0.9 / 0.7 μm thickness) is formed by vapor deposition. Further, the metallized structure of the circuit board electrode is formed by depositing Cr / Au (0.05 / 0.1 μm thick) on the quartz glass substrate. The projections 8 dedicated to the alignment on the chip side according to the present invention are provided in the central portions of the n-type electrodes at two locations, each 30 × 30 × 3 μm
The thick Au is formed by plating. Further, in the central portion of the two n-type electrodes 3 on the side of the circuit board, fitting concave portions 9 for fitting with the convex portions 8 formed on the chip side are 33 × 33 × 5 μm each.
It is provided in depth.

A method for face-down bonding the chip 1 to the circuit board 4 will be described below. First, the chip 1 is chucked by a vacuum collet and placed at a predetermined position on the circuit board 4. At this time, the two convex portions provided on the chip are fitted into the two concave portions provided on the circuit board to complete the alignment.

The second embodiment shows an example applied to a parallel waveguide type optical arithmetic unit.

The parallel optical waveguides 13 and 15 shown in FIG. 3 are made of quartz glass, which is a transparent material for signals, and rectangular portions are formed by groove processing in parallel with the signal light transmission direction to form optical waveguides. It is a thing. The height of this waveguide is 200μ
It has a rectangular shape of m and a width of 150 μm. The pitch between the rectangular waveguides is 250 μm. Further, oblique groove processing of 45 degrees is performed in the direction perpendicular to the rectangular waveguide. This depth gradually increases by 50 μm from the input light side to form four grooves. A vapor deposition film of Au is applied to the surface of the rectangular waveguide and the oblique groove processed portion to a thickness of about 0.5 μm so as to enhance the optical confinement efficiency in the waveguide.

Two fitting recesses similar to those shown in FIG. 2 are formed on the side of the parallel optical waveguides 13 and 15 opposite to the side where the waveguides are formed. Two fitting protrusions are formed on each side of the one-sided element. The dimensions and electrode structure are the same as in FIG. Next, the surface amplification element array 4 is sandwiched, and Au / Sn fusion is performed by fitting of unevenness by flip-chip bonding so that the transmission directions of the rectangular waveguides are orthogonal to each other. The parallel optical waveguide 13 has a high melting point P on the alumina substrate 11 provided with two convex portions.
Bonded with b / Sn solder. The dimensions of the fitting irregularities are the same as in FIG. The PD array 12, the LD array 18, and the heat sink 19 are Pb as shown in FIG.
Bonding with / Sn.

The input light 16 from the LD array 18 is converted into collimated light by the microlens array 17, and the position of the light of each LD array element is adjusted so as to correspond to each waveguide of the parallel optical waveguide 15. After that, the microlens array 17 is fixed on the LD array 18. Input light 16
Is reflected in a direction perpendicular to the waveguide substrate surface by the oblique groove in each waveguide. The reflected light is a surface-type optical amplification element array 14
Is incident on the parallel optical waveguide substrate 13 after being subjected to the optical amplification and modulation action, and is condensed for each waveguide to output light 2
It becomes 1 and is incident on the PD array 12.

The product-sum operation is performed by using the light intensity of each element from the LD array 18 as an input vector, the surface amplification element array 14 as an operation matrix, and the light receiving sensitivity of each element of the PD array 12 as an output vector. Was completed. Similarly, by applying the amplification / attenuation action of each element of the surface amplification element array 14, optical communication between the input Xi and the output Yj,
That is, optical exchange could be performed.

The third embodiment will describe an example in which a parallel optical waveguide is applied to connection between electronic devices such as LSI.

FIG. 4 shows a parallel waveguide type optoelectronic information processing apparatus. The parallel optical waveguide substrate 35 is similar to that shown in FIG. Two concave portions for alignment are provided on the surface of the parallel optical waveguide 35 opposite to the waveguide portion,
Further, in the microprocessor LSI 34 having the same electrode pattern 36 and two convex portions as in FIG. 2, Ti / Pt /
Protrusions are formed by Au electrodes, and the protrusions and recesses are fitted to each other for alignment and flip-chip bonding. This L
Four SIs 34 are mounted in parallel in the parallel optical waveguide 35, and one PD array 33 having two convex portions corresponds to one LSI, and the alignment is performed by fitting the concave and convex portions in parallel. After that, it is flip-chip bonded by Au / Sn. The signal light 39 emitted from the LD array 38 travels in parallel for each waveguide similarly to that shown in FIG. 3, is reflected by the oblique groove, and is incident on each PD array 33 in parallel. This light is converted into an electric signal and transmitted to an adjacent LSI as an input signal. The output signal electrically processed by the LSI 34 is taken out through the electrode pattern 36 of the parallel waveguide 35.

The light from the LD array 38 is aligned with the microlens array 37 so as to become collimated light, and then fixed on the LD array 38 on the substrate. Similarly, the parallel optical waveguide 35 to which the LSI 34 and the PD array 33 are bonded is bonded to the substrate 31 by Pb / Sn solder via a spacer.

As a result, the parallel waveguide type optoelectronic information processing apparatus is compact and can be cooled without taking a spatial space, and parallel signal processing to the processor LSI is enabled.

[0023]

According to the invention described above, the alignment accuracy in face-down bonding can be set to about 5 μm, and in particular, it greatly contributes to the mounting of a device which requires face-down bonding as an easy alignment method. ..

[Brief description of drawings]

FIG. 1 is a configuration diagram of a back illuminated PIN photodiode chip and a circuit board showing a conventional example.

FIG. 2 is a concavo-convex configuration diagram of a back illuminated PIN photodiode chip and a circuit board surface showing an embodiment of the present invention.

FIG. 3 is a configuration diagram of a parallel waveguide type optical arithmetic unit showing an embodiment of the present invention.

FIG. 4 is a configuration diagram of a parallel waveguide type optoelectronic information processing apparatus showing an embodiment of the present invention.

[Explanation of symbols]

1 ... Semiconductor chip (photodiode), 2 ... p electrode, 3
... n electrode, 4 ... circuit board, 5 ... p electrode wiring pattern, 6
... n-electrode wiring pattern, 7 ... combination mark, 8 ... convex portion, 9 ... concave portion, 11 ... alumina substrate, 12 ... PD array, 13, 15 ... parallel optical waveguide substrate, 14 ... planar optical amplification element array, 16 Input signal light, 17 Microlens array, 18 LD array, 19 Heat sink, 21
... output light, 22 ... convex portion, 23 ... concave portion, 31 ... substrate, 32
... Spacer, 33 ... PD array, 34 ... Microprocessor LSI, 35 ... Parallel optical waveguide substrate, 36 ... Electrode pattern, 37 ... Microlens array, 38 ... LD array, 39 ... Signal light, 40 ... Convex portion, 41 ... Recessed portion ..

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomohiro Suzuki 180 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Communication Systems Co., Ltd. Central Research Laboratory

Claims (1)

[Claims] 1. A semiconductor device in which a semiconductor chip is mounted on a circuit board, wherein the chip and the board are each provided with projections and depressions for performing alignment by fitting.