JPH05259462A - Insulated gate type bipolar transistor - Google Patents

Abstract

PURPOSE:To enlarge a turn off SOA (safe operation area) without lowering on voltage.switching time property by inserting a resistor and a inductive load connected in series, between a gate electrode and a gate electrode. CONSTITUTION:An n<+>-layer 2 (second region) and an n<-> layer 3 (third region) are stacked on a p<+>-substrate 1 (first region), and a gate oxide film 6 is made, and then a gate electrode 7 is made. Using the same mask as the gate electrode pattern, a p<+>-channel formation layer 4 (fourth region) is made, and then with the gate electrode 7 as a mask, an n<+>-layer 5 (fifth region) is made, and an insulating film 8 is made, and a source electrode 9 is made on the surface, and a drain electrode 10 is made on the rear side. Furthermore, with the view of raising recoupling, a life time killer is made on a silicon substrate, and inductive load 11 and a gate resistor 12 for discharge are inserted in series between one place of the gate electrode 7n and a gate terminal G. Hereby, return off is prevented, and SOA becomes large.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as IGBT) used as a power switching element.

[0002]

2. Description of the Related Art Recently, I has been used as a power switching element.
The GBT is generally used, but this is a vertical MOS
It has a structure in which a layer of opposite conductivity type is added to the drain electrode side of the drain region of the FET. That is, as shown for one unit cell in FIG. 2, p ⁺ on the substrate 1 through the low-resistance n ⁺ layer 2 of the high-resistance n ^- layer 3 is formed, the n ^- surface layer of the layer 3 The p ⁺ layer 4 and the n ⁺ layer 5 are selectively formed on the surface layer of the p ⁺ layer 4.
The gate electrode 7 connected to the gate terminal G via the gate insulating film 6 is formed on the surface portion of the p ⁺ layer 4 sandwiched between the n ⁻ layer 3 and the n ⁺ layer 5 as a channel region. It is provided. A source electrode 9 insulated from the gate electrode 7 and the insulating film 8 and connected to the source terminal S is provided on the surfaces of the p ⁺ layer 4 and the n ⁺ layer 5, and a drain terminal D is provided on the surface of the p ⁺ substrate 1. The drain electrodes 10 are in contact with each other.

In this IGBT, the source terminal S is grounded,
When a positive voltage is applied to the gate terminal G and the drain terminal D,
Built-in M composed of n ⁺ layer 2 and n ⁻ layer 3, p ⁺ layer 4, n ⁺ layer 5, gate electrode 7 and source electrode 9
The OSFET is turned on, and electrons flow into the n ⁻ layer 3 via the channel region. p ⁺ substrate 1 to n ⁻ layer 3 has n
Holes corresponding to the inflow of electrons are injected through the ⁺ layer 2, and conductivity modulation occurs in the n ⁻ layer 3, so that the resistance in this region becomes low and a low on-resistance is conducted.

[0004]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Has a low on-voltage, but has a problem that the switching time is long because the recombination rate of electrons and holes in the n ⁻ layer 3 is low. In order to solve this problem, in order to increase the recombination rate of electrons and holes, a silicon body is irradiated with an electron beam or gold is diffused to introduce a lifetime killer to shorten the lifetime. There is a way. However, when these methods are executed, the on-voltage is increased. To shorten the switching time while keeping the on-voltage low, there is a method of lowering the impurity concentration of the n ⁻ layer 3 to quickly expand the depletion layer. However, due to this, when there is a turn-off operation, the rate of increase in drain voltage per unit time dV _D / dt rises sharply, and the n ⁻ layer 3
-Displacement current flows through the capacitor formed of the gate insulating film 6 and the gate electrode 7. As a result, the MOSFET that was once turned off is turned on again, and the built-in MOSFET is turned on when the high drain voltage is applied. This phenomenon causes a problem that the turn-off SOA (safe operating area) of the IGBT is reduced.

In view of the above problems, it is an object of the present invention to reduce the on-voltage / switching time characteristics,
The turn-off SOA is to provide an expanded IGBT.

[0006]

In order to achieve the above object, the present invention provides a first region having a first conductivity type and a second region having a second conductivity type on the first region. A low impurity concentration third region having a second conductivity type on the second region, a fourth region having a first conductivity type selectively formed on the third region surface layer, and a surface of the fourth region. A high impurity concentration fifth region having a second conductivity type selectively formed in the layer, and a portion sandwiched by the third region and the fifth region of the surface of the fourth region as a channel region thereon. An IGBT comprising a gate electrode provided through a gate insulating film, a source electrode commonly contacting the surfaces of the fourth region and the fifth region, and a drain electrode contacting the first region Between the electrode and the gate power supply And those inserted in series connection. It is composed of a plurality of unit cells having the same structure, the gate electrodes of the respective cells are connected and integrally formed, and one of the gate electrodes is connected to the gate electrode via a resistance and an inductive load. It is valid. Introducing a lifetime killer into the semiconductor body having the first to fifth regions, and reducing the inductance of the inductive load to 0.
It is effective that it is 8 μH or more.

[0007]

[Operation] High dV _D / which occurs when the IGBT is turned off
The displacement current flowing in the circuit connecting the gate electrode and the gate power supply by dt is suppressed by the inductive load inserted in the circuit, so that the built-in MOSFET can be prevented from turning on again. Therefore, the SOA becomes large.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an IGBT single cell according to an embodiment of the present invention, and the same parts as those in FIG. 2 are designated by the same reference numerals. An IGBT having a plurality of such single cells is
It was manufactured by the following method as in the past. First, p ⁺ substrate 1
The n ⁺ layer 2 is formed on the surface of the (first region) by an epitaxial growth method.
(Second region) and n ⁻ layer 3 (third region) were laminated. Next, after forming the gate oxide film 6, the gate electrode 7 is formed,
P ⁺ using the same mask as the gate electrode patterning
Ion implantation was performed for the channel forming layer 4 (fourth region). After the p ⁺ layer 4 was formed by thermal diffusion, the n ⁺ layer 5 (fifth region) was formed by the ion implantation method and the thermal diffusion method using the gate electrode 7 as a mask. Subsequently, the insulating film 8 was formed, and then the source electrode 9 was formed on the surface of the insulating film 8. Finally, the drain electrode 10 was formed on the back surface side. Further, the silicon substrate is irradiated with an electron beam for the purpose of increasing the recombination rate to form a lattice defect that becomes a lifetime killer,
After that, heat treatment was performed at 330 ° C. for 2 hours. The gate electrode 7 of each cell on the surface of the silicon substrate is formed of a connected polycrystalline silicon layer, and an inductive load (L _G ) 11 and a discharge gate resistance are provided between one portion thereof and the gate terminal G. ( _RG ) 12 was inserted in series. L _G is 1 μH and R _G is
It is 25Ω. The n ⁺ layer 2 of this IGBT has a resistivity of 0.05 Ωc
m, thickness 10 μm, n ⁻ layer 3 has a resistivity of 120 Ωcm, thickness 65 μ
The device rating is 600 V and the current capacity is 100 A.

FIG. 3 shows the respective turn-off SOAs at room temperature for this IGBT and an IGBT made in the same way, but with no L _G connected, on lines 31 and 32. Figure 4 shows the measurement circuit used for the SOA measurement.
600 via μH inductive load 42 and reverse current blocking diode 43
A V power source 44 is connected. Gate power supply is pulse power supply
45. As is apparent from FIG. 3, the IGBT having an inductive load connected to the gate circuit has a larger turn-off SOA, and is turned off without breaking up to 600 A, which is 6 times the rated value.

FIG. 5 shows a similar SOA comparison at 125.degree. C., with line 5 for the IGBT of the above embodiment.
Line 52 shows the case where 1, L _G are not connected. As is clear from Fig. 4, the IG with an inductive load connected to the gate circuit
The BT has a larger SOA, and is off without breaking up to 500 A, which is five times the rating.

[0011]

According to the present invention, by inserting an inductive load in the gate circuit, dV _D / dt at turn-off can be achieved.
As a result, the displacement current flowing in the capacitor formed in the MOS structure can be suppressed, and re-turn-on is prevented, so that the SOA becomes large.

[Brief description of drawings]

FIG. 1 is a sectional view of an IGBT according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional IGBT single cell.

FIG. 3 is an IGBT according to an embodiment of the present invention and a conventional IGBT.
SOA comparison diagram at room temperature

4 is a measurement circuit diagram of the SOA of FIG.

FIG. 5 is an IGBT according to an embodiment of the present invention and a conventional IGBT.
SOA comparison diagram at 125 ℃

[Explanation of symbols]

1 p ⁺ first region 2 n ⁺ second region 3 n ^- third region 4 p ⁺ fourth region 5 n ⁺ fifth region 6 the gate insulating film 7 gate electrode 9 a source electrode 10 drain electrode 11 inductive load 12 for discharge Gate resistance

Claims (4)

[Claims] 1. A first region having a first conductivity type, a second region having a second conductivity type on the first region, and a second impurity type second region having a second conductivity type on the second region. High impurity concentration having three regions, a fourth region having a first conductivity type selectively formed in the surface layer of the third region, and a second region having a second conductivity type selectively formed in the surface layer of the fourth region A fifth region, a gate electrode provided on the fourth region surface portion with a portion sandwiched by the third region and the fifth region as a channel region through a gate insulating film, and the fourth region. A source electrode commonly contacting the surface and the surface of the fifth region, and a drain electrode contacting the first region, wherein a resistance and an inductive load are connected in series between the gate electrode and the gate power supply. Insulated gate type bipolar La transistor. 2. A plurality of unit cells having the same structure, wherein the gate electrodes of each cell are connected and integrally formed, and one of the gate electrodes is connected to the gate electrode via a resistance and an inductive load. The insulated gate bipolar transistor according to claim 1. 3. The insulated gate bipolar transistor according to claim 1, wherein the lifetime killer is introduced into the semiconductor element body having the first to fifth regions. 4. The insulated gate bipolar transistor according to claim 1, 2 or 3, wherein the inductance of the inductive load is 0.8 μH or more.