JPH05259175A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a bipolar transistor which realizes further acceleration by forming an area of a pedestal region for suppressing a base extruding effect further smaller in a self-alignment, and reducing a parasitic capacity between a base and a collector in the method for manufacturing a high speed bipolar transistor. CONSTITUTION:The method for manufacturing a semiconductor device comprises the steps of laminating to form a first conductive layer 3 for a base leading electrode having an opening 5 in an emitter forming region and an insulating layer 4 on a one conductivity type semiconductor layer 1, implanting an opposite conductivity type impurities through the opening 5 to form an inner base region 6 on the layer 1, and forming a sidewall insulating layer 7 on the sidewall of the opening 5. The method further comprises the steps of forming a second conductive layer 8 as a part of an emitter electrode in the opening 5 formed in the layer 7, and implanting one conductivity type impurities through the layer 8 to form a one conductivity type pedestal region 9 under the region 6 directly under the emitter forming region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a high speed bipolar transistor.

With the further development of the advanced information society, higher speeds of computers are required. In order to meet this demand, it is necessary to further speed up the integrated circuit element that is a component of the computer, and further it is necessary to speed up the transistor that is a constituent element of the integrated circuit element.

[0003]

2. Description of the Related Art FIG. 4 is a sectional view of a main part of a self-aligned bipolar transistor formed by a conventional method according to the gist of the present invention. In the figure, 1 is an n ^- type silicon substrate, 2 is a field insulating layer,
6 is a p-type internal base region, 12 is a p-type external base region, 3 is a base lead electrode made of polysilicon, 4 is a silicon dioxide layer, and 7 is formed on the sidewall of the opening 5. 9 is n
The pedestal area of the mold.

The pedestal region 9 has a high concentration of impurities of a conductivity type opposite to that of the internal base in the lower part of the internal base 6 in order to suppress the expansion of the base width due to the base pushing out effect (also called Kirk effect) in the high current injection region. This is the area that was introduced in. By suppressing the spread of the base width, it is possible to prevent the cutoff frequency from lowering and to speed up the transistor.

As a conventional method of forming a pedestal, as shown in FIG. 4A, an n ⁻ -type impurity is formed through an emitter / base forming opening 5 formed in a base extraction electrode 3 and a silicon dioxide layer 4. Ion implantation is performed, but FIG.
As shown in (b), after the silicon dioxide layer 7 is formed on the side wall of the opening 5, n ⁻ -type impurities are ion-implanted through the opening 5 to selectively remove n ⁻ type impurities into the lower portion of the internal base 6 immediately below the emitter region. Methods of forming the mold pedestal region 9 are known.

[0006]

The conventional bipolar transistor manufacturing method has the following advantages (1), but has the drawback (2). (1) The self-alignment allows the pedestal region to be formed only directly under the emitter or the internal base. Although this portion is an extremely fine area, it can be formed without the need for lithography technology that requires high resolution and high alignment accuracy. (2) Since the impurity concentration in the pedestal region just below the internal base becomes high, the parasitic capacitance between the base and the collector increases, which prevents the bipolar transistor from operating at high speed.

Therefore, it is necessary to make the disadvantage shown in (2) even smaller in order to achieve higher speed, while taking advantage of the advantage shown in (1) above. An object of the present invention is to provide a method for manufacturing a bipolar transistor in which the area of a pedestal region for suppressing the base pushing effect is formed to be smaller by self-alignment, and the parasitic capacitance between the base and the collector is reduced to realize further high speed. To provide.

[0008]

The above object is to insulate a first conductive layer (3) for a base lead electrode having an opening (5) in an emitter formation region on a semiconductor layer (1) of one conductivity type. Stacking layer (4) and said opening (5)
Forming an internal base region (6) in the one conductivity type semiconductor layer (1) by introducing an impurity of opposite conductivity type through a sidewall insulating layer (7) on the sidewall of the opening (5). A step of forming, a step of forming a second conductive layer (8) forming a part of the emitter electrode in the opening (5) in which the side wall insulating layer (7) is formed, and a step of forming the second conductive layer. A step of penetrating the layer (8) to introduce an impurity of one conductivity type to form a pedestal region (9) of one conductivity type under the internal base region (6) immediately below the emitter formation region. It is achieved by the manufacturing method of.

[0009]

[Operation] FIG. 1 is a diagram for explaining the principle. The same members as those shown in FIG. 4 are designated by the same symbols. When a second conductive layer 8 that will be a part of the emitter electrode is formed in the opening 5 where the sidewall insulating layer 7 is formed and impurities are ion-implanted, the second conductive layer 8 in the region in contact with the semiconductor layer 1 In the region indicated by A in FIG. 1, impurities are introduced into the lower portion of the internal base 6 through the second conductive layer 8, but the region where the sidewall of the second conductive layer 8 is formed, that is, in FIG.
In the region indicated by B, the second conductive layer 8 is thick in the ion implantation direction, so that no impurity is introduced into the semiconductor layer 1 through this portion. Of course, the acceleration energy of ion implantation is selected so that it will be like this. Depending on the case, ions may slightly penetrate into the semiconductor layer 1 even in the region indicated by B, but the amount of impurities introduced into the semiconductor layer 1 in the region indicated by A may be reduced by an order of magnitude. You can still choose the acceleration energy.

Since the region into which the impurities for forming the pedestal are ion-implanted is limited to the region indicated by A in FIG. 1, the region indicated by C in FIG.
It becomes smaller than the size of the conventional pedestal formed corresponding to the region indicated by D in (b), and the parasitic capacitance between the base and the pedestal (collector) becomes smaller.

It should be noted that the second conductive layer 8 used for forming the pedestal does not need to be specifically formed in order to carry out the method of the present invention. This is because in the current general self-aligned bipolar transistor, the emitter is formed by ion-implanting the impurity for forming the emitter into the polysilicon layer formed in the opening of the emitter forming region, and performing the heat treatment. Since the method of diffusing the impurities in the silicon layer into the semiconductor layer is general, this polysilicon layer can be used as the second conductive layer for forming the pedestal.
The area of the pedestal can be reduced without adding any process.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a bipolar transistor according to an embodiment of the present invention will be described below with reference to the drawings.

Referring to FIG. 2A, for example, a field insulating layer 2 having a thickness of about 6000 Å is formed on the n ⁻ type silicon substrate 1 by using a normal LOCOS method.

Referring to FIG. 2B, the polysilicon layer 3 doped with boron is set to about 3000 Å.
It is formed to a thickness, and is patterned to be removed from the region excluding the region for forming the base lead electrode. Next, a silicon dioxide layer 4 is formed to a thickness of about 3000 Å by using the CVD method, and the silicon dioxide layer 4 and the polysilicon layer 3 described above are formed.
And are patterned to form an opening 5 exposing the silicon substrate 1 in the emitter formation region.

See FIG. 2C. The exposed surface of the silicon substrate 1 and the polysilicon layer 3 side.
A thermal oxide film (not shown) with a thickness of about 200Å is formed on the surface.
After that, the impurity boron is dosed 3 × 10¹³cm ^-2Striking
Ion implantation with a built-in energy of 10 KeV
The base region 6 is formed. Then, using the CVD method,
Form a silicon oxide layer and etch it anisotropically
The silicon dioxide layer 7 remains only on the side wall of the opening 5.
It should be noted that the formation of the thermal oxide film with a thickness of about 200Å described above is
Stabilizes the interface between the substrate and the crystal during ion implantation
The purpose is to prevent the occurrence of defects.
Yes, and may be omitted in some cases.

As shown in FIG. 3A, as an example, a polysilicon layer 8 is formed to a thickness of about 1000 Å, and an impurity phosphorus is ion-implanted with a dose amount of 5 × 10 ¹² cm ^-2 and an implantation energy of 400 KeV to form a pedestal region 9. .. Next, the impurity arsenic is added at a dose of 1 × 1.
Ions are implanted into the polysilicon layer 8 with an implantation energy of 0 ¹⁶ cm ^-2 and an implantation energy of 40 KeV.

Referring to FIG. 3B, the polysilicon layer 8 is patterned so as to remain only in the vicinity of the emitter electrode formation region, and the opening 10 for the base contact is formed in the silicon dioxide layer 4 formed of the polysilicon layer 3 above the base extraction electrode. To form. Although not shown, an opening for collector contact is formed in the silicon dioxide layer 4 in the collector electrode formation region.

As shown in FIG. 3 (c), heat treatment is performed to diffuse and activate the impurity arsenic in the polysilicon layer 8 in the surface layer of the internal base 6 to form the emitter 11, and the polysilicon for the base extraction electrode is also formed. The impurity boron in the layer 3 is diffused into the silicon substrate 1 to form the external base region 12.

Next, an aluminum film is formed by a known method, and the aluminum film is patterned to form an emitter electrode 13, a base electrode 14 and a collector electrode (not shown). The polysilicon layer 8 may be patterned before the ion implantation step for forming the pedestal and the ion implantation step for forming the emitter. Further, the ion implantation for forming the emitter may be performed before the ion implantation for forming the pedestal. Furthermore, the structure of the opening for forming the emitter is not limited to the structure shown in FIGS.
The SST (Super Self-Aligned Transis) shown in FIG.
tor) and a transistor having the structure disclosed in Japanese Patent Laid-Open No. 62-183558, and SICOS (SIde wall ba shown in FIG. 5B).
se COntact Structure), non-self-a shown in Fig. 5 (c)
The pedestal according to the present invention can be formed in any of the lign type transistor structures.

Further, although the above description has been made with respect to the NPN type bipolar transistor, it is naturally applicable to the PNP type transistor by reversing the N type and the P type.

[0021]

As described above, in the method of manufacturing a semiconductor device according to the present invention, the pedestal region is formed by ion-implanting impurities after forming a conductor layer forming a part of the emitter electrode in the emitter formation opening. Therefore, the pedestal can be formed small by self-alignment without increasing the number of manufacturing steps. As a result, the spread of the width of the pedestal region is suppressed, and the parasitic capacitance between the base and the collector is reduced, so that the speed of the bipolar transistor can be increased.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory view of the manufacturing process of the bipolar transistor according to the present invention.

FIG. 3 is an explanatory view of the manufacturing process of the bipolar transistor according to the present invention.

FIG. 4 is an explanatory diagram of a manufacturing process of a bipolar transistor according to a conventional technique.

FIG. 5 is a diagram showing various shapes of openings in an emitter formation region.

[Explanation of symbols]

 1 semiconductor layer (silicon substrate) 2 field insulating layer 3 first conductive layer (polysilicon layer) 4 insulating layer (silicon dioxide layer) 5 opening 6 internal base 7 sidewall insulating layer (silicon dioxide layer) 8 second conductive layer (Polysilicon layer) 9 Pedestal region 10 Opening 11 Emitter 12 External base 13 Emitter electrode 14 Base electrode

Claims (1)

[Claims] 1. A first conductive layer (3) for a base extraction electrode having an opening (5) in an emitter formation region and an insulating layer (4) are laminated on a semiconductor layer (1) of one conductivity type. A step of introducing impurities of opposite conductivity type through the opening (5) to form an internal base region (6) in the one conductivity type semiconductor layer (1), and a sidewall on the sidewall of the opening (5). Forming an insulating layer (7), forming a second conductive layer (8) forming a part of an emitter electrode in the opening (5) in which the sidewall insulating layer (7) is formed, Forming one conductivity type pedestal region (9) below the internal base region (6) immediately below the emitter formation region by penetrating the second conductive layer (8) and introducing one conductivity type impurity; A method of manufacturing a semiconductor device, comprising: