JPH05259083A - Plasma cleaning after-treatment of cvd device - Google Patents
Plasma cleaning after-treatment of cvd deviceInfo
- Publication number
- JPH05259083A JPH05259083A JP9027592A JP9027592A JPH05259083A JP H05259083 A JPH05259083 A JP H05259083A JP 9027592 A JP9027592 A JP 9027592A JP 9027592 A JP9027592 A JP 9027592A JP H05259083 A JPH05259083 A JP H05259083A
- Authority
- JP
- Japan
- Prior art keywords
- film
- reaction chamber
- plasma
- fluorine
- cleaning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/4401—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
- C23C16/4405—Cleaning of reactor or parts inside the reactor by using reactive gases
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体基板上にＣＶＤ
膜を形成するＣＶＤ装置のクリーニング技術に関するも
ので、特に反応室をプラズマ・ドライ・エッチングによ
りプラズマ・クリーニングした後に行なう後処理方法に
係るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to CVD on a semiconductor substrate.
The present invention relates to a cleaning technique of a CVD apparatus for forming a film, and particularly to a post-treatment method performed after plasma cleaning a reaction chamber by plasma dry etching.
【０００２】[0002]
【従来の技術】従来例として、コールド・ウォール（co
ld wall ）型プラズマＣＶＤ装置により、半導体基板上
にプラズマ・シリコン酸化膜（以下Ｐ−Ｓi Ｏ膜と略
記）を形成するデポジション（deposition、堆積）／ク
リーニング（cleaning、洗浄）・サイクルについて、図
面を参照し、簡単に説明する。図６は、従来のプレ・デ
ポジション後の反応室内を示すプラズマＣＶＤ装置の断
面図、図２（ｂ）は従来のデポジション／クリーニング
・サイクの流れ図である。2. Description of the Related Art As a conventional example, a cold wall (co
Drawing of deposition / cleaning cycle for forming plasma silicon oxide film (hereinafter abbreviated as P-SiO film) on semiconductor substrate by ld wall) type plasma CVD device For a brief explanation. FIG. 6 is a sectional view of a plasma CVD apparatus showing the inside of a conventional reaction chamber after pre-deposition, and FIG. 2B is a flow chart of a conventional deposition / cleaning cycle.
【０００３】まずウェーハを反応室１２に設置しない状
態で、反応室１２内に厚さ1.0 μmのＰ−Ｓi Ｏ膜１１
を堆積し、反応室１２の条件（condition ）を安定化さ
せる（プレ・デポジションと略記）。この後、ロードロ
ック室１８を介して反応室内にウェーハ（図示なし）を
設置し、所定の膜厚のＰ−Ｓi Ｏ膜をデポジションする
（ウェーハ・デポジションと略記）。引き続き、このウ
ェーハ・デポジション工程を繰り返し、繰り返したウェ
ーハ上のデポジション膜厚の総計が、例えば30μm （こ
の膜厚は、膜厚均一性や、ダストレベルから規定され
る）となったところでウェーハ・デポジション工程を終
える。次にＣＦ4 ／Ｏ2 ガス系で、プラズマ・ドライ・
エッチングを行ない、反応室内をクリーニングして、デ
ポジション／クリーニング・サイクルを完結する。この
後、再び 1.0μm のＰ−Ｓi Ｏ膜のプレ・デポジション
を行ない、上記サイクルを繰り返す。First, in a state where the wafer is not set in the reaction chamber 12, the P-SiO 2 film 11 having a thickness of 1.0 μm is formed in the reaction chamber 12.
To stabilize the condition of the reaction chamber 12 (abbreviated as pre-deposition). After that, a wafer (not shown) is placed in the reaction chamber through the load lock chamber 18, and a P—SiO 2 film having a predetermined film thickness is deposited (abbreviated as wafer deposition). Subsequently, this wafer deposition process is repeated, and when the total deposition film thickness on the repeated wafer reaches, for example, 30 μm (this film thickness is defined by film thickness uniformity and dust level), the wafer・ End the deposition process. Next, using CF 4 / O 2 gas system, plasma dry
Etch and clean reaction chamber to complete deposition / cleaning cycle. After this, a 1.0 .mu.m P-SiO film is again pre-deposited and the above cycle is repeated.
【０００４】一般に、プラズマＣＶＤ装置では、膜厚の
均一性や、ダストレベルを考慮して、ウェーハ・デポジ
ション工程でのデポジション膜厚の総計が、一定値以上
となった時点で、ＣＦ4 、Ｃ2 Ｆ6 、ＣＨＦ3 、Ｓ
Ｆ6 、ＮＦ3 など弗素原子を有するガスを主体に、Ｏ2
やＨ2 を混合した反応ガスを用いて、プラズマ・ドライ
・エッチング法で反応室内をクリーニングする。次にウ
ェーハ・デポジションを行なう前に、膜厚の均一性、膜
質の安定化及び反応室材料（例えばステンレススチール
等）や電極材料（例えばアルミニウム、カーボン等）か
らの汚染防止等を目的として、反応室にウェーハを設置
しないで、ウェーハ・デポジション膜と同質のプラズマ
ＣＶＤ膜、例えばウェーハ・デポジション膜がＰ−Ｓi
Ｏ膜の場合にはＰ−Ｓi Ｏを、またＰ−Ｓi Ｎ膜の場合
にはＰ−Ｓi Ｎを、反応室内に厚さ 1〜 2μm 程度、プ
レ・デポジションを行なっている。プレ・デポジション
直後に、ウェーハに形成したＰ−Ｓi Ｏ膜を二次イオン
質量分析法（Secondry Ion Mass Spectroscopy、ＳＩＭ
Ｓ）で分析したところ、プラズマ・ドライ・エッチング
条件にもよるが、 0.5〜5.0 at％（アトムパーセント）
程度の弗素原子が検出された。この弗素原子含有Ｐ−Ｓ
i Ｏ膜を50℃の温水に10時間浸漬後、温水中に溶出した
弗素量を原子吸光法で評価したところ、Ｐ−Ｓi Ｏ膜中
に含有される弗素量の 7〜13％が温水中に溶出してい
た。Generally, in a plasma CVD apparatus, CF 4 is added when the total deposition film thickness in the wafer deposition process exceeds a certain value in consideration of film thickness uniformity and dust level. , C 2 F 6 , CHF 3 , S
O 2 is mainly composed of a gas having a fluorine atom such as F 6 and NF 3.
The reaction chamber is cleaned by plasma dry etching using a reaction gas containing H 2 and H 2 . Next, before performing wafer deposition, for the purpose of uniformity of film thickness, stabilization of film quality, and prevention of contamination from reaction chamber materials (such as stainless steel) and electrode materials (such as aluminum and carbon), Without placing a wafer in the reaction chamber, a plasma CVD film of the same quality as the wafer deposition film, for example, the wafer deposition film is P-Si.
In the case of the O film, P-SiO and in the case of the P-SiN film, P-SiN is predeposited in the reaction chamber to a thickness of about 1 to 2 .mu.m. Immediately after pre-deposition, the P-SiO film formed on the wafer is subjected to secondary ion mass spectrometry (SIM).
According to S), it depends on plasma dry etching conditions, but it is 0.5 to 5.0 at% (atom percent).
Some fluorine atoms were detected. This fluorine atom-containing PS
After immersing the iO film in hot water at 50 ° C for 10 hours, the amount of fluorine eluted in the hot water was evaluated by an atomic absorption method. As a result, 7-13% of the amount of fluorine contained in the P-SiO film was found to be in hot water. Had been eluted.
【０００５】すなわち反応室内を弗素原子を有する反応
ガスを用いて、プラズマ・ドライ・エッチング法でクリ
ーニングした後では、プレ・デポジションを行なって
も、その直後のウェーハ上に形成されるＰ−Ｓi Ｏ膜中
には、弗素原子が含有されており、該Ｐ−Ｓi Ｏ膜が、
温度50℃程度の湿度の高い雰囲気中に置かれると、結露
した水分中に弗素原子が溶出することが予想される。That is, after cleaning the inside of the reaction chamber by a plasma dry etching method using a reaction gas containing fluorine atoms, even if pre-deposition is performed, P-Si formed on the wafer immediately after that is deposited. Fluorine atoms are contained in the O film, and the P-SiO film is
When placed in an atmosphere of high humidity at a temperature of about 50 ° C, it is expected that fluorine atoms will elute in the condensed water.
【０００６】以上の結果をふまえ、ＰＣＴ（Pressure C
ooker Test、試験条件 127℃− 2.5kg／cm2 ）によるＡ
l 配線（組成 1％Ｓi 、 0.5％Ｃu 、残Ａl ）の弗素腐
食（Corrosion 、コロージョン）耐性を評価した。その
結果ＰＣＴ98時間より 1％の弗素腐食不良が発生した。
なおＰＣＴによる弗素腐食耐性評価の試料は、図５の断
面図に示すように、半導体基板（ウェーハ）５０を覆う
弗素含有Ｐ−Ｓi Ｏ膜５１ａを形成した後、その上に 1
％Ｓi と 0.5％Ｃu を含むＡl 配線５２をパターニング
し、さらに弗素含有Ｐ−Ｓi Ｏ膜５１ｂで該Ａl 配線５
２を被覆したもので、ウェーハ状態で試験した。また前
記ＰＣＴでは、密閉された温度 127℃の水蒸気の雰囲気
（蒸気圧 2.5kg／cm2 ）中に、前記試料を所定時間放置
した後、Ａl 配線の電気抵抗測定または顕微鏡による目
視判定により、弗素腐食不良を評価する。Based on the above results, PCT (Pressure C
ooker Test, test condition 127 ℃ -2.5kg / cm 2 ) A
l Wiring (composition 1% Si, 0.5% Cu, remaining Al) was evaluated for resistance to fluorine corrosion. As a result, 1% of fluorine corrosion failure occurred from PCT 98 hours.
As shown in the cross-sectional view of FIG. 5, the sample for evaluation of fluorine corrosion resistance by PCT has a fluorine-containing P—SiO film 51a which covers the semiconductor substrate (wafer) 50, and is formed on top of it.
The Al wiring 52 containing% Si and 0.5% Cu is patterned, and further, the Al wiring 5 is formed by a fluorine-containing P--SiO film 51b.
2 was coated and tested in the wafer state. In the PCT, after leaving the sample for a predetermined time in a sealed atmosphere of water vapor (vapor pressure 2.5 kg / cm 2 ) at a temperature of 127 ° C., fluorine resistance was measured by measuring the electrical resistance of Al wiring or visually observing with a microscope. Evaluate corrosion failure.
【０００７】[0007]
【発明が解決しようとする課題】これまで述べたよう
に、ＣＶＤ装置を用いてウェーハ上にＣＶＤ膜を形成す
る場合、デポジション膜厚の総計が一定値以上になる
と、弗素原子を有する反応ガスを用い、プラズマ・ドラ
イ・エッチング法により、反応室内のクリーニングを行
なう。しかしクリーニング後に、反応室内に弗素原子が
残存し、プレ・デポジション後のウェーハ・デポジショ
ン膜に弗素原子が存在する。例えばＣＶＤ膜をＰ−Ｓi
Ｏ膜とすると、Ｐ−Ｓi Ｏ膜には弗素原子が含有され、
この膜上に形成されるＡl 配線の弗素腐食不良を発生
し、問題となっている。As described above, when forming a CVD film on a wafer by using a CVD apparatus, when the total deposition film thickness exceeds a certain value, a reaction gas containing fluorine atoms is formed. And the inside of the reaction chamber is cleaned by plasma dry etching. However, after cleaning, fluorine atoms remain in the reaction chamber, and fluorine atoms exist in the wafer deposition film after pre-deposition. For example, a CVD film is made of P-Si
Assuming an O film, the P-SiO film contains fluorine atoms,
Fluorine corrosion failure of the Al wiring formed on this film occurs, which is a problem.
【０００８】本発明は、ＣＦ4 、Ｃ2 Ｆ6 、ＣＨＦ3 、
ＳＦ6 、ＮＦ3 など弗素（Ｆ）原子を含む反応ガスを用
い、反応室内をプラズマ・ドライ・エッチングによりク
リーニングするＣＶＤ装置において、該クリーニング後
の反応室内に残存する弗素量を低減し、これにより、例
えばウェーハ上のＰ−Ｓi ＯやＰ−Ｓi Ｎ等のＣＶＤ膜
中に含有される弗素量を低減し、Ａl 配線の弗素腐食の
発生がなく、より信頼性の高いＣＶＤ膜が得られるプラ
ズマ・クリーニング後処理方法を提供することを目的と
する。The present invention relates to CF 4 , C 2 F 6 , CHF 3 ,
In a CVD apparatus in which a reaction gas containing fluorine (F) atoms such as SF 6 and NF 3 is used to clean the reaction chamber by plasma dry etching, the amount of fluorine remaining in the reaction chamber after the cleaning is reduced. A plasma that reduces the amount of fluorine contained in a CVD film such as P-SiO or P-SiN on a wafer, does not cause fluorine corrosion of Al wiring, and provides a more reliable CVD film. -To provide a post-cleaning treatment method.
【０００９】[0009]
【課題を解決するための手段】本発明は、半導体基板上
にＣＶＤ膜を形成するＣＶＤ装置の反応室内を、弗素原
子を有する反応ガスを用いてプラズマ・ドライ・エッチ
ング法でクリーニングした後、弗素原子を取り込む被膜
を該反応室内に被覆することを特徴としたプラズマ・ク
リーニング後処理方法である。According to the present invention, the inside of a reaction chamber of a CVD apparatus for forming a CVD film on a semiconductor substrate is cleaned by a plasma dry etching method using a reaction gas containing fluorine atoms, and then the fluorine is removed. This is a post-treatment method for plasma cleaning characterized by coating a coating film for incorporating atoms into the reaction chamber.
【００１０】なお上記プラズマ・ドライ・エッチング法
は、反応ガスプラズマを利用し、気相中で、反応室内面
等に付着するＣＶＤ膜をエッチングする方法である。The plasma dry etching method is a method of utilizing a reactive gas plasma to etch a CVD film adhering to the inner surface of the reaction chamber or the like in the vapor phase.
【００１１】[0011]
【作用】本発明では、プラズマ・ドライ・エッチング法
でクリーニングした後の後工程として、弗素原子を取り
込む被膜を反応室内に被覆する工程を、新しく設けたこ
とが特徴である。すなわち弗素原子を取り込む被膜は、
物理的または化学的作用を弗素原子に及ぼし、該原子を
捕獲、固着することのできる被膜であり、この被膜を反
応室内（反応室内面のほか、電極面等を含む）に被覆す
る工程により、反応室内に残存する弗素原子は、該被膜
に捕獲拘束されるので、ウェーハ上に形成されるＣＶＤ
膜中の弗素含有量は大幅に低減される。これによりＡl
配線の弗素腐食不良等を防止した信頼性の高いＣＶＤ膜
の形成が容易にできる。The present invention is characterized by newly providing a step of coating the reaction chamber with a film incorporating fluorine atoms as a post-process after cleaning by the plasma dry etching method. That is, the film that incorporates fluorine atoms is
A film capable of exerting a physical or chemical action on a fluorine atom to trap and fix the atom, and by the step of coating this film in the reaction chamber (including the reaction chamber surface, the electrode surface, etc.), Fluorine atoms remaining in the reaction chamber are captured and restrained by the coating film, so that the CVD formed on the wafer.
The fluorine content in the film is greatly reduced. This makes Al
It is possible to easily form a highly reliable CVD film that prevents the fluorine corrosion failure of the wiring.
【００１２】[0012]
【実施例】本発明の実施例について、図面を参照して、
以下説明する。Embodiments of the present invention will be described with reference to the drawings.
This will be described below.
【００１３】図１は、該実施例において、プレ・デポジ
ション後の反応室内を示すプラズマＣＶＤ装置の断面図
である。該装置は、ロードロック室２８を有するコール
ドウォール型プラズマＣＶＤ装置である。ステンレスス
チール２２ａで囲まれた反応室２２内には、ヒーター内
蔵の上部電極（Ａl ）２３及び該電極に対向する下部電
極（Ａl ）２４が設けられる。ＲＦ電源（周波数 400 k
Hz）２３ａからの高周波電力により電極間にプラズマが
誘起される。反応ガスは、ガスインレット２５より反応
室２２内に供給され、排気口２６より排出される。符号
２３ｂは、ヒータ電源、符号２７及び２９は、ロードロ
ック室２８のそれぞれ排気口及びＮ2 ガスを導入するベ
ントライン（vent line ）である。FIG. 1 is a sectional view of a plasma CVD apparatus showing the reaction chamber after pre-deposition in the embodiment. The apparatus is a cold wall type plasma CVD apparatus having a load lock chamber 28. An upper electrode (Al) 23 with a built-in heater and a lower electrode (Al) 24 facing the electrode are provided in a reaction chamber 22 surrounded by stainless steel 22a. RF power supply (frequency 400 k
Plasma is induced between the electrodes by the high frequency electric power from (Hz) 23a. The reaction gas is supplied into the reaction chamber 22 through the gas inlet 25 and exhausted through the exhaust port 26. Reference numeral 23b is a heater power source, and reference numerals 27 and 29 are an exhaust port of the load lock chamber 28 and a vent line for introducing N 2 gas, respectively.
【００１４】符号２０は、プラズマ・ドライ・エッチン
グ後に形成したプラズマＳi 膜、符号２１は、厚さ約 1
μm のプレ・デポジション膜（Ｐ−Ｓi Ｏ膜）である。Reference numeral 20 indicates a plasma Si film formed after plasma dry etching, and reference numeral 21 indicates a thickness of about 1
It is a .mu.m pre-deposition film (P-SiO film).
【００１５】次にこのＣＶＤ装置を用いて、ウェーハ上
にＰ−Ｓi Ｏ膜を形成するデポジション／クリーニング
・サイクルルについて図２（ａ）を参照して説明する。Next, a deposition / cleaning cycle for forming a P-SiO film on a wafer using this CVD apparatus will be described with reference to FIG.
【００１６】プレ・デポジション工程後、ウェーハ・デ
ポジション工程を行なう。ウェーハ上にデポジションし
た膜厚の総計が30μm となるまで、この工程を続ける。
条件は反応ガスに、Ｓi Ｈ4 ／Ｎ2 Ｏ系を用い、ガス流
量はＳi Ｈ4 ＝150 sccm、Ｎ2 Ｏ＝2200sccm、反応室内
の圧力0.40Torr、ＲＦパワー 2.3 kＷ、温度 300℃であ
る。After the pre-deposition process, the wafer deposition process is performed. Continue this process until the total film thickness deposited on the wafer reaches 30 μm.
The conditions are as follows: Si H 4 / N 2 O system is used as the reaction gas, gas flow rate is Si H 4 = 150 sccm, N 2 O = 2200 sccm, pressure in the reaction chamber is 0.40 Torr, RF power is 2.3 kW, and temperature is 300 ° C. ..
【００１７】次にプラズマ・ドライ・エッチング法によ
り反応室内のプラズマ・クリーニングを行なった。条件
は、反応ガスＣ2 Ｆ6 ／Ｏ2 、流量 600／70sccm、圧力
0.25Torr、ＲＦパワー 2.8 kＷ、温度 300℃、オーバー
エッチ40％である。Next, plasma cleaning of the reaction chamber was performed by the plasma dry etching method. Conditions are reaction gas C 2 F 6 / O 2 , flow rate 600/70 sccm, pressure
0.25 Torr, RF power 2.8 kW, temperature 300 ° C, overetch 40%.
【００１８】プラズマ・クリーニング後、弗素原子を取
り込む被膜としてプラズマＳi 膜２０を反応ガスＳi Ｈ
4 、流量 200sccm、圧力0.35Torr、ＲＦパワー 1.3 k
Ｗ、温度 300℃の条件で、反応室内に厚さ 0.1μm 被覆
し、デポジション／クリーニング・サイクルルを完了す
る。After the plasma cleaning, the plasma Si film 20 is used as a film for taking in fluorine atoms and the reaction gas Si H is used.
4 , flow rate 200sccm, pressure 0.35Torr, RF power 1.3k
Under the conditions of W and temperature of 300 ° C., the reaction chamber is coated with a thickness of 0.1 μm, and the deposition / cleaning cycle is completed.
【００１９】その後、再び 1.0μm のＰ−Ｓi Ｏ膜２１
のプレ・デポジションを行ない、さらにウェーハ・デポ
ジションを繰り返す。Thereafter, the P-SiO 2 film 21 of 1.0 μm is again formed.
Pre-deposition, and repeat wafer deposition.
【００２０】上記実施例で、ウェーハ上に形成されたＰ
−Ｓi Ｏ膜中の弗素含有量は0.02at％で、従来の2 at％
に比し大幅に低減されている。またこのＰ−Ｓi Ｏ膜上
にＡl 配線（ 1％Ｓi − 0.5％Ｃu −残Ａl ）を形成
し、ＰＣＴ（ 127℃− 2.5kg／cm2 ）で弗素腐食耐性評
価をしたところ、ＰＣＴ 500時間では腐食は発生しなか
った。The P formed on the wafer in the above embodiment
-The fluorine content in SiO2 film is 0.02at%, which is 2at% of the conventional one.
It is greatly reduced compared to. Al wiring (1% Si-0.5% Cu-remaining Al) was formed on this P-SiO film, and fluorine corrosion resistance was evaluated by PCT (127 ° C-2.5kg / cm 2 ). No corrosion occurred.
【００２１】すなわち本実施例においては、弗素原子を
含む反応ガスを使用し、プラズマ・ドライ・エッチング
によるクリーニングをした後、後処理としてプラズマＳ
i 膜を反応室内に被覆する工程を新しく設けたことによ
り、反応室内に残存していた弗素原子は、プラズマＳi
膜に捕獲され拘束されると共に、プラズマＳi 膜形成時
に、残存弗素原子の一部は、励起されたＳi によりガス
化され、反応室外に排出され、ウェーハ上のＣＶＤ膜
（Ｐ−Ｓi Ｏ膜）中の弗素含有量を大幅に低減すること
ができた。That is, in this embodiment, a reactive gas containing fluorine atoms is used, cleaning is performed by plasma dry etching, and then plasma S is used as a post-treatment.
By newly providing the step of coating the i film in the reaction chamber, the fluorine atoms remaining in the reaction chamber are converted into plasma Si.
While being captured and restrained by the film, some of the remaining fluorine atoms are gasified by the excited Si when the plasma Si film is formed and discharged outside the reaction chamber to form a CVD film (P-SiO film) on the wafer. It was possible to significantly reduce the fluorine content therein.
【００２２】次にプラズマ・クリーニング後に形成する
プラズマＳi 膜の膜厚と、ウェーハ上に堆積されるＰ−
Ｓi Ｏ膜中の弗素含有量との関係について調べた。Next, the film thickness of the plasma Si film formed after the plasma cleaning and the P- deposited on the wafer.
The relationship with the fluorine content in the SiO 2 film was investigated.
【００２３】前記実施例と同様のデポジション／クリー
ニング・サイクルルと処理条件で、弗素原子を取り込む
プラズマＳi 膜の膜厚のみを変化させ、Ｐ−Ｓi Ｏ膜を
堆積した複数枚のウェーハを作成した。図３はその結果
を示すもので、横軸は前記プラズマＳi 膜厚（μm ）、
縦軸はＰ−Ｓi Ｏ膜中の弗素含有量（at％）である。同
図からわかるように、クリーニング後にプラズマＳi 膜
を形成しない場合、すなわち従来の方法では、Ｐ−Ｓi
Ｏ膜中の弗素含有量が2.0 at％であったものが、プラズ
マＳi 膜 0.1μm 形成した場合で、 0.02 at％、 0.4μ
m 形成した場合で、 0.01 at％以下となった。この際、
特記すべきことは、プラズマＳi 膜の膜厚が、 0.1μm
以下と薄い領域では、膜厚の増加に伴いＰ−Ｓi Ｏ膜中
の弗素含有量は急速に減少し、プラズマＳi 膜の膜厚
が、 0.1μm を越えると弗素含有量は漸減する。この原
因については十分解明されていないが、弗素原子を取り
込む効果に対し、臨界的な膜厚が存在する。Under the same deposition / cleaning cycle and processing conditions as in the above-mentioned embodiment, only the film thickness of the plasma Si film incorporating fluorine atoms is changed to prepare a plurality of wafers on which the P-SiO film is deposited. did. FIG. 3 shows the results, where the horizontal axis represents the plasma Si film thickness (μm),
The vertical axis represents the fluorine content (at%) in the P-SiO film. As can be seen from the figure, when the plasma Si film is not formed after cleaning, that is, in the conventional method, P-Si film is formed.
The fluorine content in the O film was 2.0 at%, but when the plasma Si film was 0.1 μm, it was 0.02 at%, 0.4 μm.
When m was formed, it was 0.01 at% or less. On this occasion,
It should be noted that the thickness of the plasma Si film is 0.1 μm.
In the thin region below, the fluorine content in the P—SiO 2 film decreases rapidly with increasing film thickness, and when the film thickness of the plasma Si film exceeds 0.1 μm, the fluorine content gradually decreases. Although the cause has not been sufficiently clarified, there is a critical film thickness for the effect of incorporating fluorine atoms.
【００２４】次にこのようにして形成されたＰ−Ｓi Ｏ
膜上にＡl 配線（組成 1％Ｓi − 0.5％Ｃu −残Ａl ）
を形成し、さらに該Ａl 配線を、前記下地Ｐ−Ｓi Ｏ膜
と同じ条件で形成したＰ−Ｓi Ｏ膜で被覆したサンプル
を作製し、ウェーハ状態でのＰＣＴ（ 127℃− 2.5kg／
cm2 ）で弗素腐食耐性評価を行なった。その結果を図４
に示す。同図において、横軸はＰＣＴ時間（hr）、縦軸
は弗素腐食不良率（％）である。同図中、○印は従来の
Ｐ−Ｓi Ｏ膜、△印、□印及び▽印は膜厚が 0.1μm 、
0.4μm 及び0.8 μm のプラズマＳi 膜を被覆する後工
程を行なって形成したＰ−Ｓi Ｏ膜を示す。同図より従
来のＰ−Ｓi Ｏ膜では、ＰＣＴ時間の増加に伴い弗素腐
食不良率も増加するのに対し、プラズマ・クリーニング
後処理をして形成した本発明のＰ−Ｓi Ｏ膜では、 500
時間経過後でも弗素腐食不良は発生しなかった。Next, the P-SiO formed as described above is used.
Al wiring on the film (composition 1% Si-0.5% Cu-remaining Al)
Was formed, and the Al wiring was covered with a P-SiO film formed under the same conditions as the underlying P-SiO film to prepare a sample, and a PCT (127 ° C-2.5 kg /
Fluorine corrosion resistance was evaluated in cm 2 ). The result is shown in Figure 4.
Shown in. In the figure, the horizontal axis is the PCT time (hr) and the vertical axis is the fluorine corrosion failure rate (%). In the figure, ◯ marks are conventional P-SiO films, Δ marks, □ marks and ▽ marks are film thicknesses of 0.1 μm,
The P-SiO film | membrane formed by performing the post process which covers 0.4 micrometer and 0.8 micrometer plasma Si film | membrane is shown. As can be seen from the figure, in the conventional P-SiO film, the fluorine corrosion defect rate increases with the increase of the PCT time, whereas in the P-SiO film of the present invention formed by the plasma cleaning post-treatment, the defect rate is 500%.
Even after the lapse of time, no defective fluorine corrosion occurred.
【００２５】図３及び図４に示す結果より、弗素原子を
取り込む被膜がプラズマＳi 膜の場合には、その膜厚を
0.1μm 以上にすることが望ましい。From the results shown in FIG. 3 and FIG. 4, when the film that takes in fluorine atoms is a plasma Si film, the film thickness is changed.
It is desirable to make it 0.1 μm or more.
【００２６】本発明の対象となるＣＶＤ装置は、プラズ
マＣＶＤ装置以外の例えばＬＰＣＶＤ装置等であって
も、ＣＦ4 、Ｃ2 Ｆ6 、ＳＦ6 、ＮＦ3 等少なくとも 1
つ以上の弗素原子を有するガスを主体に、プラズマ・ド
ライ・エッチングによるクリーニングを実施する装置で
あればよい。Even if the CVD apparatus which is the object of the present invention is, for example, an LPCVD apparatus other than the plasma CVD apparatus, at least one of CF 4 , C 2 F 6 , SF 6 , NF 3, etc.
Any device may be used as long as it is a device that performs cleaning by plasma dry etching mainly using a gas having three or more fluorine atoms.
【００２７】また反応室内に残存する弗素原子を取り込
む被膜として、本実施例ではプラズマＳi 膜としたが、
これに限定されない。例えば炭素（Ｃ）被膜であって
も、またＡl 等の金属被膜であってもよい。さらに形成
されるＳi 膜はプラズマ法以外の、例えばシランガスの
熱分解などの方法で形成されてもよい。Further, in the present embodiment, a plasma Si film was used as the film for taking in the fluorine atoms remaining in the reaction chamber.
It is not limited to this. For example, it may be a carbon (C) coating or a metal coating such as Al. Further, the Si film to be formed may be formed by a method other than the plasma method, such as thermal decomposition of silane gas.
【００２８】また本実施例ではＣＶＤ膜としてＰ−Ｓi
Ｏ膜を例示したが、Ｐ−Ｓi Ｏ膜以外のＳi Ｎ膜などの
絶縁膜、ポリシリコン膜、あるいはＷ等の金属膜であっ
てもよい。In this embodiment, P-Si is used as the CVD film.
Although the O film is exemplified, an insulating film such as a Si N film other than the P—SiO 2 film, a polysilicon film, or a metal film such as W may be used.
【００２９】[0029]
【発明の効果】これまで詳述したように、弗素原子を有
する反応ガスを用いて、ＣＶＤ装置の反応室内をプラズ
マ・ドライ・エッチングによりクリーニングするＣＶＤ
装置において、該クリーニング後、弗素原子を取り込む
被膜を反応室内に形成する工程を、前記クリーニングの
後処理工程として新設したことにより、反応室内に残存
する弗素は該被膜に捕獲固着され、これによりウェーハ
上のＰ−Ｓi ＯやＰ−Ｓi Ｎ等のＣＶＤ膜中に含有され
る弗素量を大幅に低減できた。すなわち本発明により、
例えばＡl 配線の弗素腐食の発生がなく、より信頼性の
高いＣＶＤ膜が得られるプラズマ・クリーニング後処理
方法を提供することができた。As described in detail above, the CVD method is used for cleaning the reaction chamber of the CVD apparatus by plasma dry etching using the reaction gas containing fluorine atoms.
In the apparatus, the step of forming a coating film for incorporating fluorine atoms after the cleaning in the reaction chamber is newly provided as a post-treatment step for the cleaning, so that the fluorine remaining in the reaction chamber is captured and fixed to the coating film. The amount of fluorine contained in the above CVD films such as P-SiO and P-SiN could be greatly reduced. That is, according to the present invention,
For example, it is possible to provide a plasma cleaning post-treatment method which does not cause fluorine corrosion of Al wiring and can obtain a more reliable CVD film.
【図１】本発明のプレ・デポジション後の反応室内を示
すプラズマＣＶＤ装置の断面図である。FIG. 1 is a sectional view of a plasma CVD apparatus showing a reaction chamber after pre-deposition according to the present invention.
【図２】同図（ａ）及び（ｂ）はそれぞれ本発明及び従
来例のデポジション／クリーニング・サイクルルのフロ
ー図である。2A and 2B are flow charts of a deposition / cleaning cycler of the present invention and a conventional example, respectively.
【図３】Ｐ−Ｓi Ｏ膜中の弗素含有量と弗素原子を取り
込むプラズマＳi 膜厚の関係を示す図である。FIG. 3 is a diagram showing a relationship between a fluorine content in a P—Si 2 O 3 film and a film thickness of plasma Si which takes in fluorine atoms.
【図４】従来及び本発明の弗素腐食不良率とＰＣＴ時間
との関係を示す図である。FIG. 4 is a diagram showing a relationship between a fluorine corrosion defect rate and a PCT time according to the related art and the present invention.
【図５】ＰＣＴによる弗素腐食耐性評価のサンプルの断
面図である。FIG. 5 is a cross-sectional view of a sample for evaluation of fluorine corrosion resistance by PCT.
【図６】従来のプレ・デポジション後の反応室内を示す
プラズマＣＶＤ装置の断面図である。FIG. 6 is a cross-sectional view of a plasma CVD apparatus showing a conventional reaction chamber after pre-deposition.
２０ 弗素原子を取り込む被膜 １１，２１ プレ・デポジション膜 １２，２２ 反応室 １３，２３ 上部電極 １３ａ，２３ａ ＲＦ電源 １３ｂ，２３ｂ ヒータ電源 １４，２４ 下部電極 １５，２５ ガス・インレット １６，２６ 反応室排気口 １７，２７ ロードロック室排気口 １８，２８ ロードロック室 １９，２９ ベントライン 20 Films that incorporate fluorine atoms 11,21 Pre-deposition film 12,22 Reaction chamber 13,23 Upper electrodes 13a, 23a RF power supply 13b, 23b Heater power supply 14,24 Lower electrode 15,25 Gas inlet 16,26 Reaction chamber Exhaust port 17,27 Load lock chamber Exhaust port 18,28 Load lock chamber 19,29 Vent line
Claims (1)
装置の反応室内を、弗素原子を有する反応ガスを用いて
プラズマ・ドライ・エッチング法でクリーニングした
後、弗素原子を取り込む被膜を該反応室内に被覆するこ
とを特徴としたプラズマ・クリーニング後処理方法。1. A CVD method for forming a CVD film on a semiconductor substrate.
A plasma cleaning post-treatment method characterized in that the reaction chamber of the apparatus is cleaned by a plasma dry etching method using a reaction gas containing fluorine atoms, and then a coating film incorporating fluorine atoms is coated in the reaction chamber.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09027592A JP3150408B2 (en) | 1992-03-16 | 1992-03-16 | Plasma cleaning post-processing method for CVD equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09027592A JP3150408B2 (en) | 1992-03-16 | 1992-03-16 | Plasma cleaning post-processing method for CVD equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05259083A true JPH05259083A (en) | 1993-10-08 |
| JP3150408B2 JP3150408B2 (en) | 2001-03-26 |
Family
ID=13993970
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP09027592A Expired - Fee Related JP3150408B2 (en) | 1992-03-16 | 1992-03-16 | Plasma cleaning post-processing method for CVD equipment |
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| Country | Link |
|---|---|
| JP (1) | JP3150408B2 (en) |
Cited By (12)
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|---|---|---|---|---|
| JPH07326589A (en) * | 1993-12-28 | 1995-12-12 | Applied Materials Inc | Single chamber cvd process for thin film transistor |
| JPH0831750A (en) * | 1994-07-15 | 1996-02-02 | Toshiba Corp | Coating of reaction chamber of cvd system |
| WO1997023663A1 (en) * | 1995-12-22 | 1997-07-03 | Lam Research Corporation | A plasma cleaning method for removing residues in a plasma process chamber |
| US5843838A (en) * | 1995-12-27 | 1998-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Modified clean recipe to suppress formation of BPSG bubble |
| JP2000200786A (en) * | 1999-01-04 | 2000-07-18 | Toshiba Corp | Forming method of insulating film |
| JP2001291716A (en) * | 1999-12-14 | 2001-10-19 | Applied Materials Inc | Method of reducing unnecessary etching of insulator due to increase in boron concentration |
| JP2004111983A (en) * | 2003-10-27 | 2004-04-08 | Toshiba Corp | Method for coating reaction chamber in cvd apparatus |
| WO2004086482A1 (en) * | 2003-03-25 | 2004-10-07 | Tokyo Electron Limited | Method for cleaning thin-film forming apparatus |
| US7271082B2 (en) | 1993-10-26 | 2007-09-18 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
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1992
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Cited By (15)
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|---|---|---|---|---|
| US7271082B2 (en) | 1993-10-26 | 2007-09-18 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US8304350B2 (en) | 1993-10-26 | 2012-11-06 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US7452794B2 (en) | 1993-10-26 | 2008-11-18 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of a thin film semiconductor device |
| US7691692B2 (en) | 1993-10-26 | 2010-04-06 | Semiconductor Energy Laboratory Co., Ltd. | Substrate processing apparatus and a manufacturing method of a thin film semiconductor device |
| JPH07326589A (en) * | 1993-12-28 | 1995-12-12 | Applied Materials Inc | Single chamber cvd process for thin film transistor |
| JPH0831750A (en) * | 1994-07-15 | 1996-02-02 | Toshiba Corp | Coating of reaction chamber of cvd system |
| WO1997023663A1 (en) * | 1995-12-22 | 1997-07-03 | Lam Research Corporation | A plasma cleaning method for removing residues in a plasma process chamber |
| US5843838A (en) * | 1995-12-27 | 1998-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Modified clean recipe to suppress formation of BPSG bubble |
| JP2000200786A (en) * | 1999-01-04 | 2000-07-18 | Toshiba Corp | Forming method of insulating film |
| JP2001291716A (en) * | 1999-12-14 | 2001-10-19 | Applied Materials Inc | Method of reducing unnecessary etching of insulator due to increase in boron concentration |
| JP2012089886A (en) * | 2002-11-11 | 2012-05-10 | Hitachi Kokusai Electric Inc | Manufacturing method of semiconductor device |
| WO2004086482A1 (en) * | 2003-03-25 | 2004-10-07 | Tokyo Electron Limited | Method for cleaning thin-film forming apparatus |
| JP2004111983A (en) * | 2003-10-27 | 2004-04-08 | Toshiba Corp | Method for coating reaction chamber in cvd apparatus |
| JP2008240034A (en) * | 2007-03-26 | 2008-10-09 | Mitsubishi Heavy Ind Ltd | Vacuum treatment apparatus and operation method of the same |
| US8529704B2 (en) | 2008-06-27 | 2013-09-10 | Mitsubishi Heavy Industries, Ltd. | Vacuum processing apparatus and operating method for vacuum processing apparatus |
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