JPH05258579A - Associative memory device - Google Patents

Abstract

PURPOSE:To provide extendability of a memory with a low cost, a high speed and higher integration by bypassing a logical operation circuit while making first a control signal active in coincidence retrieval. CONSTITUTION:First the control signal C is inputted to a control signal line 42 as active and a through transistor Tr 40 is turned on. Then, coincidence retrieval of data to be retrieved is carried out in a CAM memory array at every memory word. The signal state of a coincidence retrieval line 30 for the memory word with the coincident content is changed to be H and the state of the retrieval line 30 is changed to be L for the discordant memory word. Since the Tr 40 is turned on, the coincident retrieval signal is passed through the Tr 40 and directly inputted to a data latching circuit 34 through an AND gate 38. When the circuit 34 receives a clock signal from a clock terminal CLK, the circuit latches an input signal from the input terminal D and then outputs the latched signal at an output terminal Q.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an associative memory device capable of searching data according to contents, and more specifically,
For expanding the bit width per word of the associative memory,
The present invention relates to an associative memory device having a more efficient structure.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory circuit having a function of performing a match detection of search data and stored data in parallel for all bits and outputting a stored address or data of the matched data, an associative memory, that is, a complete semiconductor memory circuit. Parallel CAM (Content Access Memory: Content
Addressable Memory is well known (edited by Takuo Sugano, edited by Tetsuya Iizuka, “Design of CMOS VLSI,” Baifukan, P.
176-P177).

The associative memory is searched by content rather than by physical memory address. Each memory cell that constitutes the associative memory includes a 1-bit memory, like other memories, and has a predetermined number of bits.
A memory word is organized. In a CAM memory match search, multiple memory words in the CAM memory are stored in a series of
It is compared in parallel with a known search pattern (search data pattern) consisting of data bits. When a match is detected, the physical address of the cell containing the matched data is determined. The main advantage of a CAM memory is that a full memory match search is performed quickly in the time it takes to perform a substantially one word search.

Many conventional associative memories are limited to a specific memory width by their design and cannot be expanded by cascading the memories. Therefore, such a CAM memory is limited in the number of bits for a given word to some maximum value, for example 16 bits, and search data patterns larger than 16 bits for this CAM memory will not be reliably searched for, which is why There was a problem that its usage was also limited.

Some conventional CAM memories are designed so that they can be searched for a match only with a fixed length search data pattern. However, this has the problem that no match search can be performed at all with variable length search data patterns.

For this reason, a device for expanding the bit width of the associative memory is proposed in Japanese Patent Publication No. 63-5839 as "memory width expanding device for associative memory". As shown in FIG. 5, the conventional bit width expansion device 100 disclosed herein includes circuits 102, 104a, 104b, ... Which output a match signal for each memory word of a CAM memory array.
, And the first word circuit 102 has the match search line 10
6. The second word circuit 104a has a latch circuit 108 to which 6 is directly input, and the second word circuit 104a outputs the AND of the output of the latch circuit 108 in the preceding stage and the match search line 110a of the second word and the output. A latch circuit 114a for latching a logical product. .. and the latch circuits 11 in the same manner as the circuit 104a for the second word.
4b, and these circuits 102, 104a,
104b, ... Are cascade-connected.

When performing a match search in this device 100, first, the latch circuits 108, 1 provided for each memory word by the initialization signal from the signal line 116.
14a, 114b, ... Are all initialized, and AND gates 112a, 112b ,.
The output signal initialized by ... and the match search lines 110a, 110b, ... of the next memory word are ANDed to determine the match search signal of each memory word as the final match search signal. Was output as. here,
When the bit width is expanded, a logical product of the previous match search signal and the current match search signal, which are also latched, is taken to finally obtain the match search signal with the expanded bit width. .. That is, for example, assuming that the CAM memory is an 8-bit cell, 16-bit search data is found to be a coincident search when the type-2 8-bit search data is continuously searched twice. 2 times 8
Latch circuit 114 after matching search of bit search data
When the output signals a, 114b, ... Are coincidence signals, the 8-bit cell of the memory word from which the coincidence signal is output and the 8-bit cell of the memory word immediately before that are 16 in total.
It has been detected that the memory data of the bit memory cell matches the above 16-bit search data. In this way, the bit width is expanded by repeating the match search of the search data of a predetermined bit and detecting the match signal from the latch circuit.

[0008]

By the way, in the bit width expansion device 100 disclosed in Japanese Patent Publication No. 63-5839 shown in FIG. 5, the latch circuit 1 for each memory word is used.
Since 08, 114a, 114b, ... All need to have a latch configuration with an initialization function (set function),
There is a problem that the circuit area increases and the hardware cost increases. Also, when performing a match search, all latch circuits 1 provided for each memory word must be
08, 114a, 114b, ... Initialize (set)
However, there is a problem in that it takes time to perform the set process. In particular, such various problems have been problems in high integration.

An object of the present invention is to solve the above problems of the prior art and to provide an associative memory device having a low-cost, high-speed and highly integrated memory width expanding function.

[0010]

In order to achieve the above object, the present invention provides a memory word, a match search circuit for detecting match between memory data of the memory word and search data, and a match search circuit for the match search circuit. A first logic function circuit and a second logic function circuit having an output as a common input;
And a search result data latch circuit having a common output of the second logic function circuit as an input, and a plurality of match search units, and a first one of the plurality of match search units.
Between the first unit and the second unit, the output of the search result data latch circuit of the first unit constitutes the input of the first logic function circuit of the second unit, and the first unit.
And a control signal input means for activating at least one of the logic function circuit and the second logic function circuit.

Here, it is preferable that the control signal input means is a means for inputting a control signal for exclusively activating the first logic function circuit and the second logic function circuit.

The first logic function circuit of the second unit is a logical product of the output of the search result data latch circuit of the first unit and the output of the match search circuit of the second unit. It is preferable that

The second logic function circuit preferably has one input and one output.

That is, the associative memory device of the present invention is provided for at least one memory word, and outputs a match search signal between the memory data of this memory word and the search data for each memory word. A search line, a composite gate provided for each of the match search lines and having the match search line as an input, and a data latch circuit for latching an output signal of the composite gate, and the composite gate as an output, It is configured to select one of the match search line input and the logical operation output of the match search line input and the output from the data latch circuit connected to the composite gate adjacent to the one side.

The associative memory device of the present invention is provided for at least one memory word, and outputs a match search signal between the memory data of this memory word and the search data for each memory word. A search line, a composite gate provided for each of the match search lines, which is controlled by at least control signals A and C with the match search line as an input, and a data latch circuit which latches an output signal of the composite gate. The output of the data latch circuit is sequentially connected so as to be input as the control signal A of the composite gate adjacent to one side, and the plurality of composite gates are connected to the control signal line for inputting the control signal C. And whether the control signal A is a coincidence signal or the control signal C is
Is active, the composite gate outputs its input signal, and when the control signal A is inconsistent and the control signal C is inactive, it is configured to output an inconsistency signal. Here, it is preferable that the coincidence search line is provided for each memory word.

[0016]

The search result of the search result data latch circuit of the first unit is input to the first logic function circuit of the second unit, whereby the logic of the search result of the second unit and the output of the coincidence search circuit of the second unit is obtained. Calculation is possible.

When it is not desired to perform the operation by the first logic function circuit, the search result data latch of the first unit is activated by activating the second logic function circuit which is exclusively activated by the control signal. The influence of the output value of the circuit can be eliminated.

By using the first logical function circuit as a logical product circuit, the logical product of the search results of the first unit and the second unit can be obtained.

Furthermore, by setting the second logic function circuit to have one input and one output, the output of the match search circuit of the first or second unit can be directly input to the search result data latch circuit.

That is, in the associative memory device of the present invention, when performing a match search of search data, first, at least the control signal C is set to "active" to control the composite gates, and all the data latch circuits have their respective memory words. The match search signal from the match search line is latched as it is. That is, by activating the control signal "C", the composite gate bypasses the logical operation circuit by the bypass means and outputs the match search signal input from the match search line as it is. At this time, it is preferable to inactivate the output of the logical operation circuit of the composite gate because the match search signal and the output signal of the logical operation circuit do not completely collide. The match search signal output from the composite gate as it is is latched by the data latch circuit. When the match search of the search data with the expanded bit width is not performed, this signal is output as the final match search signal.

On the other hand, when the bit width is to be expanded, the control signal C is then set to "inactive" and the match search signal latched in the data latch circuit of the memory word of the previous stage is set to the memory word of the current stage. If the composite signal is controlled as the control signal A, and the control signal A is the coincidence signal, the coincidence search signal by the next search data is latched as it is, and then output as the coincidence search signal. For example, after latching this, a mismatch signal is output. That is, after the logical operation of the control signal A (the match search signal of the previous stage by the previous search data) and the match search signal of the next search data of this memory word, for example, the logical product is taken, the result is latched. And outputs it as a match search signal. If necessary, it is further repeated and output as a match search signal with the final bit width expanded.

In the associative memory device of the present invention, when searching for a match, the control signal C is first made "active" to bypass the logical operation circuit, and preferably its output is made inactive to perform a logical operation, for example, a logical operation. Since the initialization by the latch with the set function in the conventional device can be made unnecessary by simply passing through the multiplication function, it is possible to realize the high-speed and highly integrated memory width expansion function at low cost. You can

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An associative memory device according to the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a conceptual diagram showing the construction of an embodiment of the associative memory device of the present invention. FIG. 2 is a schematic configuration diagram of an embodiment of a bit width expansion device used in the associative memory device shown in FIG.

As shown in FIG. 1, an associative memory device (CAM memory) 10 of the present invention comprises a CAM memory array 12,
It includes a data and mask drive block 14, an address decoder 16, a match detection circuit block 20 including a match search circuit and a bit width expansion device 18, which is the most characteristic feature of the present invention, and an address encoder 22. The CAM memory 10 has a memory mode that operates similarly to a memory such as a RAM or ROM and a mode that performs a match search. Here, for simplification of description, a case where a match search line is provided for each memory word of the CAM memory array 12 will be described below as a typical example, but the present invention is not limited to this. ..

First, in the normal memory mode, an arbitrary address in the CAM memory array 12 is designated by the address decoder 16, and the content of the address is read or written via the data and mask drive block 14. At this time, the bit width expansion device 18, the match detection circuit block 20, and the address encoder 22 are not driven.

Next, in the match search mode, a mask signal for designating a bit position to be a match search target and search data are input from the data and mask drive block 14. At this time, the content of each memory word of the CAM memory array 12, that is, the memory data of the memory cell at each bit position is compared. As described above, in the example shown in FIG. 1, the CAM memory array 12 has one memory word for each memory word.
A match search line for books is provided. The signal state (“1” H (high) or “0” L (low)) of the match search line causes the match of the search data (search data pattern) with respect to the content (memory data pattern) of the memory word. Here, a match signal when a match typically occurs is indicated by “1” (H (high)), and a mismatch signal when there is a mismatch is “0” (L (low)). ), But of course the reverse is also possible.

Next, the bit width expansion device 18, which is the most characteristic of the present invention, will be described in detail later, but if the bit width expansion is not performed, the above-mentioned coincidence signal ("1") or non-coincidence signal ("0"). ), Either match search signal is simply passed through and output as it is.
The match signal H (“1”) is output only when the search data and the memory data match with respect to the expanded bit width, and the others are configured to output the mismatch signal L (“0”). ..

Next, the match detection circuit block 20 includes a plurality of match detection circuits and a bit width expansion device 18, each of which receives a search result of a match search line of each memory word.
A match signal (“1”) corresponding to the lowest address among the matched addresses is output. When the bit width is expanded by the bit width expansion device 18, the memory word address immediately above may be sequentially output. This signal is input to the address encoder 22, and the lowest address (or the memory word address of the higher order if the bit width is expanded) in which a match has occurred is determined. Here, when the coincidence search line is provided for each memory word, it is not necessary to use the address decoder 16 in particular, but it is not necessary to use one for a plurality of memory words.
When one match search line is provided, it is preferable that the address decoder 16 selects a memory word address for which a match search is performed.

The bit width expansion device 18 shown in FIG.
A match search line 30 (30 ₁ , 30) provided for each memory word having a predetermined bit width (memory width) composed of memory cells of predetermined bits of the CAM memory array 10 shown in FIG.
₂ , 30 ₃ , ...), composite gates 32 (32 ₁ , 32 ₂ , 32 ₃ , ...) respectively connected to these, and search result data latch circuit 3 respectively connected to these
4 (34 ₁ , 34 ₂ , 34 ₃ , ...) And these output lines 36 (36 ₁ , 36 ₂ , 36 ₃ , ...).
The compound gate 32 (32 ₁ , 32 ₂ , 32 ₃ , ...)
AND gates 38 (38 ₁ , 38 ₂ , 38 ₃ respectively constituting the logical operation circuit which is the first logical function circuit of the present invention.
, ...) and through transistors 40 which form the second logic function circuit of the present invention by passing these through.
(40 ₁ , 40 ₂ , 40 ₃ , ...). Here, the through transistor 40 constitutes a bypass means for outputting the input signal to the composite gate 32 as it is by bypassing the AND gate 38 which is a logical operation circuit. Here, the memory word of the CAM memory array 12 and the match search line 30 (30 ₁ , 30 connected to this memory word
₂ , 30 ₃ , ...), a match search circuit, a composite gate 32 (32 ₁ , 32 ₂ , 32 ₃ , ...), and a search result data latch circuit 34 (34 ₁ , 34 ₂ , 34 ₃ , ...). …)
And constitute the matching search unit of the present invention.

Here, the control signal line 42 for inputting the control signal C has all the through transistors 40 (40
₁ , 40 ₂ , 40 ₃ , ...) are connected to the gate electrodes. In addition, the data latch circuit 34 (34 ₀ , 34
The output signal from the output terminal Q of ₁ , 34 ₂ , ...) Is used as the control signal A, and the composite gate 32 (3
2 ₁ , 32 ₂ , 32 ₃ , ... AND gate 38 (3
8 ₁ , 38 ₂ , 38 ₃ , ...), the signal line 44 (44 ₁ ) branched from each output terminal Q of the data latch circuit 34 (34 ₁ , 34 ₂ , 34 ₃ , ...). , 44
₂ , 44 ₃ , ...) are AND gates 38 (38 ₁ , 38).
₂ , 38 ₃ , ...) are connected to the input terminals. AN
The other input terminal of the D gate 38 is connected to the match search line 30 of each memory word. The output of the AND gate 38 is connected to the input terminal D of the data latch circuit 34. Here, the AND gate 38 has a row active control terminal, and this terminal is connected to the control signal C. The data latch circuit 34 also has a clock input terminal CLK to which a clock for latching is supplied.

Next, the operation of the bit width expansion device 18 shown in FIG. 2 will be described. First, the control signal C is set to “active” (“1” H (high)) and the control signal line 42.
Input to the through transistor 40 (40 ₁ , 40
₂ , 40 ₃ , ...) are turned on. At this time, conversely AND
Since "1" H (high) is supplied to the low-active control terminal of the gate 38, the AND gate 38 becomes inactive.

Therefore, a match search for the first portion of the search data (pattern) is performed in the CAM memory array 12 for each memory word. For example, assuming that the CAM memory device 10 of the present invention is an 8-bit wide device, the first 8 bits of search data (pattern) are used for a match search.

For the first part of the search data, contents (memo)
Memory of the CAM memory array 12 having the same
The signal state of the match search line 30 for the word is H
(“1”), and a match search line for unmatched memory words
The signal state of 30 becomes L (“0”). Where thru
Transistor 40 (40₁ , 40₂ , 40₃ , ……)
Since it is turned on, the match search signal on the match search line 30 is
Through transistor 40 (40 ₁ , 40₂ , 40₃ , ...
...) and the AND gate 38 (38₁ , 38
₂ , 38₃ , ……) through and data latch circuit directly
34 (34₁ , 34₂ , 34₃ , ……) is entered.
That is, the composite gate 32 (32₁ , 32₂ , 32₃ ,
......) allows the match search signal to pass through as it is. Day
Taratch circuit 34 (34₁ , 34₂ , 34₃ , ……)
Input when receiving a clock signal from clock terminal CLK
After latching the input signal from terminal D, output terminal Q
Output the latched signal. Where each memory word
The result of the match search is H, L, L, ... From the first memory word.
Then, the latch circuit 34₁ , 34₂ , 34₃ 
The data that is latched in ... is exactly the same H, L, L, ...
Is ...

Here, when the search data is 8 bits or less and there is no second part of the search data pattern, the latched data H, L, L, ... Is output, and in the upper three memory words, It can be seen that only the first memory word matched. If the search data is 9 bits or more, the search data has a second portion, and then a match search is performed for this portion. For example, the 8-bit CAM described above
In the case of memory, 16-bit search data, bits 9 to 16 form search data for the next match search. Prior to the next match search, inactive (“0” L (low)) is input to the control signal line 42 as the control signal C, and the through transistors 40 (40 ₁ , 40 ₂ , 40 ₃ , ...).
…) Are all turned off. On the contrary, the AND gate 38 having the row active control terminal is activated.

The CAM memory device 10 executes the next match search and uses the result as a match search signal for each word memory in the match search lines 30 (30 ₁ , 30 ₂ , 30 ₃ , ...).
...). Since the through transistors 40 are all off, the match search signal on the match search line 30 is input to one input terminal of the AND gate 38. On the other hand, the latch data of the latch circuit 34 at the previous stage is input as the control signal A to the other input terminal of the AND gate 38.
The gate 38 takes the logical product of the control signal A and the coincidence search signal and outputs the result.

Here, if the control signal A input to the AND gate 38 is the coincidence signal H ("1"), the logical product is determined by the coincidence search signal input from the other. That is, in this case, the logical product, that is, the output of the composite gate 32 is L if the match search signal is L (mismatch) and H if H (match). On the other hand, when the control signal A is the disagreement signal L (“0”), the logical product, that is, the output of the composite gate 32 becomes L (disagreement) regardless of the signal state of the coincidence search signal.

In this way, the AND gate 38 (38
_1, 38 _2, signals outputted from ...) is input to the data latch circuit 34 (34 _1, 34 _2, ...), the data latch circuit 34 receives the clock signal from the clock terminal CLK, input terminal After latching the input signal from D, the latched signal is output from the output terminal Q. Here, the data latch circuit 34 is configured to receive a clock during each match search. Here, as described above, the result of the match search of the first portion of the search data is H, L, L in the upper three memory words, and therefore the signal state of the control signal A is also H, L, L. Therefore, if the result of the match search of the second portion of the search data is L, H, and H in the upper 3 memory words, the composite gate 32
The outputs of ₁ , 32 ₂ , 32 ₃ are L, H, L, and the output lines 36 ₁ , 3 of the data latch circuits 34 ₁ , 34 ₂ , 34 ₃ are output.
L 2, H and L are also output from 6 ₂ and 36 ₃ . That is, H (match signal) is output only to the second memory word. At this time, the above-mentioned 16-bit search data is the first
It can be seen that the 8 bits of the memory word and the 8 bits of the second memory word are in agreement with the total 16 bits of memory data.

As described above, the search data of M × N bits in the memory having the N-bit width is achieved by M times of matching searches, that is, within M clock cycles input to the data latch circuit.

Next, more detailed circuit diagrams of another specific embodiment of the bit width expanding device used in the associative memory device of the present invention are shown in FIGS. 3, 4 and 5.

The bit width expansion device 18 shown in FIG.
It is an example of a specific circuit diagram for realizing a bit width expanding function similar to that of the bit width expanding device 18 shown in FIG. 1, and the same components are designated by the same reference numerals and the description thereof will be omitted. Here, a sense amplifier 48 with a precharge transistor 46 for precharging the match search line 30 (30 ₁ , 30 ₂ , 30 ₃ , ...) Is attached to each of the match search lines 30. Match (H) and mismatch (L) between the memory data and the search data of the memory cells succeeding each memory word of the CAM memory array connected to
Are in control.

Here, the sense amplifier 48 is the inverter 4
7 and inverts the signal on the match search line 30 and returns the inverted signal to the gate of the P-channel transistor that constitutes the sense amplifier 48. If the match search result is match (H), this N-channel transistor is selected. When turned on, it has the capability of self-driving so that the potential of the coincidence search line 30 is surely kept at H (high: “1”) and the inversion potential is kept at L (low: “0”). Also, each match search line 30 (3
0 ₁ , 30 ₂ , 30 ₃ , ...) Inverted outputs of the respective inverters 47 connected to the transmission line 31 of the match search result.
It is input to the composite gate 32 (32 ₁ , 32 ₂ , 32 ₃ , ...) Via (31 ₁ , 31 ₂ , 31 ₃ , ...).
In the illustrated example, the precharge transistor 46 is also a P-channel transistor.

The composite gate 32 (32 ₁ , 32 ₂ , 32 ₃ , ...) Of the bit width expansion device 18 in the illustrated example is the transmission line 3
1 (31 ₁ , 31 ₂ , 31 ₃ , ...), the input signal (inverted signal) of the match search result and the output line 36.
(36 ₀ , 36 ₁ , 36 ₂ ...) And the control signal line 44.
Latch circuits 34 (34 ₀ , 34 ₁ , 34 ₂ , ...) Transmitted by (44 ₀ , 44 ₁ , 44 ₂ , ...)
...) and performs a logical operation with the control signal A and outputs the result as a composite gate output.
₁ , 39 ₂ , 39 ₃ , ...) and this logical operation circuit 39
(39 ₁ , 39 ₂ , 39 ₃ , ...) Bypass transistors 40 (40 ₁ , 40 ₂₎ forming bypass means for bypassing the input signal (inverted signal) of the match search result as it is as a composite gate output. , 40 ₃ , ......)
And a transistor 5 connected to the output side of the logical operation circuit
0 (50 ₁ , 50 ₂ , 50 ₃ , ...). Here, the transistors 50 (50 ₁ , 50 ₂ , 50
₃ , ...), all the gate electrodes are control signal lines 52.
And is controlled by the control signal B. Here, the through transistors 40 (40 ₁ , 40 ₂ , 40 ₃ , ...
...) and transistors 50 (50 ₁ , 50 ₂ , 50)
₃ , ...) are all N-channel MOS transistors.

Further, each representative logic operation circuit 39 will be described by way of a representative example. A transistor 49 connected to the transmission line 31, a transistor 54 connected to the output side of the transistor 49, and a serial connection to the transistor 54. And a transistor 55 having the other electrode connected to a predetermined H (high) potential power supply. Here, the transistor 49 is composed of an N-channel MOS transistor (hereinafter, referred to as NMOS) like the through transistor 40 and the transistor 50, the control signal line 44 is connected to the gate electrode of the transistor 49, and the control signal line 44 is output from the previous stage data latch circuit 34. The control signal A transmitted by the line 36 and the control signal line 44 is input. Also transistor 4
9 is connected in parallel with the through transistor 40. The transistors 54 and 55 connected in series are both P-channel MOS transistors (hereinafter referred to as PMOS). The gate electrode of the transistor 54 is connected to the control signal line 44 and controlled by the control signal A described above. Here, the transistors 49 and 54 controlled by the same control signal A have opposite polarities, and one of them is on (O
In the case of N), the other is always off. The gate electrode of the transistor 55 is connected to the control signal line 42 and is controlled by the control signal C that controls the through transistor 40. However, the transistor 55 and the through transistor 40 have opposite polarities and one of them is turned on. , The other is turned off. An output connection end of the transistor 49 and the through transistor 40 connected in parallel is connected to one electrode of the transistor 50, and a transistor serially connected to the transistor 55 between them (between the output connection end and the transistor 50). The output terminals of 54 are connected.

In the bit width expansion device 18 shown in FIG. 3, as described above, the composite gate 32 (32 ₁ , 32 ₂ ,
32 ₃ , ...) are transistors 50 (50 ₁ , 50 ₂ , 50 ₃ , ...) Controlled by the control signal B on the output terminal side.
,), The gate electrodes of all the transistors 50 are connected to one control signal line 52, and the composite gate 3
The timing at which the signal from 2 (match signal H or mismatch signal L) is output to the data latch circuit 34 is controlled. Therefore, in the bit width expansion device 18, the control signals B and C are at least "active" at the time of a match search of search data at the beginning or less than the device memory width.
It is necessary to set it to (“1”), and the control signal B is active (“1”) at the time of matching search for the second part of the search data.
The control signal C needs to be inactive (“0”). In this way, the composite gate 32 is connected to the three control signals A,
It may be controlled by B and C, and it is the main point of the present invention that the first match search result is passed through for bit width expansion. The composite gate 32 of the bit width expansion device 18 shown in FIG. 3 is basically configured as described above.

In the bit width expansion device 18 shown in FIG. 3, the data latch circuit 34 includes two inverters 56 and 57 connected in parallel in opposite directions and an N-channel MOS transistor provided on the output end side thereof. 58
Composed of and. Output line 36 of data latch circuit 34
Are two inverters 5 connected in parallel in opposite directions.
Data holding circuits 6 and 57 are connected in parallel. All the latch circuits 34 (34 ₁ , 34 ₂ , 3
4 ₃ , ...) are all connected to a control signal line 59 to which a clock signal CLK is input, and a data latch is provided every time a clock signal CLK (pulse signal H (high) is input. The latch data latched in the circuit 34 is output as the control signal A. Here, the data latch circuit 34 in the illustrated example holds the input signal in the inverters 56 and 57 connected in parallel, and inverts the control signal A. That is, the match search signal inverted by the sense amplifier 48 is inverted by the data latch circuit 34 again.

The operation of the bit width expansion device 18 shown in FIG. 3 will be described. First, at the time of matching search for the first part of the search data, the control signals B and C are active (“1”: H).
(High)). Therefore, in the compound gate 32 of the bit width expanding device 18 for all words, the through transistor 40 and the transistor 50 are turned on and the transistor 5 is turned on.
5 is turned off. Here, the match search signal (H (“1”: match)) or L (“0” :) of the match search line 30.
(Inconsistency)) is inverted by the inverter 47, and becomes an inverted match search signal (“1”: mismatch or “0”: match) on the transmission line 31. When the coincidence signal “0” or the non-coincidence signal “1” is input to the composite gate 32 through the transmission line 31, it passes through the through transistor 40 that is turned on and performs a logical operation regardless of the signal state of the control signal A. Circuit 3
9 is bypassed, and is output from the composite gate 32 through the transistor 50 as it is. Here, compound gate 3
The inverted match search signal (“0”: match or “1”: mismatch) output from 2 enters the data latch circuit 34 and is latched according to the signal state. Here, if the search data is only the first portion, the transistor 58 is turned on by the input of the clock signal CLK, and the inverted match search signal (“0”: mismatch or “1”: match) is output line 36. Output to the outside.

Next, when the second part of the search data exists and the second part is searched for a match following the first part, the control signal B is in the "1" (active) state, and the control signal C is "." It is set to 0 ”(inactive). Here, the through transistor 40 is turned off and the transistor 55 is turned on. At this time, when the transistor 58 is turned on by the input of the clock signal CLK, the re-inverted match search signal (“0”: no match, or “1”: match) of the first part of the search data changes to the word of the previous stage. Data latch circuit 3
4 through the control signal line 44, and the control signal A is input to the logical operation circuit 39 of the composite gate 32.

If the control signal A is "1" (H) indicating the matching of the first portion of the search data, the transistor 49
Is turned on and the transistor 54 is turned off, so that the inverted match search signal (“0”: match or “1”: mismatch) of the second portion of the search data input to the composite gate 32 causes the transistors 49 and 50 to be turned on. As it is, it is output from the composite gate 32 as it is, is latched by the data latch circuit 34, is inverted again by the next clock signal CLK,
A match search signal (“0”: mismatch or “1”: match) is output to the outside. At this time, when the match signal "1" is output from the output line 36 of the data latch circuit 34, both the first part and the second part of the search data: that is, the search data having the expanded bit width match. Can be detected.

On the other hand, if the control signal A is "0" (L) indicating that the search data do not match, the transistor 49 is turned off and the transistor 54 is turned on. Therefore, even if the inverted match search signal of the second portion of the search data is input to the composite gate 32 via the match search line 30, the sense amplifier 48, and the transmission line 31, the through transistor 40 also
Since the transistor 49 of the logical operation circuit 39 is also off, it cannot pass through. That is, the output of the logical operation circuit 39 is inactivated. On the other hand, transistors 54 and 55
Are turned on, the output side of the logical operation circuit 39 is held at H (high) potential, and the mismatch signal “1” output from the logical operation circuit 39 passes through the transistor 50 controlled by the control signal B. , Output from the composite gate 32,
It is latched by the data latch circuit 34. When the clock signal CLK is input, the inverted mismatch signal “0” is output from the output line 36 to the outside. That is,
If the control signal A is "0", the bit width expansion device 18 in the illustrated example has a mismatch in the first part of the search data, and therefore a mismatch signal "0" regardless of the match search result of the second part of the search data. "Is output from the data latch circuit 34 to the outside. As described above, the search operation may be repeated if the search data has a longer bit width.

Next, the bit width expansion device 19 shown in FIG.
Is a bit width expansion device 18 shown in FIG.
Except for the connection position of the through transistor 40 of No. 2, it has the completely same structure, the same number is attached to the same component, and the description thereof is omitted. One electrode of the through transistor 40 shown in FIG. 4 is connected to the input side of the logical operation circuit 39 connected to the transmission line 31 similarly to that shown in FIG. 3, but the other electrode of the through transistor 40 is It is connected to the output side of the transistor 50 controlled by the control signal B. Then, the control signal C and the control signal B are
They are controlled in reverse. Here, the control signal B line 52 is set to AN
When the D signal line is used, the control signal C line 42 can be an anti-AND signal line (AND bar signal line).

In the bit width expansion device 19 shown in FIG. 4, when searching the first part of the search data, the control signal B is made inactive (AND = "0") and the control signal C is made active (anti-AND =). "1"). Therefore, only the through transistor 40 is turned on, the transistor 50 is always turned off, and the output of the logical operation circuit 39 is deactivated. Therefore, even if the control signal A is "1" and the transistor 49 is turned on, the transistor 50 is not turned on at the same time. Therefore, the inverted coincidence search signal passed through the through transistor 40 and the logical operation are performed. The output signal of the circuit 39 and the output signal of the circuit 39 do not collide with each other at the merging point, which does not reduce the processing speed or disturb the processing result.

Bit width expansion device 1 shown in FIGS. 3 and 4.
Since 8 and 19 cause inversion of data in the sense amplifier 48 and the data latch circuit 34, the logical operation function of the logical operation circuit 39 including them is a logical product, as shown in the figure. Any operation is possible as long as it can perform a logical operation, for example, a logical product, between the match search signal of the word match search line and the match search signal output from the previous word data latch circuit. Further, in the bit width expansion device shown in FIGS. 2 to 4, the polarities and configurations of the transistors used as the logical operation circuit, the bypass means and the signal transmission control means and their connections are not limited to those shown in the illustrated example, and the bit width expansion is not limited. If possible, they may be reversed, and improvements and design changes may be made to carry out necessary logical operations.

Although the associative memory device according to the present invention has been described with reference to various modes as the bit width expansion device applied thereto, the present invention is not limited to these and the bit width is not limited thereto. The expansion device is not necessarily limited to one used only between the CAM memory array and the match search block, and may be provided integrally with the match search block or within the match search, which deviates from the gist of the present invention. It goes without saying that various design changes, changes, and replacements are possible without them.

[0055]

As described in detail above, according to the present invention,
Whether the search search is within the device bit width unique to the device or the search search is within the device bit width, the control signal C is set to " In the conventional device, only the logic operation function, for example, the function of taking the logical product is passed as "active", and preferably the other control signal B is made "inactive" to deactivate the logic operation output and allow it to pass. Since the initialization by the latch with the set function can be dispensed with, it is possible to realize the memory width expansion function of high speed and higher integration at low cost.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of an associative memory device according to the present invention.

FIG. 2 is a schematic configuration diagram of an embodiment of a bit width expansion device used in an associative memory device according to the present invention.

FIG. 3 is a configuration diagram of another embodiment of a bit width expansion device used in the associative memory device according to the present invention.

FIG. 4 is a configuration diagram of another embodiment of a bit width expansion device used in the associative memory device according to the present invention.

FIG. 5 is a configuration diagram of a bit width expansion device of a conventional associative memory device.

[Explanation of symbols]

10 associative memory device 12 associative memory array 14 data and mask drive block 16 address decoder 18, 19, 60 bit width expansion device 20 match detection circuit block 22 address encoder 30, 30 ₁ , 30 ₂ , 30 ₃ match search line 31, 31 ₁ , 31 ₂ , 31 ₃ signal transmission line 32, 32 ₁ , 32 ₂ , 32 ₃ composite gate 34, 34 ₀ , 34 ₁ , 34 ₂ , 34 ₃ data latch circuit 62, 62 ₁ , 62 ₂ , 62 ₃ data latch Circuits 36, 36 ₀ , 36 ₁ , 36 ₂ , 36 ₃ Output lines 38, 38 ₁ , 38 ₂ , 38 ₃ AND gates 39, 39 ₁ , 39 ₂ , 39 ₃ Logical operation circuits 40, 40 ₁ , 40 ₂ , 40 ₃ through transistor 42, 52, 59 control signal line 44, 44 ₁ , 44 ₂ , 44 ₃ control signal line 46 precharge transistor 47, 56, 5 7 Inverter 48 Sense Amplifier 49, 54, 55, 58, Transistor 50, 50 ₁ , 50 ₂ , 50 ₃ Transistor

Claims (4)

[Claims] 1. A memory word, a match search circuit for performing match detection between memory data of this memory word and search data, a first logic function circuit and a second logic function circuit having an output of this match search circuit as a common input. There is provided a plurality of match search units each having a logic function circuit and a search result data latch circuit having a common output of the first and second logic function circuits as an input. Between the first unit and the second unit, the output of the search result data latch circuit of the first unit serves as the input of the first logic function circuit of the second unit, and the first logic function circuit. And a control signal input means for activating at least one of the logic function circuit and the second logic function circuit. 2. The associative memory according to claim 1, wherein said control signal input means is means for inputting a control signal for exclusively activating each of said first logic function circuit and said second logic function circuit. apparatus. 3. The first logical function circuit of the second unit is a logical product of an output of the search result data latch circuit of the first unit and an output of the coincidence search circuit of the second unit. The associative memory device according to claim 1, wherein 4. The associative memory device according to claim 1, wherein the second logic function circuit has one input and one output.