JP2728824B2 - Associative memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an associative memory device capable of performing a data search according to contents.
For expanding the bit width per word of the associative memory,
The present invention relates to an associative memory device having a more efficient configuration.

[0002]

2. Description of the Related Art Conventionally, an associative memory, that is, an associative memory, has been used as a semiconductor memory circuit having a function of detecting coincidence between search data and stored data in parallel with all bits and outputting a storage address or data of the matched data. Parallel CAM (Content access memory: Content
Addressable Memory is well known (Takuo Sugano, supervised by Tetsuya Iizuka, "Design of CMOS Ultra LSI" Baifukan, P.
176-P177).

[0003] Associative memories are searched by content, not by physical memory address. Each of the memory cells constituting the associative memory includes a 1-bit memory, like the other memories, and has a 1-bit memory with a predetermined number of bits.
A memory word is configured. In a CAM memory match search, the memory words in the CAM memory are a series of,
It is compared in parallel with a known search pattern consisting of data bits (search data pattern). When a match is detected, the physical address of the cell containing the matched data is determined. A major advantage of CAM memories is that a full memory match search is performed quickly, substantially in the time required to perform a one word search.

Many conventional associative memories are limited by design to a specific memory width, and cannot be expanded by cascading the memories. Therefore, such a CAM memory is limited in the number of bits for a given word to a certain maximum value, for example, 16 bits, and a search data pattern larger than 16 bits for this CAM memory is not reliably searched for, so that There is a problem that its use is also restricted.

[0005] Some conventional CAM memories are designed so that a match search can be performed only with a fixed-length search data pattern. However, this has a problem that a match search cannot be performed at all with a variable-length search data pattern.

For this reason, a device for expanding the bit width of an associative memory has been proposed in Japanese Patent Publication No. 63-5839 as a "memory width expanding device of an associative memory". As shown in FIG. 5, the conventional bit width expansion device 100 disclosed here outputs circuits 102, 104a, 104b,... For outputting a match signal for each memory word of the CAM memory array.
.., And the first word circuit 102
6 is directly input, and the second word circuit 104a is provided with an AND gate 112a for outputting a logical product of the output of the preceding latch circuit 108 and the second word match search line 110a, and the output And a latch circuit 114a for latching a logical product. The third and subsequent circuits 104b,..., And the AND gates 112b,.
4b, and these circuits 102, 104a,
Are connected in cascade.

When a match search is performed in the device 100, first, a latch circuit 108, 1 provided for each memory word is provided by an initialization signal from a signal line 116.
.. Are initialized, and after the second memory word, AND gates 112a, 112b,.
The logical product of the output signal initialized by... And the match search lines 110a, 110b,... Of the next memory word is converted to the final match search signal of each memory word. Was output as. here,
When the bit width is expanded, a logical AND of the previous match search signal and the current match search signal, which are similarly latched, is used to finally obtain a match search signal whose bit width is expanded. . That is, for example, if the CAM memory is an 8-bit cell, if two types of 8-bit search data are successively searched for twice, the 16-bit search data will be matched. Twice 8
Latch circuit 114 after match search of bit search data
When the output signals of a, 114b,... are coincidence signals, a total of 16 bits of the 8-bit cell of the memory word from which the coincidence signal was output and the 8-bit cell of the memory word immediately before the same.
It has been detected that the memory data of the bit memory cell matches the above-mentioned 16-bit search data. In this manner, the bit width is extended by repeating the match search of the search data of the predetermined bit and detecting the match signal from the latch circuit.

[0008]

In the bit width expansion device 100 disclosed in Japanese Patent Publication No. 63-5839 shown in FIG. 5, a latch circuit 1 for each memory word is provided.
08, 114a, 114b,... Must all be latched with an initialization function (set function).
There is a problem that a circuit area increases and hardware cost increases. When a match search is performed, all the latch circuits 1 provided for each memory word must be used.
08, 114a, 114b,... Are initialized (set)
And the setting process requires time. In particular, such various problems have been a problem in high integration.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide an associative memory device having a low-cost, high-speed, and highly integrated memory width extending function.

[0010]

To achieve the above object of the Invention The present invention includes a memory word, a matching search circuit for performing coincidence detection of the memory data and the search data for the memory word, the matching search circuit Logical operation between output and other input
A first logic function circuit for performing an output of the matching search circuit
A second bypass output to the output of the first logic function circuit;
, And a plurality of match search units each having a search result data latch circuit that latches a common output of the first and second logic function circuits. Between the first unit and the second unit, the output of the search result data latch circuit of the first unit forms the other input of the first logic function circuit of the second unit, and the first logic It is an object of the present invention to provide a content addressable memory device characterized by having control signal input means for exclusively activating a functional circuit and the second logical functional circuit.

[0011]

Further, the first logic function circuit of the second unit is a logical product of an output of the search result data latch circuit of the first unit and an output of the match search circuit of the second unit. Is preferable.

Preferably, the second logic function circuit has one input and one output.

That is, the associative memory device of the present invention is provided for at least one memory word, and outputs a match search signal between the memory data of the memory word and the search data for each memory word. A search line, having this match search line as input, having a composite gate provided for each match search line, and a data latch circuit for latching an output signal of the composite gate, wherein the composite gate has as an output One of the match search line input and a logical operation output of the match search line input and an output from a data latch circuit connected to a composite gate adjacent to one side is configured to be selected.

Further, the associative memory device of the present invention is provided for at least one memory word, and outputs a match search signal between the memory data of the memory word and the search data for each memory word. A search line, a composite gate which receives the match search line as an input, and is provided at least for each of the match search lines and is controlled by at least control signals A and C, and a data latch circuit which latches an output signal of the composite gate. The output of the data latch circuit is sequentially connected to one side so as to be input as a control signal A of the adjacent composite gate, and the plurality of composite gates are connected to a control signal line for inputting the control signal C. And whether the control signal A is a coincidence signal or the control signal C
Is active, the composite gate outputs its input signal, and is configured to output a mismatch signal when the control signal A is mismatched and the control signal C is inactive. Here, it is preferable that the match search line is provided for each memory word.

[0016]

The search result of the first unit search result data latch circuit is used as the input of the first logic function circuit of the second unit, so that the logic of the second unit with the output of the match search circuit of the second unit is obtained. Calculation becomes possible.

If the operation by the first logic function circuit is not desired to be performed, the second logic function circuit exclusively activated by the control signal is activated to operate the search result data latch of the first unit. The influence of the output value of the circuit can be eliminated.

By using the first logical function circuit as an AND circuit, the logical product of the search results of the first unit and the second unit can be obtained.

Further, the output of the match search circuit of the first or second unit can be directly input to the search result data latch circuit by making the second logic function circuit one input and one output.

That is, in the associative memory device of the present invention, when performing a match search of search data, first, at least the control signal C is set to "active" to control the composite gate, and all data latch circuits are provided with each memory word. The match search signal from the match search line is latched as it is. That is, by activating the control signal "C", the composite gate causes the logic operation circuit to be bypassed by the bypass means therein, and outputs the match search signal input from the match search line as it is. At this time, it is preferable to inactivate the output of the logical operation circuit of the composite gate because the match search signal does not completely collide with the output signal of the logical operation circuit. The match search signal output as it is from the composite gate is latched by the data latch circuit. When a match search is not performed on the search data having the extended bit width, the signal as it is is output as a final match search signal.

On the other hand, when the bit width is to be expanded, the control signal C is set to "inactive" next, and the match search signal latched in the data latch circuit of the preceding memory word is used as the control signal C. If the control signal A controls the composite gate and the control signal A is a match signal, the match search signal based on the next search data is latched as it is and then output as a match search signal. For example, after latching this, a mismatch signal is output. That is, after performing a logical operation between the control signal A (a match search signal at the previous stage based on the previous search data) and a match search signal of the next search data of this memory word, for example, a logical product is obtained, and the result is latched. And outputs it as a match search signal. If necessary, it is repeated to output a match search signal having a final bit width expanded.

In the associative memory device of the present invention, when searching for a match, the control signal C is first set to "active" to bypass the logical operation circuit. By simply passing through the multiplication function, the initialization by the latch with the set function in the conventional device can be made unnecessary, thereby realizing a low-cost, high-speed, highly integrated memory width extension function. Can be.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The associative memory device according to the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a conceptual diagram showing the configuration of an embodiment of an associative memory device according to the present invention. FIG. 2 is a schematic configuration diagram of one embodiment of a bit width expansion device used in the content addressable memory device shown in FIG.

As shown in FIG. 1, an associative memory device (CAM memory) 10 of the present invention includes a CAM memory array 12,
It includes a match detection circuit block 20 including a data and mask drive block 14, an address decoder 16, a match search circuit, and a bit width expansion device 18 which is the most characteristic of the present invention, and an address encoder 22. The CAM memory 10 has a memory mode that performs the same function as a memory such as a RAM or a ROM, and a mode that performs a match search. Here, for the sake of simplicity, a case where a match search line is provided for each memory word of the CAM memory array 12 will be described below as a representative example, but the present invention is not limited to this. .

First, in a normal memory mode, an arbitrary address in the CAM memory array 12 is designated by the address decoder 16, and reading or writing of the content of the address is performed via the data and mask driving block 14. At this time, the bit width expansion device 18, the coincidence detection circuit block 20, and the address encoder 22 are not driven.

Next, in the match search mode, the data and mask drive block 14 receives a mask signal specifying search target bit positions and search data. At this time, the contents of each memory word of the CAM memory array 12, that is, the memory data of the memory cell at each bit position are compared. As described above, in the example shown in FIG. 1, the CAM memory array 12 has one memory word for each memory word.
A number of match search lines are provided. The signal state (“1” H (high) or “0” L (low)) of the match search line indicates that the search data (search data pattern) matches the content of the memory word (memory data pattern). Here, typically, a match signal when a match occurs is indicated by “1” (H (high)), and a mismatch signal when there is a mismatch is “0” (L (low)). ), But of course the reverse is also possible.

Next, the bit width expansion device 18 which is the most characteristic of the present invention will be described later in detail. When the bit width expansion is not performed, the above-mentioned match signal ("1") or mismatch signal ("0") ) Is simply passed through and output as it is. To expand the bit width,
The match signal H ("1") is output only when the search data matches the memory data with respect to the expanded bit width, and the other signals are output with the mismatch signal L ("0"). .

Next, the match detection circuit block 20 includes a plurality of match detection circuits each receiving a search result of a match search line of each memory word and a bit width expansion device 18,
A match signal ("1") corresponding to the lowest address among the addresses where the match has occurred is output. When the bit width is expanded by the bit width expansion device 18, the immediately higher memory word address may be sequentially output. This signal is input to the address encoder 22, and the lowest address (or, if the bit width is expanded, the higher memory word address) is determined. Here, when a match search line is provided for each memory word, it is not necessary to use the address decoder 16 in particular.
When two match search lines are provided, it is preferable to select a memory word address for performing a match search by the address decoder 16.

The bit width expansion device 18 shown in FIG.
A match search line 30 (30 ₁ , 30) provided for each memory word having a predetermined bit width (memory width) composed of memory cells of predetermined bits of the CAM memory array 10 shown in FIG.
_2, 30 _3, and ...), composite gate 32 (32 ₁ to be connected thereto, 32 _2, 32 _3, ...) and the search result data latch circuit 3 which is connected thereto
4 (34 _1, 34 _2, 34 _3, ...) has a, these output lines 36 (36 _1, 36 _2, 36 _3, ...) and a.
The composite gate 32 (32 ₁ , 32 ₂ , 32 ₃ ,...)
Each of the AND gates 38 (38 ₁ , 38 ₂ , 38 ₃₎ constituting the logical operation circuit serving as the first logical function circuit of the present invention
,...), And through transistors 40 through which constitute the second logic function circuit of the present invention.
(40 ₁ , 40 ₂ , 40 ₃ ,...). Here, the through transistor 40 constitutes a bypass unit that bypasses the AND signal 38, which is a logical operation circuit, and outputs the input signal to the composite gate 32 as it is. Here, the memory words of the CAM memory array 12 and the match search lines 30 (30 ₁ , 30 ₁₎ connected to the memory words
_2, 30 _3, and matching search circuit including a ...), the composite gate 32 (32 _1, 32 _2, 32 _3, and ...), the search result data latch circuit 34 (34 _1, 34 _2, 34 _3, ... …)
Constitute the match search unit of the present invention.

Here, the control signal line 42 for inputting the control signal C is connected to all the through transistors 40 (40
_1, 40 _2, 40 ₃ is connected to the gate electrode of ...). Further, the data latch circuit 34 (34 ₀ , 34
₁ , 34 ₂ ,...) As a control signal A, the composite gate 32 (3
The AND gates 38 (3, 32 ₁ , 32 ₂ , 32 ₃ ,...)
8 ₁ , 38 ₂ , 38 ₃ ,...), The signal line 44 (44 ₁ ) branched from each output terminal Q of the data latch circuit 34 (34 ₁ , 34 ₂ , 34 ₃ ,...). , 44
₂ , 44 ₃ ,...) Are AND gates 38 (38 ₁ , 38).
₂ , 38 ₃ ,...). AN
The other input terminal of the D gate 38 is connected to the match search line 30 of each memory word. The output of the AND gate 38 is connected to the input terminal D of the data latch circuit 34. Here, the AND gate 38 has a row active control terminal, and this terminal is connected to the control signal C. The data latch circuit 34 has a clock input terminal CLK to which a clock for latch is supplied.

Next, the operation of the bit width extending device 18 shown in FIG. 2 will be described. First, the control signal C is set to “active” (“1” H (high)) and the control signal line 42
To the through transistor 40 (40 ₁ , 40
₂ , 40 ₃ ,...) Are turned on. At this time, AND
Since "1" H (high) is supplied to the low active control terminal of the gate 38, the AND gate 38 is in an inactive state.

Therefore, a match search for the first portion of the search data (pattern) is performed in the CAM memory array 12 for each memory word. For example, if the CAM memory device 10 of the present invention is an 8-bit wide device, the first 8 bits of the search data (pattern) are used for a match search.

For the first part of the search data, the contents (memo
Memory of the CAM memory array 12 whose redata) matches
The signal state of the match search line 30 for the word is H
("1") and the match search line for the unmatched memory word
The signal state of L30 is L ("0"). Where through
Transistor 40 (40₁ , 40_Two , 40_Three , ……) is
Since it is on, the match search signal of the match search line 30 is:
Through transistor 40 (40 ₁ , 40_Two , 40_Three …
..) And the AND gate 38 (38₁ , 38
_Two , 38_Three , ……) through the data latch circuit directly
34 (34₁ , 34_Two , 34_Three , ......).
That is, the composite gate 32 (32₁ , 32_Two , 32_Three ,
...) Allows the match search signal to pass through as it is. Day
Taratch circuit 34 (34₁ , 34_Two , 34_Three , ……) is
When receiving a clock signal from the clock terminal CLK, the input
After latching the input signal from terminal D,
Outputs the latched signal. Where each memory word
Match search results are H, L, L,... From the first memory word.
, The latch circuit 34₁ , 34_Two , 34_Three 
The data latched in... Are exactly the same H, L, L,.
...

Here, if the search data is 8 bits or less and there is no second part of the search data pattern, the latched data H, L, L,... Are output, and in the upper three memory words, It can be seen that only the first memory word matched. If the search data is 9 bits or more, a second portion exists in the search data, and then a match search of this portion is performed. For example, the above-mentioned 8-bit CAM
In the case of memory, 16-bit search data, bits 9 to 16 constitute search data for the next match search. Prior to the next match search, an inactive signal (“0” L (low)) is input to the control signal line 42 as the control signal C, and the through transistors 40 (40 ₁ , 40 ₂ , 40 ₃ ,.
…) Are all turned off. Conversely, an AND gate 38 having a row active control terminal is activated.

The CAM memory device 10 executes the next match search, and uses the result as a match search signal for the match search lines 30 (30 ₁ , 30 ₂ , 30 ₃ ,...) For each word memory.
…). Since the through transistors 40 are all off, the match search signal of the match search line 30 is input to one input terminal of the AND gate 38. On the other hand, to the other input terminal of the AND gate 38, the latch data of the preceding latch circuit 34 is input as the control signal A.
Gate 38 takes the logical product of control signal A and the match search signal, and outputs the result.

Here, if the control signal A input to the AND gate 38 is the coincidence signal H ("1"), its logical product is determined by the coincidence search signal input from the other. That is, in this case, the logical product, that is, the output of the composite gate 32 is L when the match search signal is L (mismatch) and H when the match search signal is H (match). On the other hand, when the control signal A is the mismatch signal L ("0"), the logical product thereof, that is, the output of the composite gate 32 becomes L (mismatch) regardless of the signal state of the match search signal.

Thus, the AND gate 38 (38
_1, 38 _2, signals outputted from ...) is input to the data latch circuit 34 (34 _1, 34 _2, ...), the data latch circuit 34 receives the clock signal from the clock terminal CLK, input terminal After latching the input signal from D, the latched signal is output from the output terminal Q. Here, the data latch circuit 34 is configured to receive a clock during each match search. Here, as described above, the result of the match search of the first portion of the search data is H, L, and L in the upper three memory words, and thus the signal states of the control signal A are H, L, and L. Therefore, if the result of the match search of the second part of the search data is L, H, H in the upper three memory words, the composite gate 32
_1, 32 _2, 32 ₃ output of L, H, L, and the data latch circuit 34 _1, 34 _2, 34 ₃ of the output lines 36 _1, 3
6 _2, 36 L from _3, H, L is output. That is, H (coincidence signal) is output only to the second memory word. At this time, the 16-bit search data described above
It can be seen that the data coincided with a total of 16 bits of memory data, that is, 8 bits of the memory word and 8 bits of the second memory word.

As described above, the search data of M × N bits in the memory having the N-bit width is achieved by the M-times matching search, that is, within the M clock cycles input to the data latch circuit.

Next, FIGS . 3 and 4 show more detailed circuit diagrams of another specific embodiment of the bit width expansion device used in the content addressable memory device of the present invention.

The bit width extending device 18 shown in FIG.
Is an embodiment of a specific circuit diagram for realizing a bit width extension function similar to that of the bit width extension device 18 shown in FIG. 1, and the same components are denoted by the same reference numerals and description thereof will be omitted. Each of the match search lines 30 (30 ₁ , 30 ₂ , 30 ₃ ,...) Is provided with a sense amplifier 48 with a precharge transistor 46 for precharging the match search lines 30. (H), mismatch (L) between the memory data of the memory cell connected to each memory word of the CAM memory array connected to the memory cell and the search data
Is controlling.

Here, the sense amplifier 48 is connected to the inverter 4
7, the signal of the match search line 30 is inverted, and the inverted signal is returned to the gate of the P-channel transistor constituting the sense amplifier 48. If the match search result is match (H), the N-channel transistor is changed to It is capable of self-driving so as to be turned on to reliably maintain the potential of the match search line 30 at H (high: "1") and maintain the inversion potential at L (low: "0"). Also, each match search line 30 (3
0 ₁ , 30 ₂ , 30 ₃ ,...) Are output from the transmission line 31 of the match search result.
Are input to the composite gate 32 (32 ₁ , 32 ₂ , 32 ₃ ,...) Via (31 ₁ , 31 ₂ , 31 ₃ ,...).
In the illustrated example, the precharge transistor 46 is also formed of a P-channel transistor.

The composite gate 32 (32 ₁ , 32 ₂ , 32 ₃ ,...) Of the bit width expansion device 18 shown in FIG.
1 (31 ₁ , 31 ₂ , 31 ₃ ,...) And the input signal (inverted signal) of the match search result and the output line 36
(36 ₀ , 36 ₁ , 36 ₂ ...) and the control signal line 44
(44 ₀ , 44 ₁ , 44 ₂ ,...) Transmitted by the preceding stage latch circuit 34 (34 ₀ , 34 ₁ , 34 ₂ ,...).
) Perform a logical operation on the control signal A and output the result as a composite gate output.
₁ , 39 ₂ , 39 ₃ ,...)
(39 ₁ , 39 ₂ , 39 ₃ ,...) Are bypassed, and the through transistors 40 (40 ₁ , 40 ₂₎ constituting bypass means for outputting the input signal (inverted signal) of the match search result as a composite gate output as it is. , 40 _3, ...)
And a transistor 5 connected to the output side of the logical operation circuit
0 (50 ₁ , 50 ₂ , 50 ₃ ,...). Here, the transistor 50 (50 ₁ , 50 ₂ , 50
₃ ,...) Indicate that all of the gate electrodes are control signal lines 52.
And is controlled by a control signal B. Here, the through transistors 40 (40 ₁ , 40 ₂ , 40 ₃ ,...)
..) And transistors 50 (50 ₁ , 50 ₂ , 50)
_3, ...) consists of all N-channel MOS transistor.

To explain one typical example, each of the logical operation circuits 39 includes a transistor 49 connected to the transmission line 31, a transistor 54 connected to the output side of the transistor 49, and a series connected to the transistor 54. And a transistor 55 whose other electrode is connected to a predetermined H (high) potential power supply. Here, the transistor 49 is formed of an N-channel MOS transistor (hereinafter, referred to as an NMOS) like the through transistor 40 and the transistor 50, and has a gate electrode connected to the control signal line 44, and an output from the data latch circuit 34 in the preceding stage. The control signal A transmitted by the line 36 and the control signal line 44 is input. Transistor 4
9 is connected in parallel with the through transistor 40. Each of the transistors 54 and 55 connected in series is configured by a P-channel MOS transistor (hereinafter, referred to as PMOS). The gate electrode of the transistor 54 is connected to the control signal line 44 and is controlled by the control signal A described above. Here, the transistors 49 and 54 controlled by the same control signal A have opposite polarities, and one of them is turned on (O
In the case of N), the other is always turned off (OFF). The gate electrode of the transistor 55 is connected to the control signal line 42 and is controlled by a control signal C for controlling the through transistor 40. The transistor 55 and the through transistor 40 have opposite polarities, and one of them is turned on. , The other is turned off. An output connection end of the transistor 49 and the through transistor 40 connected in parallel is connected to one electrode of the transistor 50, and a transistor connected in series to the transistor 55 between the output connection end (between the output connection end and the transistor 50). 54 output terminals are connected.

In the bit width expansion device 18 shown in FIG. 3, the composite gate 32 (32 ₁ , 32 ₂ ,
32 ₃ ,...) Have transistors 50 (50 ₁ , 50 ₂ , 50 ₃ ,.
..), The gate electrodes of all the transistors 50 are connected to one control signal line 52, and the composite gate 3
2 controls the timing at which the signal (match signal H or mismatch signal L) is output to the data latch circuit 34. Therefore, in the bit width expansion device 18, at the time of the search for the match of the search data initially or less than the memory width of the device, the control signals B and C are at least "active".
(“1”), and the control signal B is also active (“1”) during the match search of the second part of the search data.
The control signal C needs to be inactive ("0"). Thus, the composite gate 32 is connected to the three control signals A,
It may be controlled by B and C, and the main point of the present invention is to pass through the first match search result for bit width expansion. The composite gate 32 of the bit width expansion device 18 shown in FIG. 3 is basically configured as described above.

In the bit width extending device 18 shown in FIG. 3, the data latch circuit 34 includes two inverters 56 and 57 connected in parallel in opposite directions, and an N-channel MOS transistor provided on the output side thereof. 58
It is composed of Output line 36 of data latch circuit 34
Have two inverters 5 connected in parallel in opposite directions.
Data holding circuits 6 and 57 are connected in parallel. All the latch circuits 34 (34 ₁ , 34 ₂ , 3
4 ₃ ,...) Are all connected to a control signal line 59 to which a clock signal CLK is input, and each time a clock signal CLK (pulse signal H (high)) is input, a data latch is provided. The latch data latched by the circuit 34 is output as the control signal A. Here, the data latch circuit 34 in the illustrated example holds the input signal in the inverters 56 and 57 connected in parallel, inverts the input signal, and inverts the control signal A. That is, the match search signal inverted by the sense amplifier 48 is inverted by the data latch circuit 34 again.

The operation of the bit width extending device 18 shown in FIG. 3 will be described. First, at the time of matching search of the first portion of the search data, the control signals B and C are active (“1”: H).
(High)). Therefore, in the composite gate 32 of the bit width expansion device 18 for all words, the through transistor 40 and the transistor 50 are turned on and the transistor 5
5 is turned off. Here, the match search signal (H (“1”: match)) or L (“0”:
Non-coincidence) is inverted by the inverter 47 and becomes an inverted coincidence search signal ("1": non-coincidence or "0": coincidence) on the transmission line 31. When the coincidence signal “0” or the non-coincidence signal “1” is input to the composite gate 32 through the transmission line 31, the logical operation is performed regardless of the signal state of the control signal A through the through transistor 40 which is turned on. Circuit 3
9 and is output from the composite gate 32 through the transistor 50 as it is. Here, composite gate 3
The inverted match search signal (“0”: match or “1”: mismatch) output from 2 enters the data latch circuit 34 and is latched according to the signal state. Here, if the search data is only the first portion, the transistor 58 is turned on by the input of the clock signal CLK, and the inverted match search signal (“0”: mismatch or “1”: match) is again output to the output line 36. Output to the outside.

Next, when a second portion of the search data exists and a match search of the second portion is performed following the first portion, the control signal B is "1" (active) and the control signal C is " 0 "(inactive) state. Here, the through transistor 40 turns off and the transistor 55 turns on. At this time, when the transistor 58 is turned on by the input of the clock signal CLK, the match search signal (“0”: non-match, or “1”: match) of the first part of the search data that has been reinverted is output from the previous word. Data latch circuit 3
4 through a control signal line 44 and is input to the logical operation circuit 39 of the composite gate 32 as a control signal A.

If the control signal A is "1" (H) indicating the match of the first part of the search data, the transistor 49
Turns on and the transistor 54 turns off, the inverted match search signal (“0”: match or “1”: mismatch) of the second part of the search data input to the composite gate 32 causes the transistors 49 and 50 to pass through. As it is, it is output from the composite gate 32 as it is, latched by the data latch circuit 34, inverted again by the next clock signal CLK, and
A match search signal ("0": mismatch or "1": match) is output to the outside. At this time, when the match signal "1" is output from the output line 36 of the data latch circuit 34, both the first portion and the second portion of the search data: that is, the search data having the extended bit width matches. Can be detected.

On the other hand, if the control signal A is "0" (L) indicating that the search data does not match, the transistor 49 is turned off and the transistor 54 is turned on. Therefore, even if the inverted match search signal of the second part of the search data is input to the composite gate 32 via the match search line 30, the sense amplifier 48, and the transmission line 31, the through transistor 40 also
The transistor 49 of the logical operation circuit 39 is also off and cannot pass. That is, the output of the logical operation circuit 39 is inactivated. On the other hand, transistors 54 and 55
Are turned on, the output side of the logical operation circuit 39 is held at the H (high) potential, and the mismatch signal “1” output from the logical operation circuit 39 passes through the transistor 50 controlled by the control signal B. , Output from the composite gate 32,
The data is latched by the data latch circuit 34. In response to the input of the clock signal CLK, the inverted mismatch signal “0” is output from the output line 36 to the outside. That is,
In the illustrated example, if the control signal A is "0", the first portion of the search data does not match, and therefore the mismatch signal "0" is obtained regardless of the matching search result of the second portion of the search data. "Is output from the data latch circuit 34 to the outside. As described above, if the search data has a longer bit width, the above-described search operation may be repeated.

Next, the bit width expansion device 19 shown in FIG.
Is the bit width expansion device 18 shown in FIG.
Except for the connection position of the two through transistors 40, they have exactly the same configuration, and the same components are denoted by the same reference numerals and description thereof will be omitted. One electrode of the through transistor 40 shown in FIG. 4 is connected to the input side of the logical operation circuit 39 connected to the transmission line 31 similarly to the one shown in FIG. 3, but the other electrode of the through transistor 40 is Connected to the output side of transistor 50 controlled by control signal B. Then, the control signal C and the control signal B are
They are controlled opposite to each other. Here, the control signal B line 52 is set to AN
When the control signal C line 42 is a D signal line, the control signal C line 42 can be an anti-AND signal line (AND bar signal line).

In the bit width expansion device 19 shown in FIG. 4, when the first part of the search data is searched, the control signal B is made inactive (AND = "0"), and the control signal C is made active (anti-AND = "1"). Therefore, only the through transistor 40 is turned on and the transistor 50 is always turned off, and the output of the logical operation circuit 39 is inactivated. Therefore, even if the control signal A is "1" and the transistor 49 is turned on, the transistor 50 is not turned on at the same time. The output signal of the circuit 39 does not collide with each other at the confluence point, and does not lower the processing speed or change the processing result at all.

Bit width expansion device 1 shown in FIGS. 3 and 4
The logic circuits 8 and 19 are configured as shown in the illustrated example in which the logical operation function of the logical operation circuit 39 including the data is inverted in the sense amplifier 48 and the data latch circuit 34, and the logical operation function includes the logical inversion. Any logic operation, for example, a logical product of the match search signal of the word match search line and the match search signal output from the data latch circuit of the preceding word can be used. In addition, the polarity and configuration of the transistors used as the logic operation circuit, the bypass unit, and the signal transmission control unit in the bit width expansion device shown in FIGS. 2 to 4 and their connections are not limited to those in the illustrated example. If possible, the reversal may be performed, and an improvement and a design change for performing a necessary logical operation may be performed.

As described above, the associative memory device according to the present invention has been described with various modes as the bit width extending device applied thereto, but the present invention is not limited to these embodiments. The expansion device is not necessarily used only between the CAM memory array and the match search block, and may be provided integrally with the match search block or in the match search. Of course, various design changes, changes, and replacements are possible.

[0055]

As described in detail above, according to the present invention,
Regarding the match search of the search data within the device bit width unique to the device or the match search of the expanded search data larger than the device bit width, the control signal C is first set to “ In the conventional device, only the logic operation function, for example, the function of taking a logical product, is passed through as “active”, and preferably, another control signal B is made “inactive” to inactivate the logic operation output to pass through. Since the initialization by the latch with the set function can be made unnecessary, it is possible to realize a low-cost, high-speed, and highly integrated memory width extension function.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of an associative memory device according to the present invention.

FIG. 2 is a schematic configuration diagram of an embodiment of a bit width expansion device used in the content addressable memory device according to the present invention.

FIG. 3 is a configuration diagram of another embodiment of the bit width expansion device used in the content addressable memory device according to the present invention.

FIG. 4 is a configuration diagram of another embodiment of the bit width expansion device used in the content addressable memory device according to the present invention.

FIG. 5 is a configuration diagram of a conventional bit width expansion device of an associative memory device.

[Explanation of symbols]

Reference Signs List 10 associative memory device 12 associative memory array 14 data and mask drive block 16 address decoder 18, 19, 60 bit width expansion device 20 match detection circuit block 22 address encoder 30, 30 ₁ , 30 ₂ , 30 ₃ match search line 31, 31 _1, 31 _2, 31 ₃ the signal transmission lines 32 _1, 32 _2, 32 ₃ composite gate 34 _0, 34 _1, 34 _2, 34 ₃ data latch circuit 62 _1, 62 _2, 62 ₃ data latches circuit 36 _0, 36 _1, 36 _2, 36 ₃ output lines 38, 38 _1, 38 _2, 38 ₃ the AND gates 39, 39 _1, 39 _2, 39 ₃ and logic circuit 40, 40 _1, 40 _2, 40 ₃ through transistor 42,52,59 control signal lines 44 _1, 44 _2, 44 ₃ control signal line 46 precharge transistor 47,56,5 7 inverter 48 sense amplifier 49, 54, 55, 58, transistor 50, 50 ₁ , 50 ₂ , 50 ₃ transistor

Claims (3)

(57) [Claims] And 1. A memory word, and memory data of the memory word and match search circuit for performing coincidence detection of the search data, a logical operation on the output and the other input of the matching search circuit row
Cormorant a first logic function circuit, before the output of the matching search circuit
A plurality of match search units each having a second logic function circuit that bypasses the output of the first logic function circuit and a search result data latch circuit that latches a common output of the first and second logic function circuits And the output of the search result data latch circuit of the first unit is the first logic of the second unit between the first unit and the second unit of the plurality of match search units. An associative memory device, comprising: a control signal input unit serving as the other input of the function circuit and exclusively activating the first logic function circuit and the second logic function circuit. 2. The first logic function circuit of the second unit, comprising: a logical product of an output of the search result data latch circuit of the first unit and an output of the match search circuit of the second unit. 2. The associative memory device according to claim 1 , wherein: Wherein said second logic function circuit, an associative memory apparatus according to claim 1 or 2 comprising with one input and one output.