JPH05258571A - Static ram - Google Patents

Abstract

PURPOSE:To enlarge capacity by miniaturizing transistors for equalizing connected between a pair of bit lines and drastically reducing chip area. CONSTITUTION:A transistor for equalizing Q4 is connected between a pair of common lines com which connects a bit line bit, bit line the inverse of bit and a sense amplifier/writing circuit 9 and a common line the inverse of com, first of all, the common line com and the common line the inverse of com are equalized by this transistor Q4. Succeedingly, a column selecting signal Y is controlled by a ATD signal in this state, the bit line bit, bit line the inverse of bit and the common line com, the common line the inverse of com are separated. And simultaneously, a transistor Q1 for equalizing connected between the bit line bit and the bit line the inverse of bit is operated, and the bit line bit and the bit line the inverse of bit are equalized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a static RAM (S
static Random AccessMemor
With regard to y), more specifically, it relates to a static RAM that requires a small equalizing transistor connected between each pair of bit lines.

[0002]

2. Description of the Related Art FIG. 3 shows the flow of address signals in a static RAM of this type. FIG. 4 shows a memory cell portion of a conventional static RAM. The schematic structure of the static RAM and the operation up to precharging the bit lines will be described below.

Column address signals AC1, AC2, ... Are input to the address buffers 1A, 1B. Next, these column address signals AC1, AC2 ... Are decoded by the predecoder 3 and column selection signals corresponding to the column address signals AC1, AC2. Similarly, column address signals AR1, AR2, ... Are input to the address buffers 2A, 2B.
A row selection signal is generated by being decoded by the predecoder 4. A memory cell is selected by the above column selection signal and row selection signal.

As shown in FIG. 4, memory cells M1, ... M
n is connected between the bit line bit and the bit line bar bit. An equalizing transistor Q1 is connected between the bit line bit and the bit line bar bit. FIG. 4 shows one column of the memory cell portion, and the other columns are similarly constructed. That is, the similar transistor Q1 and memory cells M1, Mn, ... Are connected between the other bit lines and bit line bars.

Further, word lines WL1, ... WLn are connected to the memory cells M1 ,. A common line com is connected to each of the plurality of bit lines bit. Similarly, a common line bar com is connected to each of the plurality of bit line bars bit. The data stored in the memory cells M1, ... Mn is read to the common line com and the common line bar com, and the data given from the data line DL is read to the memory cells M1 ,.
A sense amplifier / write circuit 9 that functions as a read / write unit for writing data in n is connected. Furthermore,
Transistors Q2 and Q3 for transfer gates are connected to the bit line bit and the bit line bar bit, respectively.

Referring again to FIG. 3, the column selection signal is input to the column decoder 5. Further, the ATD signal 7 is input to the column decoder 5.
The ATD signal 7 is generated by the ATD circuit 6 which detects a change in the address signal or the like. When the ATD signal 7 is input, the column decode 5 sets the column selection signal Y supplied to the transistors Q2 and Q3 to "H" level (= high level). The ATD signal 7 is also applied to the equalizing circuit 8, which causes the equalizing circuit 8 to apply the equalizing signal EQ to the transistor Q1.

When the "H" level column selection signal Y is applied to the transistors Q2 and Q3, the bit line bit is connected to the common line com and the bit line bar bit is connected to the common line bar com. In addition, ATD signal 7
The equalizing signal EQ generated by
When set to 1, the transistor Q1 turns the bit line bit
And the bit line bar bit are precharged to the same potential.

[0008]

The conventional static RAM described above has the following drawbacks.

As a recent technical trend in the field of this type of static RAM, the arrangement pitch between the bit lines and the bit line bar bits has come to be reduced by the progress of the fine processing technology of LSI. .. For this reason,
According to the above conventional example, the bit line bit and the bit line bar b
It becomes difficult to dispose one equalizing transistor Q1 for each it.

On the other hand, recently, in order to increase the capacity of the static RAM, the bit line bit and the bit line bar bit tend to be long, and in order to cope with this, a larger size equalizer is used. Transistor Q1 for use is required. However, due to the above-mentioned reason, in the current static RAM, the transistor Q1 having a larger size is limited due to the restriction on the arrangement technology of the transistor Q1.
There is a limit in dealing with the increase in capacity by using 1. Also,
If so, there is a new drawback that the chip area becomes large.

The present invention solves the above-mentioned problems of the prior art, and the transistor for equalizing connected between bit lines can be made small, and as a result, the chip area can be greatly reduced and the capacity can be increased. It is an object of the present invention to provide a static RAM which is advantageous in achieving the above.

[0012]

Static RA of the present invention
M has a first equalizing transistor connected between a pair of bit lines, and operates the first equalizing transistor according to an equalizing signal generated by an ATD signal generated by sensing a change in an address signal or the like. In a static RAM which is operated to precharge the pair of bit lines to an equal potential, a second equalizing transistor is connected between a pair of common lines connecting a plurality of pairs of bit lines and a sense amplifier, and the ATD signal is supplied. The column selection signal is controlled by the above, and the equalizing signal is applied to the second equalizing transistor to equalize the pair of bit lines through the common line, thereby achieving the above object.

[0013]

According to the above structure, first, the common line is equalized by the second equalizing transistor connected between the pair of common lines connecting the bit line and the sense amplifier. Then, the column selection signal is controlled from this state to disconnect the bit line and the common line. And
At the same time, by operating the first equalizing transistor, the pair of bit lines are equalized.

Here, the equalizing operation of the first equalizing transistor may be any operation that only maintains the potential equalized by the second equalizing transistor. This means that the first equalizing transistor only needs to have such a function. Therefore, according to the above configuration, the size of the first equalizing transistor connected between the bit lines can be minimized.

[0015]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 shows a memory cell portion of the static RAM of the present invention. Since the signal processing system for the signal applied to the memory cell portion is substantially the same as that shown in FIG. 3, the following description will be borrowed for the overlapping portions.

First, the structure of the memory cell portion will be described. FIG. 1 shows one column of the memory cell portion, and a plurality of memory cells M1, M2 ... Are connected in the row direction between a pair of bit line bits and bit line bar bits. Each memory cell M1, M2 ... Has a word line WL.
1, WL2 ... Are connected. Also, the bit line bi
The transistor Q1 for equalization is connected to a portion located at one end of the bit line bar bit t. The transistor Q1 is an N-channel MOS transistor and equalizes the bit line bit and the bit line bar bit by the equalize signal EQ provided from the equalize circuit 8 shown in FIG.

On the other hand, bit line bit and bit line bar bi
On the other end side of t, a common line com and a common line bar c
om are connected to each other. That is, the bit line b
It and the common line com are connected, and the bit line bar bi
t and the common line bar com are connected. The data stored in the memory cells M1, M2, ... Is read to the common line com and the common line bar com, and the data provided from the data line DL is read to the memory cells M1, M2.
2 is connected to a sense amplifier / writing circuit 9.

Furthermore, the bit line bit and the bit line bar bi
Transistor transistors Q2 and Q3 are connected in the vicinity of the connection between the common line com of t and the common line bar com. This transistor Q2,
Q3 is also an N-channel MOS transistor, and the column selection signal Y supplied from the column decoder 5 shown in FIG.
This connects and disconnects the bit line bit and the common line com, and the bit line bar bit and the common line bar com, respectively. Although not shown in the drawing, other columns have the same structure.

In addition to the above structure, a transistor Q4 composed of an N-channel MOS transistor is connected between the common line com and the common line bar com. The transistor Q4 equalizes the common line com and the common line bar com by the equalize signal EQ1 provided from the equalize circuit 8.

Next, the equalizing operation of the bit line bit and the bit line bar bit in the static RAM of the present invention will be described with reference to FIG.

The column address signals AC1, AC2, ..., The row address signal AR1, at the timing shown in FIG.
AR2 ... Address buffers 1A, 1B ... 2A, 2B
., The ATD circuit 6 that monitors them generates an ATD signal 7 corresponding to a change in the address signal, and supplies the ATD signal 7 to the column decode 5 and the equalize circuit 8.

Then, by the ATD signal 7 (see FIG. 2 (e)), as shown in FIG. 2 (a), the word line W is first formed.
L falls from "H" level to "L" level (= low level), and the word line WL is closed. Then, as shown in FIG. 2D, the equalizing signal EQ1 applied from the equalizing circuit 8 to the transistor Q4 is raised from the "L" level to the "H" level, whereby the common line com and the common line bar com. Is equalized.

Then, as shown in FIG. 2B, the ATD
The column selection signal Y controlled by the signal 7 is lowered from the “H” level to the “L” level, whereby the bit line bit, the bit line bar bit, the common line com,
The common line bar com is separated. At the same time, as shown in FIG. 2C, the equalizer circuit 8
Equalize signal EQ given to transistor Q1 from
Is raised from the "L" level to the "H" level, whereby the bit line bit and the bit line bar bit are equalized and precharge is performed.

In this way, after the bit line bit and the bit line bar bit are precharged, the data reading / writing is performed with respect to the memory cells M1, M2, ....

In the above structure, the transistor Q4 need only be arranged for the common line com, the plurality of bit lines commonly connected to the common line bar com, and one for the bit line bar bit. Therefore, there is a space for the transistor Q1 that needs to be provided for each bit line bit and bit line bar bit, and it is possible to cope with the increase in the capacity of the memory cell without increasing the chip area. You can

Further, if the above operation timing is surely controlled by the ATD signal 7, the equalizing operation of the bit line bit and the bit line bar bit by the transistor Q4 can be surely performed. As a result, the transistor Q1
Need only have the function of maintaining the equalized potential. Therefore, the size of the transistor Q1 can be the minimum necessary size.

Therefore, according to the invention, the bit line bi
The pitch between t and the bit line bar bit can be narrowed, and it is possible to sufficiently cope with the recent technical tendency that requires a large capacity.

[0029]

According to the above-described static RAM of the present invention, a second equalizing transistor is connected between a pair of common lines connecting a bit line and a sense amplifier, a column selection signal is controlled by an ATD signal, and The equalizing signal is applied to the second equalizing transistor to equalize the bit line through the common line.
The pair of bit lines can be surely equalized by the equalizing transistor.

As a result, the first equalizing transistor connected between the bit lines need only have the function of maintaining the potential equalized by the second equalizing transistor. Therefore, the size can be the minimum required size. Therefore, according to the static RAM of the present invention, the size of a plurality of equalizing transistors connected for each bit line can be reduced.
The entire chip area can be significantly reduced as compared with the conventional example. Therefore, there is an advantage that it can greatly contribute to an increase in capacity.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a memory cell portion of a static RAM of the present invention.

FIG. 2 is a timing chart showing the operation of the static RAM of the present invention.

FIG. 3 is a circuit diagram showing a flow of address signals in a static RAM.

FIG. 4 is a circuit diagram showing a memory cell portion of a conventional static RAM.

[Explanation of symbols]

1A, 1B Column address buffer 2A, 2B Row address buffer 3, 4 Predecoder 5 Column decoder 6 ATD circuit 7 ATD signal 8 Equalize circuit 9 Sense amplifier / write circuit bit, Bar bit line EQ, EQ1 Equalize signal M1, M2 memory Cell Q1 Equalizing transistor Q2, Q3 connected between bit lines Transistor transistor Q4 Equalizing transistor connected between common lines com, bar com Common line Y Column selection signal WL1, WL2 Word line

Claims (1)

[Claims] 1. A first equalizing transistor having a first equalizing transistor connected between a pair of bit lines, the first equalizing transistor according to an equalizing signal generated by an ATD signal generated by sensing a change in an address signal or the like. In a static RAM in which a transistor is operated to precharge the pair of bit lines to an equal potential, a second equalizing transistor is connected between a pair of common lines connecting a plurality of pairs of bit lines and a sense amplifier, A static RAM in which a column selection signal is controlled by an ATD signal, an equalizing signal is given to the second equalizing transistor, and the pair of bit lines are equalized through the common line.