JPH05258560A - Defect masking device in transparent memory body - Google Patents

Abstract

PURPOSE: To make a memory IC having a defect accomplish the same effect as a normal memory IC by masking the defect in the memory IC from the external side and making to act for the operation of the memory IC. CONSTITUTION: A defective mask 300 in a memory body is formed as an additional means in the external part of the memory IC. Plural circuit units are provided within the mask 300, and each circuit unit is provided with an address storage device 410 and a data storage device 420, respectively. And whether a defective address exists or not in the memory IC is detected with the address storage device 410, whereby whether or not the operation of the memory IC is controlled and the operation of the data storage device 420 are determined. Further, the data storage device 420 is made to act for the operation of the memory IC to mask the defective address in the memory IC and made to act for the function by controlling the address storage device 410 and a read/write signal for the memory body.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect masking device for a transparent memory body, and more particularly to a masking device outside the memory body IC
The present invention relates to a defect mask device for a transparent memory body that can replace a defective portion of the memory IC.

[0002]

2. Description of the Related Art In producing a memory IC, a product yield of a predetermined quality is one of the most important issues.
In order to improve the yield rate of the product of a given quality, two approaches should be taken; namely, the first is to improve the manufacturing process of the memory body itself to prevent the chips from being defective; 2 starts from the design side of the memory body, for example, the method disclosed in U.S. Pat. Nos. 4,733,372 and 4,829,480, that is, FIG.
As shown in FIG. 1, one 1-Mbit DRAM chip contains a matrix of one memory unit 100 and its size is provisionally set to 512 × 2048.

At the design stage of this memory body, some spare memory unit rows 110 or columns 120 can be added to the outside of the memory unit 100, and one DRAM chip is produced and classified. When it is sent to the (Sort) process, it can detect whether the chip has a defect or not, and if there is a defect, fuse the fuse in the row decoder 111 or the column decoder 121 with a laser beam or high voltage. Disconnect and connect the spare row decoder 112 or column decoder 122 to achieve the purpose of repair. However, in such a method of repairing a defect of a memory body with a spare row or a spare column, repair must be performed on a row or column basis. Since there are 2048 bits and 512 bits for each column, if even one bit is defective, it must be repaired with a spare column of at least 512 bits,
In other words, in a 1 megabit DRAM chip,
If a defect that can be repaired by an average of N spare rows occurs, the repair cost is N / 2 of the entire chip.
When reaching 048 and N = 10, the cost of the spare row becomes 0.5% of the entire chip, and if repairing by the spare row, the cost is higher when N = 10. It reaches 2% of the whole chip.

Due to such cost considerations, each memory
It is not possible to attach too many spare rows or spare columns to a chip, so in the process of classifying memory chips, it is often the case that the number of defects exceeds the maskable number of spare rows and spare columns. It is not repaired and is therefore eliminated, so that the manufacturer of the memory body must always consider the cost of the spare row or column and the cost of the chip that cannot be repaired at the design stage of the product. One compromise has to be chosen and it is not possible to repair all defects with an infinite number of spare rows or spare columns.

In addition, memory chips are still burned in after the sorting, repair, and packaging processes.
n) must be performed, and a small amount of ICs also have defects in this process, and a defect in a certain part is a defect in manufacturing that prevents a small number of memory units from operating normally. Therefore, even if there is only one bit defect, it cannot be repaired again because it has already been filled, and it must be eliminated and treated as a waste product.

Further, different memory body manufacturers have different product yield rates, and in the case of 1M DRAM as an example, the product yield rate in the classification process is usually 80.
%, And reaches over 95% in the burn-in process. If it is a 4M DRAM, the product yield rate after the classification and repair process is 60%, and the burn-in process is still 95%, that is, 25% of 1M DRAM is a defective product and 40% or more of 4M DRAM. A DRAM is a defective product, and among these defective products, many chips include only a few defective bits.

[0007]

SUMMARY OF THE INVENTION In view of the above problem of repairing a defect of a memory body in the conventional manufacturing process, the present invention masks a defect of a memory IC from the outside so that the defective memory IC has a normal IC. It is an object of the present invention to provide a defect mask device for a transparent memory body that achieves the same effect as the above.

[0008]

To achieve the above object, the present invention is an additional device external to a memory IC, which comprises a plurality of circuit units therein, and each circuit unit includes an address storage device. A data storage device is provided, and the address storage device detects the presence / absence of a defective address in the memory IC to determine whether the operation of the memory IC should be controlled and the operation of the data storage device. By controlling the read / write signals of the storage device and the memory body, the data storage device acts on behalf of the memory IC to mask a defective address of the memory IC and perform its function. ..

A memory device set for recording a defective address in the memory IC, a latch set for temporarily storing a working address of the memory IC, and a temporary storage address in the latch set are stored in the respective address storage devices. And a comparator which compares the defective address in the memory IC with each other and outputs a "comparison coincidence" signal when the both coincide with each other, so that the "comparison coincidence" signal generated in each of the address storage devices is provided. It is connected to an OR or other system so as to finally output the "match"signal; and the data storage device is provided with a memory body of 1 bit or more, and the memory body technology is formed into SRAM or EEPROM. And further controlling the operation of the memory IC on the signal bus by the "match" signal, if the memory IC is activated or equivalent. When the control signal is not output, the "match" signal always sends a "write" output enable signal to the memory IC. If an output activation signal exists in the memory IC, The "match" signal always prompts the memory IC to output a start signal to enter the interrupt disabled state, prevent the memory IC from outputting a data signal, or cause the output signal of the memory IC to be in a high impedance state. As shown; the memory IC is a full-associative memory or a N-way S
It is more preferable to have a configuration similar to the associative memory.

[0010]

The present invention having the above-described structure has the memory I.
C When provided externally, a plurality of circuit units are provided therein, each circuit unit is provided with an address storage device and a data storage device, and the address storage device provides a defective address to the memory IC. Whether or not the operation of the memory IC should be controlled and whether or not the operation of the data storage device can be determined by detecting whether or not there is, and by controlling the read / write signals of the address storage device and the memory body, the data Since the storage device can operate the memory IC, the defective address of the memory IC can be masked to substitute the function of the memory IC.

In each of the address storage devices, a memory device set for recording a defective address in the memory IC, a latch set for temporarily storing a working address of the memory IC, and a temporary storage address in the latch set. And a comparator for generating a "comparison match" signal by comparing defective addresses in the memory IC, and connecting the "comparison match" signal generated in each address storage device to an OR or other method. So as to generate a final "match" signal: and the data storage device is provided with a memory body of one bit or more, and the memory body technology is formed into SRAM or EEPROM; The signal controls the operation of the memory IC on the signal bus, and if the memory IC does not activate or output a control signal equivalent thereto, The "match" signal always sends a "write" output enable signal to the memory IC, and if the memory IC has an output start signal, the "match" signal must be sent by the memory IC. By outputting a start-up signal to prompt an interrupt-disabled state so that the memory IC does not output a data signal or the output signal of the memory IC exhibits a high impedance state, the memory IC is All Associative Memories (Full Associate Memor)
y) or an N-Way Set associative memory may be configured so that any defective memory IC can function more reliably and more accurately as a normal IC. it can.

[0012]

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings. In the current memory body manufacturing industry, a plurality of DRAM ICs are always attached to a small printed circuit board to obtain SIMM or SIP (Single).
The SIMM or SIP signal pin has a common industrial standard, and for the sake of clarity, a 1M × 8 SIMM signal pin will be described as an example. 1M × 8 DRAM SI
As shown in FIG. 16, the structure of the MM and its interface signals have a total capacity of 1M × 8 because there are eight 1M × 1 DRAMs 200 in total, and the interface signals of the entire DRAM SIMM and the external world are basically the DRAM.
It is a direct extension of the 200 pin signal. These signals are supplied to the VDD and VSS power supplies, the A0 to A9 address lines 220, the DQ0 to DQ7 data lines 210 and the RAS.
Includes three control lines such as * 230, CAS * 240 and WE * 250. Basically, when the DRAM SIMM is performing a read operation, its working waveform is as shown in the upper half of FIG. Become.

FIG. 1 shows the above-mentioned DRAM SIMM.
The defect mask (Defect Mask) device 30 of the present invention
0 is added to the matrix of the DRAM 200 (Mat
The defect mask device 300 masks the defect existing in rix), but the signal of the defect mask device 300 is similar to the signal of the pin of the DRAM, and the difference between the two is that the data lines of the defect mask device 300 are DQ0 to DQ0. DQn, where n is SI
Indicates the data width (Data Width) of MM.
The data width of a normal SIMM is 8, 9 or 32 bits, while n = 7. Further, the defect mask device 300 has one WEO * 470 than the DRAM 200.
The difference is that there are many signals, and the above WE * 250 signals are DR
It controls the read or write operation of the AM 200. Then, in order to achieve the purpose of masking the defect function in the DRAM 200, the defect mask device 300 uses S
If the signal from the WE * 250 outside the IMM is received and it is found that the defective address of the memory body in which the defect mask device 300 is present appears, the signal is dripped from the WEO * 470 pin.
Issue to the WE * pin of the AM200 matrix to output the DRAM20
0 is placed in the "write" state, and under the "write" state, the data output of the DRAM 200 exhibits a high impedance so that it does not interfere with other signals on the data bus 210. Defect mask device 300
Further determines whether to read or write the data bus 210 based on the external WE * signal.

FIG. 2 shows the above defect mask device 30.
The basic structure of the defect mask device 300 is substantially the same as that of the defect mask device 300 and a general CAM (Content Addressable Memory).
Alternatively, it is similar to the associative memory (Associate Memory), and N entries (E
ntry) may be provided, and each entry has a valid bit (Valid Bit) 430 and an address cell (Addre).
ss Cell 410 and data cell (Data Cell 42
0) and the valid bit 430.
Is used to indicate whether the entry has already been written to the defective address and if the valid bit 430 is true (T
rue), the address cell 410 of the entry must always monitor the address 220, and if the address of the address bus 220 and the address cell 41
Hit (Hit) when 0's own defective address matches
440 signal is generated. Then, the defect mask device 30
If a hit 440 signal is generated in any one of the 0 entries, the AND gate (AND Gat) shown in FIG.
e) 400 positions WEO * in the "true" state
Since EO * is connected to the matrix pin of the DRAM 200, at this time, if the DRAM 200 enters the "write" operation state and the hit 440 signal is not established, the AND gate 400 of FIG. The WE * 250 signal is allowed to pass freely to drive the WE * 250 of the DRAM 200. If the signal of the hit 440 is "true", the data cell 4 of the entry which issued the hit 440 signal.
20 mimics the operation of DRAM 200 depending on the state of WE *, and if WE * 250 is "true", the data cell 420 will store the signal on the data bus 210, and vice versa. The data cell 420 will release its data to the data bus 210 and the SI
Speaking from the external circuit of the MM, it is not possible to see the mask operation that occurs when the defective mask device 300 is hit,
Overall, the SIMM's functionality behaves like a flawless SIMM.

A normal DRA is shown in the upper half of FIG.
The read waveform of the M200 and the working waveform in the hit state of the defect mask device 300, the WE * 250 is HIGH and the CAS * 240 appears for a certain period of time.
It can be seen that the valid data (Valid Data) of the DRAM 200 appears in the Dout 550 of the RAM 200. Figure 3
When a hit 440 signal is generated in the lower half of the
EO * 470 becomes “true”, and at this time, the DRAM 200
The Dout 550 signal maintains a high impedance state and does not emit a signal. Then, the defect mask device 300
Data bus 210 because WE * 250 is “tentative”
The data in the data cell 420 is discharged to the memory cell 420. Therefore, the utility of the defect mask is the read cycle (Read C) of the memory body.
ycle).

FIG. 4 shows the defect mask device 30.
In the structure diagram of the address cell 410 in 0 and the valid bit 430, the row address latch 6 is provided for each address 410.
10 is included and is used to store the row address during the RAS * cycle. Defective row address PROM
(Defect Row Address PROM) 620 and defective column address PROM (Defect Column Address PROM)
M) 630 is used to permanently record the defective address in the DRAM 200, and is used as an address comparator (Address Com).
parator) 640 is the signal of address bus 220 and PROM
Used to compare the address of the defective column / row in 620 and 630 to see if it matches, if there is a hit n
Generate a 680 signal. The output control circuit 700 is shown in FIG.
The purpose is SIMS RAS * 230 and CA.
S * 240 determines what this is a DRAM operation, eg read, write, full page read (P
age Mode Lead), all page writing (Page Mode Wri)
te), read-after-write (Read Modified Write)
, And refresh, etc. Then, except in the refresh cycle, the output control circuit 700 outputs the signal 71
Generates 0 and latches 610 and PROMs 620 and 630.
To release the signal to the comparator 640,
Determine if a hit n signal 680 has occurred.

Valid bit PROM, shown in FIG.
650 is used to control whether or not the address cell 410 should be activated, and the output Q * of the PROM 650 maintains a "temporary" state before a program is written in the valid bit PROM 650, so that the signal hit n680 is also reduced. "Tentative"
Therefore, a pair of defective column / row addresses are about to be written to the PROMs 620 and 630, and at the same time, the signals WSELn * 660 and VPP670 are all “true”.
Therefore, the output Q of the PROM 650 is also written as "true", and the address cell 410 can be used. The entire defect mask device 300 includes N address cells 410 as shown in FIG.
The output signal of the hit n680 of each address cell 410 is
The hits 440 shown in FIG. 2 are always generated, and as a simple method therefor, there is a wired OR gate method as shown in FIG.

Defective row address PROM shown in FIG.
620 and defective column address PROM 630 must be S
In the process of manufacturing the IMM, all defective addresses of the DRAM 200 are written, and the program writing procedure of the PROMs 620 and 630 is shown in FIG.
Must be greater than or equal to the number of defect positions in the DRAM 200, and if the number of defects in each DRAM 200 does not exceed 4 or more, then 8 DRAMs are required.
The defect mask device 300 used by the SIMM formed by 200 must have 32 entries, that is, FIG. 6 will be described by taking 32 entries as an example.

In FIG. 6, a programmer (Programer) of the defect mask device 300 first sets one entry pointer (Entry Pointer) to 0 as indicated by 810, and thereafter, a matrix (Matrix) of the DRAM 200.
Until the defective address is found or the DRAM 20
Scanning is performed as indicated by 820 up to the end of 0. Young D
If it is at the end of the RAM, then the blogging of the defect mask device 300 should be bound at 830, otherwise the bloglamer will always send PEN * and continue to A0.
The value of the entry guideline is transmitted from A4. The value of the entry pointer is captured by the latch 1110 shown in FIG. 9, and the WSELn * signal 660 is generated through the decoder 1120 to generate the PROM 620 of the Nth address cell 410.
630 and 650. The PROMs 620 and 63
When data is written to 0 and 650, the programmer must always establish WEN *, VPP and WSELn *, and must therefore send VPP as shown at 850 as the next step. Thereafter, at 860, RAS * and the defective row address are transmitted, and a certain time delay (Delay) 870 is performed to complete the program specifications of the PROM 620. At 880, CAS * and the defective column address are transmitted, and after a certain time delay. PROM630
And 650 complete the program write, and finally the programmer cancels the PEN * signal, adds 1 to the entry pointer, and returns to 820 to continue searching for the next defect.

FIG. 7 shows a logic circuit of the output control circuit 700. The operation of the output control circuit 700 generates an OE * signal and sends it to the latch 610, PROMs 620 and 630, and the latch 610, PROMs 620 and 630. At a more appropriate time, the address is sent to the comparator 640 and compared to generate a hit n680. The flip-flop (Flip Flop) in FIG. 7 can record the CAS * signal at that time when RAS * is in a falling wave,
If CAS * is LOW at this time, it indicates a CAS * -before-RAS * refresh cycle,
The defect mask device 300 does not operate. Then, as seen from the waveform of FIG. 3, when RAS * falls, a row address appears on the address bus 220, and at this time, the comparator 6
When 40 is activated, the two row addresses are combined into A0 to A9 and compared with the defective address. If there is exactly one position hit in the defective address cell, erroneous operation will occur and therefore the delay line (Delay Lin) in FIG.
e) The purpose of 930 is to establish OE * 710 after waiting for address bus 220 to disappear at the row address after RAS * 230 has fallen. And FIG.
, The CLR of the flip-flop 920 removes Q and simultaneously removes OE * 710 when RAS * 230 rises.

The logic shown in FIG. 7 is the RAS of the DRAM.
* -OE * 71 in only-refresh cycle
At this time, if the hit n680 is in the "true" state, the defect mask device 300 immediately detects WEO * 470.
, The Nth data cell 420 of the entry in the defect mask device 300 immediately operates according to CAS * and WE *, and CAS * appears because it is in the RAS * -only-refresh cycle. In addition, the Nth data cell of the defect mask device 300 does not cause an erroneous operation, and the DRAM 200 also has WEO * 4.
The erroneous operation due to 70 does not occur.

The output control circuit 700 shown in FIG. 7 is designed so that the hit n680 appears as early as possible. The WEO * 470 is emitted as soon as possible, and the DRAM 200 provided with the defect mask device 300 is arranged. If the main body has an output activation control signal, CAS * may be used instead of the entire output control circuit 700. At the same time, the AND gate 400 shown in FIG.
Control the signal, not the WE * 250 signal. outside,
As another embodiment, the AND gate 400 shown in FIG. 2 controls the CAS * signal but does not control the WE * 250. In this case, the WE * 33 shown in FIG.
0 and the signal connection method with the CAS * 340 defect mask device 300 must be corrected as shown in FIG.

FIG. 8 is a structural diagram of the data cell 420 of the entry in the defect mask device 300. The data cell 420 is a memory unit 1030 for replacing the defective memory address of the DRAM 200, and the memory cell 1030 "". The data cell 420 itself includes a NAND gate 1020 for controlling a "write" operation and an AND gate connected to the clock terminal CLR of the flip-flop 1040 for controlling a "read" operation of the memory unit 1030. is there. Its purpose is DRA
It replaces the memory function of the defective position in M200, and when a hit n680 occurs, CAS *
If 240 is “true” and WE * 250 is also “true”,
The Nth data cell 420 records the signal on the data bus 210. If the hit n680 and CAS * are both satisfied and WE * 250 is not satisfied, the data cell 420 stores the stored data. The data bus 210
To be released. If hit n680 is established and CAS * 2
If 40 does not appear, data cell 420 will be inactive.

In the above description, the SIMM of the DRAM 200 is taken as an example. In a similar process, the defect mask device 300 of the present invention is applied to a mother board of a computer or a subsystem of a memory body to make a memory body memory. The purpose of masking the defective function can also be achieved. At this time, the widths of the address cells 410 and the data cells 420 in the defect mask device 300 must be corrected according to the system standard, and at the same time, the number of entries of the defect mask device 300 must be increased. , Must accommodate more defective addresses.

If the memory body arranged and used in the defect mask device 300 is not the DRAM 200, the structure of the defect mask device must be revised accordingly. That is, first, the interface signal; DR
In addition to the RAS * and CAS * address control signals in the AM 200, all general memory units temporarily record the access address of the memory unit by the address latch activation signal (ALE) or the chip select signal (CS *). Therefore, the address bus interface of the defect mask device 300 must be corrected as shown in FIG.
On the other hand, since all the memory bodies other than the DRAM normally have the OE * control signal to control Dout, the gate 1200 in FIG. 10 may control the OE *.

Second, data cell 420; data cell 4
Reference numeral 20 is a proxy position of the matrix defect position in the memory body, and basically, the technique of the data cell must always correspond to the matrix of the memory body, for example, the ROM matrix for the ROM data cell. The above technology may be both SRAM and EEPROM. When the data cell is SRAM technology, the external memory body matrix may be DRAM, SRAM slower than the data cell, or some other form of ROM. Well, in the case of the data cell EEPROM technology, the memory matrix is ROM, PROM, EPROM, FLA.
It may be either SH or EEPROM. 11
The matrix operating waveforms of the defect mask device 300 and the virtual SRAM are shown in FIG. 5, and one extra VPP is included in the operating waveforms of the PROM, EPROM, FLASH, and EEPROM.
Signal, ROM has no WE * cycles.

Lastly, the above embodiment is one of the relatively good embodiments in which the defect mask device 300 of the present invention and the DRAM 200 interface are simply connected, and as a circuit for achieving the purpose, FIG. It may be formed as shown in FIG.
It is another type of connection application mode of the AM200 interface. The difference between the application circuit of FIG. 12 and FIG.
The defect mask device 300 of No. 2 is the CAS of the DRAM 200.
* The point of having a function of suppressing the defect of the DRAM 200 through the control of the signal is shown in FIG.
The defect mask device 300 corresponding to the tangent line of FIG.
In this case, the tangential line change occurs inside, and at this time, the signal controlled by the AND gate is already changed to CAS *.

As described above, the embodiments of the defect mask device shown in FIGS. 2 and 10 and the defect mask device shown in FIG. 13 mainly have a structure similar to that of the full associative memory (Ful Associate Memory). One possible implementation is a configuration similar to the N-Way Set associative memory body,
As shown in FIG. 14, the configuration of the defect mask device 300 is such that N sets of valid bits 1610 and defect addresses 1620 are provided.
And memory cell series such as data cell 1630, comparator 16
40 and an RD / WR controller 1680, a memory device 1600; an address decoder 1650; an address latch 1660; and a control logic circuit 1670.

In the RAS cycle of the DRAM 200, the address latch 1660 first detects the DRAM 20.
0 row address is latched and the address decoder 1650
Activates the valid bit 1610 and defective address memory body 1620 of a certain column in each set memory body device 1600 according to the decoding address sent from the address latch 1660, and if the column address of the DRAM 200 appears, the address The comparator 1640 compares the values of the address latch 1660 and the defective address memory body 1620, and if the values are “match”, the control logic circuit 167.
A signal of WEO * 470 is generated at 0 to suppress the operation of the defective memory body;
RD / WR controller 1680 in the data cell 1
The read / write execution operation in DQ0 to DQ7 210 of 630 is controlled. Therefore, when designing the defect mask device 300 with the associative memory body collective configuration, it is possible to form the memory body devices 1600 by a sufficient number of groups to cover and mask defects generated at the same number of opposing positions. Must be done.

[0030]

According to the present invention constructed as described above, when provided outside the memory IC, a plurality of circuit units are provided therein, and each of the circuit units has an address storage device and a data storage device. And detecting whether or not there is a defective address in the memory IC by the address storage device, and whether or not to control the operation of the memory IC and the operation of the data storage device can be determined. By controlling the read / write signals of the address storage device and the memory body, the data storage device can operate the memory IC. Therefore, the defective address of the memory IC is masked to replace the function of the memory IC. You can

In each of the address storage devices, a memory device set for recording a defective address in the memory IC, a latch set for temporarily storing a working address of the memory IC, and a temporary storage address in the latch set. And a comparator for generating a "comparison match" signal by comparing defective addresses in the memory IC, and connecting the "comparison match" signal generated in each address storage device to an OR or other method. To provide a final "match"signal; and provide the data storage device with a memory body of one bit or more to form the memory body technology in SRAM or EEPROM; and further, to provide the "match" signal. The signal controls the operation of the memory IC on the signal bus, and if the memory IC does not activate or output a control signal equivalent thereto, The "match" signal always sends a "write" output enable signal to the memory IC, and if the memory IC has an output start signal, the "match" signal must be sent by the memory IC. Since the memory IC does not output a data signal or the output signal of the memory IC exhibits a high impedance state by outputting a start-up signal to prompt an interrupt disabled state, it has a defect. The memory IC can function more reliably and more accurately like a normal IC.

[Brief description of drawings]

FIG. 1 is an application circuit diagram in a defect mask device of the present invention.

FIG. 2 is a diagram showing the internal structure of the defect mask device of the present invention.

FIG. 3 is a signal waveform diagram when the defect mask device of the present invention and the DRAM are operated together.

FIG. 4 is a diagram showing an address cell structure in the defect mask device of the present invention.

FIG. 5 is an output control circuit diagram of an address cell in the defect mask device of the present invention.

FIG. 6 is a programming block diagram of an address cell in the defect mask device of the present invention.

FIG. 7 is a structural display diagram of a data cell in the defect mask device of the present invention.

FIG. 8 is a logic circuit diagram of a data cell in the defect mask device of the present invention.

FIG. 9 is a circuit diagram of an entry select signal generation circuit in the defect mask device of the present invention.

FIG. 10 is a configuration display diagram when a memory body other than a DRAM is arranged in the defect mask device of the present invention.

11 is an operation waveform diagram of FIG.

FIG. 12 is another application circuit diagram of the defect mask device and the DRAM interface of the present invention.

13 is a diagram showing the configuration of the defect mask device shown in FIG.

FIG. 14 is a configuration display diagram of another embodiment of the present invention.

FIG. 15 is a block diagram showing an internal structure and a spare memory column or row in a conventional 1M DRAM chip.

FIG. 16 is an application circuit diagram of a conventional DRAM.

[Explanation of symbols]

 200 ... DRAM 210 ... Data bus 300 ... Defect mask device 400 ... AND gate 410 ... Address cell 420 ... Data cell 430 ... Effective bit

Claims (5)

[Claims] 1. An additional device external to a memory IC, comprising a plurality of circuit units therein, and each of the circuit units being provided with an address storage device and a data storage device, the address storage device providing the memory. By detecting the presence / absence of a defective address in the IC, determining whether or not the operation of the memory IC should be controlled and the operation of the data storage device, and further controlling the read / write signals of the address storage device and the memory body, A defect mask device for a transparent memory body, wherein the data storage device acts on behalf of the memory IC to mask a defective address of the memory IC and to perform its function. 2. A memory device set for recording a defective address in the memory IC, a latch set for temporarily storing a working address of the memory IC, and a temporary storage address in the latch set in each of the address storage devices. And a comparator which compares the defective address in the memory IC with each other and outputs a "comparison coincidence" signal when the both coincide with each other, so that the "comparison coincidence" signal generated in each of the address storage devices is provided. 2. The defect mask device for a transparent memory body according to claim 1, wherein the defect mask device is connected to an OR or other system to finally output a "match" signal. 3. The data storage device is provided with a memory body of 1 bit or more, and the memory body technology is SRAM or EE.
The defective mask device for a transparent memory body according to claim 1, which is formed in a PROM. 4. The memory I according to the "match" signal.
Controlling the operation of the C signal bus, if the memory IC
Is not activated or outputs a control signal equivalent thereto, the "match" signal must always send a "write" output enable signal to the memory IC, and if the memory IC has an output activation signal. If so, the “match” signal always prompts the memory IC to output a start signal to enter the interrupt disabled state, and prevents the memory IC from outputting a data signal, or the output of the memory IC. 3. The defective mask device for a transparent memory according to claim 2, wherein the signal exhibits a high impedance state. 5. The associative memory (Ful) is used as the memory IC.
2. The defective mask device for a transparent memory body according to claim 1, wherein the defective mask device may have a structure similar to that of an associative memory or an N-way set associative memory.