JPH05257864A - Direct memory access device - Google Patents

Abstract

PURPOSE:To make DMA transfer from a memory to a specific transfer destination device efficient when a series of data are stored in the memory divisionally as plural discontinuous blocks. CONSTITUTION:The blocks of the data 302 stored in the memory are given control information 303. The control information 303 indicates the head address of the block to be read next by DMA. Its head bit 304 is used to discriminate between the data 302 and control information 303. The data are read out of the memory by the DMA according to a DMA transfer command from a CPU and the head address of the block to be read next is decided according to the control information 303. Consequently, the data 302 stored as the discontinuous blocks can be transferred by the DMA with one DMA transfer command generated by the CPU and the frequency of actuation of the DMA decreases, so the DMA transfer efficiency is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a direct memory access device (DMA) which is capable of directly accessing and transferring data stored in a memory.

[0002]

2. Description of the Related Art Conventionally, DMA has been used in a data processing device such as a computer. In Figure 3, DM
The configuration of the data processing device with A is shown.

The device shown in this figure comprises a memory 101,
Bus 1 for I / O 102, CPU 103, and DMA 105
It is the structure connected by 04. When the CPU 103 tries to transfer the data in the memory 101 to the external transfer destination device via the I / O 102, the CPU 103 uses the DMA1
05 issues a command to perform DMA transfer, and DMA1
05 responds to this command with I / O data stored in the memory 101.
Write to O102. That is, the DMA 105 directly accesses the memory 101 and transfers this data to an external transfer destination device via the I / O 102. DMA105 is
Therefore, the transfer of data between the memory 101 and the I / O 102 is executed, and when a plurality of memories 101 are provided, the transfer of the memory 101 to the memory 101 is realized.

[0004]

As described above, according to the conventional data processing device, the load on the CPU 103 is reduced by using the DMA 105, and a large amount of data can be transferred to an external device at high speed. .. However, when a series of data is divided into a plurality of discontinuous blocks and stored in the memory, the CPU must issue a command for each block when attempting the DMA transfer. That is, the CPU has to activate the DMA for the number of blocks, which reduces the efficiency of the DMA transfer.

Now, the conventional DMA transfer efficiency can be obtained by the following equation.

[0006]

[Equation 1] Among the variables appearing in this equation, D and B cause the transfer efficiency A to decrease. For example, when the transfer time per word (1 word = the smallest unit of data transferred by DMA) is 1, the time required to activate the DMA is 10 and the time required for the CPU to determine the order of data blocks is 3
It can be zero. In this case, the time required to transfer 100 words is as shown in the following table when the number of blocks storing the data to be transferred is changed.

[0007]

[Table 1] That is, the smaller the data block size and the larger the number of data blocks, the lower the DMA transfer efficiency A becomes.

The present invention has been made to solve the above problems, and even when a series of data is divided and stored in a plurality of discontinuous blocks in a memory, these data are stored. Data related to the block
An object of the present invention is to provide a device capable of efficiently transferring to an external device by MA transfer.

[0009]

In order to achieve such an object, the DMA of the present invention comprises means for directly reading data from a memory in response to a command from a processor and means for writing data to a transfer destination device. Discontinuity is achieved by determining the block to be read subsequently to the block based on the management information added to the data stored in the memory in block units, and controlling the data read operation based on the determination result. Means for managing reading of data stored in a plurality of blocks.

Further, the data processing apparatus of the present invention is capable of dividing a series of data into a plurality of discontinuous blocks and storing the data, and blocks to be read subsequently given to the plurality of discontinuous blocks. Memory for storing management information, a processor for issuing a command to transfer the data in the memory to the transfer destination device, and a series of data stored in the memory divided into a plurality of discontinuous blocks. , The DMA of the present invention for transferring to the transfer destination device in response to one command from the processor.

[0011]

In the DMA of the present invention, the management means makes the determination based on the management information. When a series of data is divided into a plurality of discontinuous blocks and stored in the memory, a block to be read subsequent to a certain block is determined by this determination. Further, the management unit controls the data reading operation based on the determination result. Therefore, even when a series of data is divided and stored in a plurality of discontinuous blocks on the memory, it becomes possible to transfer these data by one DMA transfer command, and the DMA transfer efficiency can be improved. Is improved.

The same operation can be obtained in the data processing device of the present invention.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a DMA according to an embodiment of the present invention.
The configuration of 201 is shown. DMA shown in this figure
201 comprises a data reading block 202, a DMA control block 203, and a data writing block 204. The DMA 201 of this figure is applicable to a data processing device having a configuration as shown in FIG.

The data reading block 202 is a block for reading the data written in the memory 101 in response to a DMA transfer command from the CPU 103. DM
The A control block 203 is the data reading block 20.
The data read in 2 is output to the data write block 204 while determining management information. The data write block 204 transfers the data to a predetermined transfer destination device by writing the data to the I / O 102.

The management information to be judged by the DMA control block 203 is the information 303 given to each block as shown in FIG. When data is written on the memory 101, as shown in FIG. 2, it is divided into a plurality of discontinuous blocks 301 and written, and at that time, n pieces of data 302 are written in each block 301.
In addition to this, management information 303 is added.

The first 1 bit 304 of the data 302 and the management information 303 is the data 302 or the management information 3
It is a bit indicating whether it is 03. The DMA control block 203 determines that the data 302 is the data 302 when the first bit 304 of the information read from the memory 101 is “0”, and determines the management information when it is “1” and performs control. .. The DMA control block 203 knows the start address of the block to be read next from the contents stored in the memory 101 as the management information 303, and reads the data of the next block.

The DMA transfer efficiency A in this embodiment is obtained by the following equation.

[0019]

[Equation 2] That is, the DMA obtained by the above equation in this embodiment.
Since the number of times the DMA 201 is activated is one, the transfer efficiency A is significantly improved as compared with the conventional one as shown in Table 2.
For example, when the number of transfer blocks is 2, and the number of words per block is 50, the transfer efficiency of 66.7% in the past is improved to 87.0%, and the transfer block number is 10,
Conventional 2 when the number of words per block is 10
The transfer efficiency, which was 1.3%, is improved to 64.5%.

[0020]

[Table 2]

[0021]

As described above, according to the present invention,
When the data is stored in the memory, the management information is added in block units, and the block to be read next is determined based on this management information. Therefore, the number of DMA activations is reduced and the transfer efficiency is significantly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a DMA according to an embodiment of the present invention.

FIG. 2 is a diagram showing a data storage mode on a memory in this embodiment.

FIG. 3 is a block diagram showing a configuration of a general data processing device.

[Explanation of symbols]

 101 Memory 102 I / O 103 CPU 201 DMA 202 Data Read Block 203 DMA Control Block 204 Data Write Block 301 Block 302 Data 303 Management Information 304 Data or First 1 Bit of Management Information

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shoji Ishikawa 5-1-1 Shimorenjaku, Mitaka-shi, Tokyo Within Japan Radio Co., Ltd. (72) 5-1-1 1-1 Shimorenjaku, Mitaka-shi, Tokyo Inventor Within the corporation

Claims (2)

[Claims] 1. A means for directly reading data from a memory in response to a command from a processor, a means for writing the data to a transfer destination device, and a management information added to the data stored in the memory in block units. A block to be read subsequent to the block concerned, and controlling the data read operation based on the result of the judgment, thereby managing the reading of the data stored divided into a plurality of discontinuous blocks. A direct memory access device comprising: 2. A memory capable of storing a series of data by dividing it into a plurality of discontinuous blocks and storing management information indicating a block to be read subsequently given to the plurality of discontinuous blocks. And a processor issuing a command to transfer the data in the memory to the transfer destination device, and a series of data stored in the memory divided into a plurality of discontinuous blocks into one command from the processor. A direct memory access device according to claim 1, which transfers data to a transfer destination device in response thereto, and a data processing device.