JPH05257790A - Set panel device - Google Patents

Abstract

PURPOSE:To simultaneously and surely write data in plural panels by finishing a write cycle by outputting an answer signal at the time of a simultaneous transmission mode to a main processing part after the lapse of prescribed time when the simultaneous transmission mode is detected. CONSTITUTION:When simultaneously writing data from a main processing part 1 to panels 20-2N, the address of the simultaneous transmission mode is outputted. A simultaneous transmission mode detecting circuit 2 recognizes this address, applies a signal to each panel for showing write in the simultaneous transmission mode and starts a timer 4 for preparing the answer signal. This timer 4 outputs signals by being operated after the lapse of time longer than required time for write on the panels 20-2N. Corresponding to the instruction of the simultaneous transmission mode detecting circuit 2, a selector circuit 3 switches an input from the panel side through an answer signal line 50 to an input from the timer 4 for preparing the answer signal and applies the signal from this timer 4 to the main processing part 1 as the answer signal, and the main processing part 1 finishes the write cycle corresponding to this signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a device in which a plurality of panels for writing data are mounted. In particular, it relates to write control means for each panel in the device.

[0002]

2. Description of the Related Art Conventionally, in a device in which a plurality of panels are mounted, as shown in FIG. 2, a main control unit 10 in the device, via an address bus 40 and a data bus 30, each of the other panels 20 to 2N. It is connected to the. When the main controller 10 writes data to each of the panels 20 to 2N, the accessed panel outputs a response signal to the main controller 10. The main processing unit 1 recognizes from this response signal that the data was correctly written on the panel, but if the same data is written on a plurality of panels at the same time, a plurality of response signals are returned to the main processing unit 1. The main processing unit 1 ends the write cycle with the response signal returned first.

[0003]

In such a conventional example, when the main controller writes the same data to a plurality of panels at one time, the response signals returned from the accessed panels vary. Since the main control unit ends the write cycle in accordance with the response signal returned first, there is a drawback that a panel in which writing is not possible occurs.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a collective panel device having means for surely executing simultaneous writing of data to a plurality of panels.

[0005]

SUMMARY OF THE INVENTION The present invention comprises a plurality of panels and a main control section including a main processing section having means for writing data to the panels, each of the panels being written with data. In a collective panel device having means for generating a response signal when the response signal is given, and the main processing section having means for recognizing that the response signal has been given and ending the write cycle, the plurality of panels are simultaneously operated. Detecting means for detecting the simultaneous transmission mode indicating writing, a timer which is activated in response to the simultaneous transmission mode detection by the detecting means and outputs a response signal after a predetermined time has passed, a response signal from each of the above panels and the timer Response signal from the timer is selected when the detection means detects the simultaneous transmission mode, and when the simultaneous transmission mode is not detected, the response signal from the timer is selected. Select a response signal from the panel, characterized in that a selection means for applying to the main processing unit.

Here, the detecting means may be means for recognizing the simultaneous transmission mode when the bit string at a predetermined position included in the address output by the main processing section shows a specific pattern.

[0007]

When the address output from the main processing unit is identified to be in the simultaneous transmission mode, the timer is started, and after a predetermined time is counted, the response signal in the simultaneous transmission mode is output to the main processing unit to start the write cycle. To finish. When writing data from the main processing unit to each of the panels individually, the main processing unit ends the write cycle in response to the response signal from the panel.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In this embodiment, as shown in FIG. 1, a main control unit 10, panels 20 to 2N, a data bus 30, an address bus 40 and a response signal line connecting the main control unit 10 and the panels 20 to 2N. 50, in which the main control unit 10 includes a main processing unit 1, a simultaneous transmission mode detection circuit 2, a response signal creation timer 4, and a selector circuit 3.
To prepare. That is, this embodiment has a plurality of panels 2.
0 to 2N and a main control unit 10 including a main processing unit 1 having means for writing data to the panels 20 to 2N, each of the panels 20 to 2N outputs a response signal when data is written. The main processing unit 1 has a means for generating, the main processing unit 1 has a means for recognizing that a response signal has been given, and ending the write cycle. Further, as a feature of the present invention, a plurality of panels 20 to 2N are provided. Simultaneous transmission mode detection circuit 2 which is a detection means for detecting the simultaneous transmission mode indicating the simultaneous writing to and a response signal generation which is activated in response to the detection of the simultaneous transmission mode by the detection means and outputs a response signal after a lapse of a predetermined time. Timer 4 and each of the panels 20 to
2N response signal and timer 4 for creating this response signal
When the detection means detects the simultaneous transmission mode, the response signal from the timer is selected, and when the simultaneous transmission mode is not detected, panels 20 to 2 are supplied.
And a selector circuit 3 which is a selection means for selecting a response signal from each N and giving it to the main processing section 1. Here, the detection means is means for recognizing the simultaneous transmission mode when the bit string at the predetermined position included in the address output by the main processing section 1 indicates a specific pattern.

Next, the operation of this embodiment will be described. When the main processing unit 1 simultaneously writes data to the panels 20 to 2N, it outputs the address in the simultaneous transmission mode. The structure of this address is different between the simultaneous transmission mode and the individual writing to each panel. For example, in the simultaneous transmission mode, the upper 8 bits are “31XXXXH”.
The simultaneous transmission mode detection circuit 2 recognizes the address indicating the simultaneous transmission mode, gives a signal indicating that writing is performed in the simultaneous transmission mode to each panel, and activates the response signal generation timer 4. This response signal creation timer 4
Operates and outputs a signal after a time longer than the time required for writing on the panels 20 to 2N. The selector circuit 3 receives the response signal line 50 according to the instruction from the simultaneous transmission mode detection circuit 2.
The input from the panel side via the switch is switched to the input from the response signal generating timer 4, and the signal from the response signal generating timer 4 is given to the main processing unit 1 as a response signal. The main processing section 1 recognizes this signal and ends the write cycle. On the other hand, when the simultaneous transmission mode detection circuit 2 does not recognize the address of the simultaneous transmission mode, the selector circuit 3 is connected to the response signal line 50 side, and the accessed panel of the panels 20 to 2N is selected as in the conventional example. Is sent to the main processing unit 1, and the write cycle is ended by recognizing this response signal.

[0010]

As described above, according to the present invention, when the simultaneous transmission mode is recognized, the response signals individually returned from the panel are ignored, and the output of the timer activated when the simultaneous transmission mode is detected is output to the main processing unit. Since it will be sent back to, there is an effect that data can be written to the panel without fail by setting the timer so that the data can be written sufficiently to the panel.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block configuration diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 Main Processing Section 2 Simultaneous Transmission Mode Detection Circuit 3 Selector Circuit 4 Response Signal Creation Timer 10 Main Control Section 20-2N Panel 30 Data Bus 40 Address Bus 50 Response Signal Line

Claims (2)

[Claims] 1. A plurality of panels and a main control section including a main processing section having means for writing data to the panels, each panel generating a response signal when data is written. In the collective panel device having means for recognizing that a response signal has been given and ending the write cycle, the main processing unit detects a simultaneous transmission mode indicating simultaneous writing to a plurality of the panels. Detecting means, a timer which is activated in response to the simultaneous transmission mode detection by the detecting means and outputs a response signal after a predetermined time has passed, a response signal from each panel and a response signal from this timer are given, and When the detection means detects the simultaneous transmission mode, it selects the response signal from the timer, and when it does not detect the simultaneous transmission mode, it selects the response signal from each panel. A collective panel device, comprising: selecting means for selecting and giving to the main processing section. 2. The detecting means is means for recognizing the simultaneous transmission mode when a bit string at a predetermined position included in an address output by the main processing section shows a specific pattern. Collective panel device.