JPH05257789A - Input/output processor - Google Patents

Abstract

PURPOSE:To improve the performance of data transfer by providing a queue for registering addresses and data at the time of data transfer from a channel to a main storage device. CONSTITUTION:This device is provided with a data buffer 8 to store data transmitted from the channel for each channel, an address buffer 7 to store a transfer address (j) for each channel, a data transfer control circuit 6 to control data transfer, a request queue 2 to register the request of write to a main storage device 1, an address queue 3, a data queue 4 and a queue control circuit 5 to control these queues and when the data buffer 8 is made full as the result of transferring data, data can be continuously transferred without waiting the data transfer request from the channel by registering data on the data queue 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output processing device, and more particularly to a queue control circuit for controlling a data write request to a main storage device.

[0002]

2. Description of the Related Art Conventionally, an input / output processing device of this type has a request queue smaller than the number of channels holding a write request to a main memory and a data buffer holding transfer data from a plurality of channels for each channel. And an address buffer for holding a write address to the main memory for each channel, a data transfer control circuit for controlling the data buffer and the address buffer by a data transfer request and a channel number from a plurality of channels, and a request queue. And a queuing control circuit for controlling the registration and deletion of the.

[0003]

In the above-mentioned conventional input / output processing device, when data is transferred from one certain channel to be stored in the data buffer and the data buffer becomes full, the data is written to the main storage device. A write request to the main memory is registered in the request queue.
If data transfer is requested from the same channel before this registered write request is processed, the data transfer request from the channel is stored because the data buffer contains data that has not yet been written to main memory. Cannot be accepted. Therefore, there is a drawback that the performance of data transfer is lowered and the probability of occurrence of data overrun is increased.

[0004]

The input / output processing device of the present invention holds a request queue smaller than the number of channels holding write requests to the main memory and transfer data from a plurality of channels for each channel. A data buffer, an address buffer that holds a write address to the main memory for each channel, a data transfer control circuit that controls the data buffer and the address buffer according to a data transfer request and a channel number from a plurality of channels, and a request It is provided with an address queue and a data queue which respectively hold a write address and data corresponding to the queue, and a queue control circuit which controls registration and deletion of these queues.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. First, the configuration of this embodiment will be described.

The main memory 1 is connected to the system bus a, and data for data transfer from, for example, 32 channels is written therein. The request queue 2 is, for example, 4
It is a queue in which a batch of main memory 1 write requests can be registered. When a write request to the main memory 1 is registered by the queue control circuit 5, the main memory 1 is channeled to the main memory 1 via the system bus a. Of the data is requested, and when the writing to the main storage device 1 is completed, the write request is deleted.

The address queue 3 is a queue for holding the address of the main memory 1 to which data is to be written corresponding to the request queue 2, and is controlled by the queue control circuit 5. The data queue 4 is a queue that holds data to be written in the main storage device 1 corresponding to the request queue 2, and is controlled by the queue control circuit 5.

When the queue control circuit 5 receives a write request e from the data transfer control circuit 6 to the main memory device 1, the request queue 2 receives the main memory device 1 write request and the address queue 3 receives the address buffer 7. From the data buffer 8 is registered in the data queue 4. And the main storage device 1
When it finishes writing to, it removes them from each queue.

Upon receiving the data transfer request h and the channel number i from the channel, the data transfer post-generation circuit 6 stores the transfer data k from the channel in the area of the data buffer 8 corresponding to the channel. Further, the transfer address j of the main memory 1 into which this transfer data k is written is stored in the address buffer 7. When the data buffer 8 is full, a write request e to the main memory 1 is sent to the queue control circuit 5.

The address buffer 7 is a buffer for 32 channels which stores the transfer address j from the channel for each channel. The data buffer 8 is a buffer for 32 channels that stores the transfer data k from the channels for each channel.

Next, the operation of this embodiment will be described.

First, the channel number i is, for example, "1".
When receiving the data transfer request h from the channel, the data transfer control circuit 6 sends out the address buffer control signal f and the data buffer control signal g, and the address buffer 7
The transfer address j is stored in the area of the channel number "1" and the transfer data k is stored in the area of the channel number "1" of the data buffer 8. Then, when the area of the data buffer 8 becomes full, the data transfer control circuit 6 sends a write request e to the main storage device 1 to the queue control circuit 5.

Upon receiving the write request e, the queue control circuit 5 sends out a request queue control signal b, an address queue control signal c and a data queue control signal d, and registers the write request in the request queue 2. The address of the channel number "1" of the address buffer 7 is registered in the address queue 3, and the data of the channel number "1" of the data buffer 8 is registered in the data queue 4. After that, even if the data transfer request h is received from the channel with the channel number “1”, the areas of the channel numbers “1” of the address buffer 7 and the data buffer 8 are already registered in the address queue 3 and the data queue 4, respectively. Therefore, there is no need to wait for the data transfer.

[0015]

As described above, the input / output processing device of the present invention is connected to a channel by adding an address queue and a data queue for registering a write address and write data to the main memory. Data transfer performance is improved because there is no need to wait for data transfer.
This has the effect of reducing the probability of occurrence of data overrun.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 main memory 2 request queue 3 address queue 4 data queue 5 queue control circuit 6 data transfer control circuit 7 address buffer 8 data buffer a system bus b request queue control signal c address queue control signal d data queue Control signal e Write request f Address buffer control signal g Data buffer control signal h Data transfer request i Channel number j Transfer address k Transfer data

Claims (1)

[Claims] 1. An input / output processing device for transferring data from a plurality of channels to a main storage device, wherein the number of request queues is smaller than the number of channels holding write requests to the main storage device, and the plurality of channels. Buffer for holding the transfer data from each channel for each channel, an address buffer for holding the write address to the main memory for each channel, and the data buffer for the data transfer request and channel number from the plurality of channels. A data transfer control circuit for controlling the address buffer,
An input / output process comprising: an address queue and a data queue that respectively hold a write address and data corresponding to the request queue, and a queue control circuit that controls registration and deletion of each queue. apparatus.