JPH05257703A - Assembler device - Google Patents

Abstract

PURPOSE:To reduce the number of times for passing an optimizing processing and to shorten processing time by alternately executing optimization in the order from a smaller address and optimization in the order from a larger address. CONSTITUTION:The analysis of rows is executed by a source analysis processing 100 for preparing a bidirectional table, and the information of a branching instruction is set to a bidirectional branching instruction information table 104. On the other hand, after an input file is finished, a bidirectional optimizing processing 102 for optimizing the branching instruction is performed by a file end discrimination processing 101. Every time the branching instruction appears in a source program file, tables linked by a bidirectional chain having the information of the branching instruction is prepared and stored in a memory. Then, the optimization in the ascending order of addresses and the optimization in the descending order are performed and when any branching instruction to be affected by the number of opposite side bytes each other is present thereon, the instruction having the least number of bytes is generated in the third optimize processing so as to reduce the number of times for passing the optimizing processing up to from once to three time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in an assembler having branch instructions having different jump destination ranges with respect to the address where the branch instruction is located and the relative address up to the branch destination address. In particular, it relates to an assembler that performs a process of selecting an optimum branch instruction.

[0002]

2. Description of the Related Art In the conventional method, optimization processing is performed in the order of branch instructions having smaller addresses. FIG. 2 is a flowchart of an example of a conventional assembler processing method. FIG. 9 is a flow chart of an example of a conventional branch instruction information table creating process. 10 and 11 are flowcharts of an example of the conventional optimization processing method. In the case of forward reference (forward reference refers to a relationship in which the position of the branch instruction is located at the head side of the source program and the branch destination is located at the end side in the source program), from the branch instruction to the branch instruction If the number of bytes to the jump destination is 127 bytes or less, a 2-byte branch instruction is generated, and if it is 128 bytes or more, a 3-byte branch instruction is generated. In the case of a back reference (a back reference refers to a relationship in which the branch destination is located on the head side in the source program rather than the branch instruction), the absolute value of the number of bytes from the branch instruction to the jump destination of the branch instruction is 12
If it is 8 bytes or less, a 2-byte branch instruction is generated. If the absolute value is 129 bytes or more, an assembler that generates branch instructions for 3 bytes, and if the path analysis result of the path 1 source analysis processing 105 is a branch instruction as shown in FIG. Information on the branch instruction of FIG. 2 is set in the branch instruction information table 107.

FIG. 7 (a) is a diagram showing the connection of the branch instruction information table of FIG. FIG. 7B is a diagram illustrating the branch instruction information table of FIG. 2 in detail. The branch instruction information table 107 includes a chain pointer 440 that points to the next table in FIG. 7B, a branch instruction address 442, a chain pointer 443 that points to the symbol table, and a code increment 444.

In the address setting process 200 of the branch instruction shown in FIG. 9, the address next to the branch instruction is substituted into the variable add in the branch instruction information table 107 of FIG. In the address setting process 201 of the symbol table shown in FIG. 9, the address of the symbol table is assigned to the variable symp in the branch instruction information table 107 of FIG. Code increase amount setting processing 202
2 which is currently processing "1" as the initial value of the code increase amount indicating that it is uncertain whether to generate a 2-byte branch instruction or a 3-byte branch instruction. Substitute for the variable code in the information table 107. In the address setting process 203 of the next table, the next branch instruction information table is created, and the address of the created next branch instruction information table is assigned to the variable next. In the address setting process 205 of the current table, the chain pointer 401 pointing to the end of the last branch instruction information table in FIG. 7A is substituted for the address of the branch instruction information table currently being processed.

The path 1 source analysis process 105 shown in FIG. 2 is performed until the end of the file, and after the completion, an optimization process 106 for optimizing a branch instruction is performed. In the optimization process 106,
In the head address substitution processing 301 shown in FIG.
The chain pointer 400 pointing to the beginning of the branch instruction information table shown by is substituted into the variable cp, and the variable flag indicating that the branch instruction is fixed to 2 bytes or 3 bytes in the flag initialization processing 305 of FIG. 10 is initialized. Substitute "0" as the value. The variable c is determined by the increase amount determination process 306.
It is determined whether or not the branch instruction of the branch instruction information table 107 pointed to by p is determined to be a 2-byte branch instruction or a 3-byte branch instruction, and if determined, the branch instruction information table determination of FIG. Go to process 320. If not determined, how many branch instructions are to be the target of the optimization processing 106 of FIG. 2 from the beginning of the file to the branch instruction of the branch instruction information table pointed to by the variable cp by the increase amount calculation processing 307 up to the branch instruction of FIG. It is calculated whether or not there is, and the calculated number of branch instructions is substituted into the variable A.

Increasing amount calculation processing 30 up to the jump destination in FIG.
8, the number of branch instructions to be subjected to the optimization processing 106 in FIG. 2 is calculated from the head of the file to the jump destination of the branch instruction in the branch instruction information table pointed to by the variable cp, and the calculated number of branch instructions is set as a variable. Substitute in B. By the relative address substitution process 309 of FIG. 10, the variable c is changed from the jump destination address of the branch instruction of the branch instruction information table pointed to by the variable cp.
The address of the branch instruction in the branch instruction information table pointed to by p is subtracted, and is substituted into the variable mrl. Then, the symbol reference determination processing 310 determines whether the branch instruction in the branch instruction information table pointed to by the variable cp is forward reference or backward reference.

If the variable mrl is "0" or less, it is a backward reference, and if it is "1" or more, it is a forward reference. When the result of the symbol reference determination processing 310 is forward reference, the relative value is set to the variable minr and the processing 311 substitutes the variable mrl into the variable minr to set the code increase amount and the relative value to the variable m.
By setting processing 312 to axr, the variable mrl is set to the variable m.
Substitute inr, and increase the code and the relative value with the variable maxr
Is added to the variable mrl and the variable B by the set process 312, and the result of subtracting the variable A from the added result is the variable m.
Substitute in axr. In the case of back reference, the relative value is set to the variable maxr and the variable mrl is substituted for the variable maxr by the setting process 313, and the code increase amount and the relative value are set to the variable min.
The variable mrl and the variable B are added to r by the set processing 314, and the result of subtracting the variable A from the added result is substituted for the variable minr.

Next, a 2-byte branch instruction output determination process 315 and a 3-byte branch instruction output determination process 3 of FIG.
16 determines whether to generate a 2-byte branch instruction or a 3-byte branch instruction, and if a 3-byte branch instruction needs to be generated, a branch instruction address correction process 317 is performed. Variable bt from the branch instruction information table next to the branch instruction information table currently being processed by
"1" is added to the address of the branch instruction stored in the branch instruction information table pointed to by m. Flag setting process 31
In step 8, "1" is assigned to a variable flag indicating that the branch instruction is determined to be either 2 bytes or 3 bytes. Similarly, when it is decided to generate a 2-byte branch instruction, "1" is similarly substituted into the variable flag.

Further, "0" is substituted into the variable code indicating that the branch instruction of the branch instruction information table pointed to by the variable cp is fixed to 2 bytes or 3 bytes by the code increase amount setting process 319. Whether a branch instruction of 2 bytes or a branch instruction of 3 bytes occurs between the branch instruction of the branch instruction information table pointed to by the variable cp and the jump destination of the branch instruction of the branch instruction information table pointed to by the variable cp. When there is a definite branch instruction and all of the undecided branch instructions are 2-byte branch instructions, or when the branch instruction of the branch instruction information table pointed to by the variable cp is a 2-byte branch instruction. If all the branch instructions are the branch instructions for 3 bytes, and if the branch instructions in the branch instruction information table pointed to by the variable cp are the branch instructions for 3 bytes, the process proceeds to the branch instruction information table determination processing 320.

In the branch instruction information table determination processing 320, it is determined whether or not there is a branch instruction information table next to the branch instruction information table pointed to by the variable cp, and if there is, a pointer increment processing 321 branches the variable cp to the branch instruction information table. The size of the information table is added, the variable cp points to the next branch instruction information table, and the process proceeds to the increment determination process 306 of FIG. If there is no next branch instruction information table, it is determined by the flag determination processing 322 of FIG. 11 whether or not the variable flag indicating that the branch instruction has been determined to be 2 bytes or 3 bytes is “0”, If it is "1", there is a possibility that the optimization can still be performed, so the process returns to the head address substitution processing 301 in FIG. The variable flag is "0"
In the case of, the process proceeds to the symbol table correction process 323 of FIG. 11, and the symbol table correction process is performed.

Next, the optimization processing of the branch instruction will be described for the case where the file shown in FIG. 8 is input. At this time, the branch instruction information table shown in FIG. 7A is created. However, in FIG. 8, when the branch instruction is a 2-byte branch instruction, the number of bytes from the branch instruction to the jump destination of the branch instruction (jump destination address-branch instruction address) is the branch instruction branching to D. 12 (hereinafter, referred to as first branch instruction) 510 to jump destination D (hereinafter, referred to as first jump destination) 520 12
7 bytes, branch instruction branching to C (hereinafter referred to as second branch instruction) 511 to jump destination C (hereinafter referred to as second jump destination) 521 127 bytes, branch instruction branching to B (hereinafter referred to as third branch instruction) 512) to jump destination B (hereinafter, referred to as third jump destination) 522, 127 bytes, branch instruction for branching to A (hereinafter, referred to as fourth branch instruction) 513
To destination A (hereinafter referred to as the fourth destination) 523 to 1
20 bytes, a branch instruction for branching to H (hereinafter referred to as the fifth branch instruction) 514 to a jump destination H (hereinafter, referred to as the fifth jump destination) 524 is -128 bytes, a branch instruction for branching to G (hereinafter, the sixth branch instruction). From instruction 515 to destination G (hereinafter referred to as the sixth destination) 525, -128 bytes, F
Branch instruction for branching to (hereinafter referred to as the seventh branch instruction) 51
6 to jump destination F (hereinafter, referred to as the seventh jump destination) 526, -128 bytes, a branch instruction (hereinafter, referred to as the eighth branch instruction) 517 that branches to E, and jump destination E (hereinafter, referred to as the eighth jump destination) 527. Up to -128 bytes, branch instruction to branch to J (hereinafter referred to as the ninth branch instruction) 518 to jump to J
(Hereafter referred to as the ninth destination) 127 bytes up to 528,
Branch instruction for branching to I (hereinafter referred to as the tenth branch instruction) 5
From 19 to 529 (hereinafter referred to as the tenth destination) 529 is -128 bytes.

When the first branch instruction 510 of FIG. 8 appears as a result of inputting the source program file of FIG. 8 and analyzing the line in the path 1 source analysis processing 105 of FIG.
In the process of FIG. 9, the branch instruction information is set in the branch instruction information table 107 of FIG. In the address setting process 200 of the branch instruction of FIG. 9, the address next to the first branch instruction 510 of FIG. 8 is substituted into the variable add held in the branch instruction information table 430 of the first branch instruction 510 of FIG. 7A. In the address set processing 201 of the symbol table of FIG.
The address of the symbol table of the first jump destination 520 of the branch instruction information table 430 of the first branch instruction of FIG.
To the variable symp held by.

In the code increment setting process 202 of FIG. 9,
The branch of the first branch instruction of FIG. 7A is set with “1” indicating that it is uncertain whether to generate a branch instruction of 2 bytes or a branch instruction of 3 bytes, as an initial value of the code increase amount. It is assigned to the variable code of the instruction information table 430. Address set processing 203 of the next table in FIG.
Then, the next branch instruction information table is created, and the address of the created next branch instruction information table is stored in the variable next in the branch instruction information table 430 of the first branch instruction of FIG. 7A.
Substitute in t. In the address set processing 205 of FIG. 9, the branch instruction information table 430 of the first branch instruction of FIG.
Variable b that points to the address of the last branch instruction information table
Substitute for tm. With this, the branch instruction information table 430 of the first branch instruction of FIG. 7A is created. Similarly, the second branch instruction 511, the third branch instruction 512, the fourth branch instruction 513, the fifth branch instruction 514, the sixth branch instruction 515, the seventh branch instruction 516, the eighth branch instruction 517, and the The nine-branch instruction 518 and the tenth branch instruction 519 are performed, and each branch instruction information table is created. After completion, the optimization process 106 of FIG. 2 for optimizing the branch instruction is performed.

In the optimization processing 106 of FIG. 2, the chain pointer 4 pointing to the head of FIG. 7A pointing to the head of the branch instruction information table in the head address substitution processing 301 of FIG.
00 is assigned to the variable cp, and flag initialization processing 3 in FIG.
At 05, "0" is assigned as an initial value to a variable flag indicating that the branch instruction is fixed to 2 bytes or 3 bytes. The increment determination process 306 determines whether the first branch instruction 510 in FIG. 8 in the branch instruction information table pointed to by the variable cp is a 2-byte branch instruction or a 3-byte branch instruction. In this case, since it is not decided, the optimization of FIG. 2 is performed from the head of the file to the first branch instruction 510 of FIG. The number of branch instructions to be processed 106 is calculated, and the calculated number of branch instructions is assigned to the variable A. In this case, since only the first branch instruction 510 of its own in FIG. 8 is set, “1” is assigned to the variable A.

Increasing amount calculation processing 30 up to the jump destination in FIG.
8 from the head of the file to the first jump destination 520 of FIG. 8 which is the jump destination of the first branch instruction 510 of FIG. 8 in the branch instruction information table pointed to by the variable cp.
The number of branch instructions to be processed is calculated, and the calculated number of branch instructions is assigned to the variable B. In this case,
The first branch instruction 510, the second branch instruction 511, the third branch instruction 512, and the fourth branch instruction 513 of
Substitute “4” into variable B. By the relative address assignment process 309 of FIG. 10, the first of the branch instruction information table pointed to by the variable cp from the address of the first jump destination 520 which is the jump destination of the first branch instruction 510 of FIG. The address of the branch instruction 510 is subtracted, and the variable m
Substitute for rl. In this case, 127 bytes, so "1
27 ”is substituted into the variable mrl.

Then, the symbol reference determination process 3 of FIG.
8 of the branch instruction information table pointed to by the variable cp by 10
It is determined whether the first branch instruction 510 of is a forward reference or a backward reference. In this case, since it is a forward reference, the relative value of FIG.
rl is substituted into the variable minr, the code increase amount and the relative value are set into the variable maxr, the variable mrl and the variable B are added by the setting processing 312, and the result of subtracting the variable A from the added result is substituted into the variable maxr. In this case, "127" is assigned to the variable minr and "130" is assigned to the variable maxr.

Next, the 2-byte branch instruction output discrimination processing 315 and the 3-byte branch instruction output discrimination processing 3 of FIG.
With 16, it is determined whether to generate a branch instruction for 2 bytes or a branch instruction for 3 bytes. In this case, since the variable maxr is "130", the condition of the 2-byte branch instruction output determination process 315 is not satisfied, and the process proceeds to the 3-byte branch instruction output determination process 316. Variable max
Since r is “130” and the variable minr is “127”, the condition of the branch instruction output determination process 316 for 3 bytes is satisfied and whether a branch instruction for 2 bytes or a branch instruction for 3 bytes is generated. Is not determined, the process proceeds to the branch instruction information table discrimination processing 320.

In the branch instruction information table determination processing 320, it is determined whether or not there is a branch instruction information table next to the branch instruction information table pointed to by the variable cp. In this case, since the next branch instruction information table exists, the process proceeds to pointer increment processing 321 and the size of the branch instruction information table is added to the variable cp so that the variable cp points to the next branch instruction information table. 8 and performs the same processing as the first branch instruction 510 on the second branch instruction 511 and the third branch instruction 512 of FIG.

Second branch instruction 511 and third branch instruction 5
Similarly to the first branch instruction 510, 12 also does not decide whether to generate a 2-byte branch instruction or a 3-byte branch instruction. Next, the fourth branch instruction 513 is processed. Figure 10
It is determined whether the fourth branch instruction 513 in FIG. 8 in the branch instruction information table pointed to by the variable cp is a 2-byte branch instruction or a 3-byte branch instruction. In this case, since it has not been confirmed,
By the increase amount calculation processing 307 up to the branch instruction of 0, the optimization processing 106 of FIG. 2 is performed from the beginning of the file to the fourth branch instruction 513 of FIG.
The number of branch instructions to be processed is calculated, and the calculated number of branch instructions is assigned to the variable A. In this case,
The first branch instruction 510, the second branch instruction 511, the third branch instruction 512, and the fourth branch instruction 513 of
Substitute "4" for variable A.

Increase amount calculation processing 30 up to the jump destination in FIG.
8 shows how many branch instructions to be subjected to the optimization processing 106 of FIG. 2 from the head of the file to the fourth jump destination 523 which is the jump destination of the fourth branch instruction 513 of FIG. 8 from the branch instruction information table pointed to by the variable cp. It is calculated whether it exists, and the calculated number of branch instructions is substituted into the variable B. In this case, the first branch instruction 510, the second branch instruction 511, and the third branch instruction 5 of FIG.
Since there are four of 12 and the fourth branch instruction 513, “4” is assigned to the variable B. Relative address substitution process 30 of FIG.
9. The address of the fourth branch instruction 513 of the branch instruction information table pointed to by the variable cp is subtracted from the address of the fourth jump destination 523 of the fourth branch instruction 513 of FIG. And assign it to the variable mrl. In this case, since it is 120 bytes, "120" is assigned to the variable mrl, and the symbol reference determination process 3 in FIG.
8 of the branch instruction information table pointed to by the variable cp by 10
It is determined whether the fourth branch instruction 513 is a forward reference or a backward reference. In this case, since it is a forward reference, the variable mrl is changed to the variable min by the calculation amount setting process 311 in FIG.
Substituting in r, the code increase amount and the relative value are set in the variable maxr, and the variable mrl and the variable B are added by the processing 312.
The result of subtracting the variable A from the result of addition is the variable maxr
To. In this case, "120" is assigned to the variable minr and "120" is assigned to the variable maxr.

Next, the 2-byte branch instruction output discrimination processing 315 and the 3-byte branch instruction output discrimination processing 3 of FIG.
With 16, it is determined whether to generate a branch instruction for 2 bytes or a branch instruction for 3 bytes. In this case, since both the variable minr and the variable maxr are “120”, the condition of the branch instruction output determination process 315 for 2 bytes is satisfied, and the process proceeds to the flag set process 318. In the flag setting process 318, since it is decided that the fourth branch instruction 513 of FIG. 8 generates a branch instruction for 2 bytes, a variable fla indicating that it is decided for 2 bytes or 3 bytes.
Substitute “1” for g.

Further, "0" is assigned to the variable code indicating that the branch instruction of the branch instruction information table pointed to by the variable cp is fixed to 2 bytes or 3 bytes by the code increment setting process 319 of FIG. The process proceeds to the branch instruction information table discrimination processing 320. In the branch instruction information table determination processing 320, it is determined whether or not there is a branch instruction information table next to the branch instruction information table pointed to by the variable cp. In this case, since the next branch instruction information table exists, the process proceeds to the pointer increment processing 321 and the variable c
The size of the branch instruction information table is added to p, and the variable c
10 so that p points to the next branch instruction information table.
Then, the process proceeds to the increase amount determination processing 306.

In the increase amount determination processing 306, it is determined whether the fifth branch instruction 514 of FIG. 8 in the branch instruction information table pointed to by the variable cp is determined to be a 2-byte branch instruction or a 3-byte branch instruction. .. In this case, since it has not been decided, the increase amount calculation process 3 up to the branch instruction in FIG.
The number of branch instructions to be subjected to the optimization process 106 of FIG. 2 is calculated from 07 from the head of the file to the fifth branch instruction 514 of FIG. 8 of the branch instruction information table pointed to by the variable cp, and the calculated branch Substitute the number of instructions into variable A. In this case, the first branch instruction 510, the second branch instruction 511, the third branch instruction 512 and the fifth branch instruction 51 of FIG.
Since there are four of them, "4" is assigned to the variable A.

Increasing amount calculation processing 30 up to the jump destination in FIG.
8 shows how many branch instructions to be subjected to the optimization process 106 of FIG. It is calculated whether or not there is, and the calculated number of branch instructions is substituted into the variable B. In this case, since the first branch instruction 510, the second branch instruction 511, the third branch instruction 512, and the fifth branch instruction 514 in FIG.
Is substituted into the variable B.

The branch instruction information table pointed to by the variable cp from the address of the fifth jump destination 524 which is the jump destination of the fifth branch instruction 514 shown in FIG. The address of the fifth branch instruction 514 is subtracted and is substituted into the variable mrl. In this case, since it is -128 bytes, "-128" is assigned to the variable mrl.

Then, the symbol reference determination process 3 of FIG.
8 of the branch instruction information table pointed to by the variable cp by 10
It is determined whether the branch instruction 514 of (1) is a forward reference or a backward reference. In this case, since it is a backward reference, the relative value of FIG.
Is assigned to the variable maxr, the code increase amount and the relative value are set to the variable minr, the variable mrl and the variable B are added by the setting process 314, and the result of subtracting the variable A from the added result is assigned to the variable minr. In this case, "-128" is assigned to the variable minr, and "-128" is assigned to the variable maxr.
Is substituted.

Next, a 2-byte branch instruction output determination process 315 and a 3-byte branch instruction output determination process 3 of FIG.
With 16, it is determined whether to generate a branch instruction for 2 bytes or a branch instruction for 3 bytes. In this case, since the variables maxr and minr are both "-128", the condition of the 2-byte branch instruction output determination processing 315 is satisfied, and it is decided that the 2-byte branch instruction is generated, and the flag is set. Go to processing 318. In the flag setting process 318, since it is determined that the fifth branch instruction 514 of FIG. 8 generates a branch instruction of 2 bytes, "1" is assigned to the variable flag indicating that it is determined to be 2 bytes or 3 bytes. To do.

Further, "0" is assigned to the variable code indicating that the branch instruction of the branch instruction information table pointed to by the variable cp is fixed to 2 bytes or 3 bytes by the code increase amount setting processing 319 of FIG. The process proceeds to the branch instruction information table discrimination processing 320. In the branch instruction information table determination processing 320, it is determined whether or not there is a branch instruction information table next to the branch instruction information table pointed to by the variable cp. In this case, since the next branch instruction information table exists, the process proceeds to the pointer increment processing 321 and the variable c
The size of the branch instruction information table is added to p, and the variable c
10 so that p points to the next branch instruction information table.
Of the sixth branch instruction 5 of FIG.
15, the seventh branch instruction 516 and the eighth branch instruction 517 are processed in the same manner as the fifth branch instruction 514. The sixth branch instruction 515 and the sixth jump destination 525 do not have a branch instruction to be subjected to the optimization processing 106 of FIG. 2 and the address of the sixth branch instruction 515 is subtracted from the address of the sixth jump destination 525. Since the value obtained is "-128" or more, the sixth branch instruction is determined to generate a 2-byte branch instruction.

Seventh branch instruction 516 and eighth branch instruction 5
Similarly to the sixth branch instruction, 17 is also determined to generate a 2-byte branch instruction.

Next, the processing of the ninth branch instruction 518 and the tenth branch instruction 519 are performed. Between the ninth branch instruction 518 and the ninth jump destination 528 is the tenth branch instruction 519 that is the target of the optimization processing 106 of FIG. 2 and the tenth branch instruction 519 is determined to be a 2-byte branch instruction. If the ninth branch instruction 518 is determined to be a 2-byte branch instruction, and if the tenth branch instruction 519 is determined to be a 3-byte branch instruction, the ninth branch instruction 518 is also determined to be a 3-byte branch instruction. So
If the tenth branch instruction 519 is not determined, the ninth branch instruction 518
Is not confirmed. Similarly, for the tenth branch instruction 519, if the ninth branch instruction 518 is not determined, it is not determined whether to generate a 2-byte branch instruction or a 3-byte branch instruction.

When the processing up to the tenth branch instruction 519 is completed, the flow proceeds to flag determination processing 322. In the flag determination processing 322, when it is determined whether to generate a branch instruction for 2 bytes or a branch instruction for 3 bytes, it is determined whether the variable flag set to "1" is "1". To do. If the variable flag is "1", it means that there is a branch instruction that determines whether a 2-byte branch instruction or a 3-byte branch instruction is generated, and a 2-byte branch instruction is generated. Whether a branch instruction for 2 bytes or a branch instruction for 3 bytes has been determined so far. Whether a branch instruction for bytes or a branch instruction for 3 bytes could not be determined can be determined for a branch instruction that generates a branch instruction for 2 bytes or a branch instruction for 3 bytes. Therefore, the process proceeds to the head address substitution processing 301. This is the first time Figure 2
The optimization process 106 of ends.

The branch instructions decided to generate a 2-byte branch instruction are the fourth branch instruction 513, the fifth branch instruction 514, the sixth branch instruction 515, and the seventh branch instruction 51 in FIG.
6 and the eighth branch instruction 517. Next, the second optimization processing 106 of FIG. 2 is performed. Between the third branch instruction 512 and the third jump destination 522 of FIG. 8, the optimization process 1 of FIG.
No target branch instruction of 06 exists and the third jump destination 5
Since the value of "22" or less is obtained by subtracting the address of the third branch instruction 512 from the address of 22, the third branch instruction is determined to generate a 2-byte branch instruction. When the third optimization process 106 of FIG. 2 is performed, there is no branch instruction to be the optimization process 106 of FIG. 2 between the second branch instruction 511 and the second jump destination 521 of FIG. Since the value obtained by subtracting the address of the second branch instruction 511 from the address of the second jump destination 521 is "127" or less, the second branch instruction is determined to generate a branch instruction of 2 bytes.

When the optimization process 106 of FIG. 2 is performed a fourth time, there is a branch instruction to be the optimization process 106 of FIG. 2 between the first branch instruction 510 and the first jump destination 520 of FIG. Since the value obtained by subtracting the address of the first branch instruction 510 from the address of the first jump destination 520 is "127" or less, the first branch instruction 510 is determined to generate a 2-byte branch instruction. ..

In the fifth optimization processing 106 of FIG. 2, the first branch instruction 510 of FIG. 8 in the branch instruction information table pointed to by the variable cp is the branch instruction of 2 bytes or not by the increase amount determination processing 306 of FIG. It is determined whether the branch instruction for 3 bytes is fixed. In this case, since it has been decided, the process proceeds to the branch instruction information table discrimination processing 320 of FIG. In the branch instruction information table determination processing 320, it is determined whether or not there is a branch instruction information table next to the branch instruction information table pointed to by the variable cp. In this case, since the first branch instruction 510 of FIG. 8 is not the last branch instruction, the procedure proceeds to the pointer increment processing 321 of FIG. 11, and the variable cp is added with the size of the branch instruction information table, and the variable cp is the next branch instruction. The process proceeds to the increase amount determination processing 306 of FIG. 10 by pointing to the information table.

The second branch instruction 511, the third branch instruction 512, the fourth branch instruction 513, the fifth branch instruction 514, the sixth branch instruction 515, the seventh branch instruction 516 and the eighth branch instruction 517 of FIG. Similar to the branch instruction 510, since the branch instruction for 2 bytes or the branch instruction for 3 bytes is determined, the same processing as the first branch instruction 510 is repeated.

Next, if the tenth branch instruction 519 is not determined to be either a 2-byte branch instruction or a 3-byte branch instruction, the ninth branch instruction 518 is a 2-byte branch instruction or a 3-byte branch instruction. It is not possible to determine whether it is a minute branch instruction. Similarly, if the ninth branch instruction 518 is not determined to be a 2-byte branch instruction or a 3-byte branch instruction, then the 10th branch instruction 519 is a 2-byte branch instruction or a 3-byte branch instruction. I can't confirm. In the optimization process 106 of FIG. 2 for the fifth time, the variable flag is “0” because there is no confirmed branch instruction in either the 2-byte branch instruction or the 3-byte branch instruction. Since the variable flag is "0" by the flag determination processing 322 of FIG. 11, the processing proceeds to the symbol table correction processing 323. Since the symbol table correction processing 323 has determined the symbol value on the assumption that a 2-byte branch instruction is generated when the symbol table is created, the branch instruction determined to generate a 3-byte branch instruction is If there is, a process of adding to the address value of the symbol for the number of times the branch instruction for 3 bytes is generated is performed. The optimization process 106 of FIG. 2 is completed at the fifth time.

In another conventional method, the optimization processing is performed in the order of the branch instruction having the smallest branch instruction address.
FIG. 13 is a flowchart of an example of a conventional assembler processing method. FIG. 22 is a flow chart of an example of a conventional branch instruction information table creating process. 23 and 24 are flowcharts of an example of a conventional optimization processing method.

In the case of forward reference, if the number of bytes from the branch instruction to the jump destination of the branch instruction is 127 bytes or less, a 2-byte branch instruction is generated, and if it is 128 bytes or more, a 3-byte branch instruction is generated. Absolute value of the number of bytes from the branch instruction to the jump destination of the branch instruction 12
If it is 8 bytes or less, a branch instruction for 2 bytes is generated,
If the absolute value is 129 bytes or more, it is an assembler that generates a branch instruction for 3 bytes.
If the line analysis result in the source analysis processing 105 is a branch instruction, the information of the branch instruction of FIG. 13 is set in the branch instruction information table 107 in the processing of FIG. FIG. 20 (a) is shown in FIG.
5 is a diagram showing the connection of tables of the branch instruction information table of FIG. FIG. 20B is a diagram illustrating the branch instruction information table of FIG. 13 in detail.

The branch instruction information table 107 is shown in FIG.
Chain pointer 440 that points to the table next to (b)
, A branch instruction address 442, a chain pointer 443 pointing to the symbol table, and a code increment 444. In the address setting process 200 of the branch instruction shown in FIG. 22, the variable a in the branch instruction information table 107 of FIG. 13 which is currently processing the next address of the branch instruction.
Substitute in dd. In the symbol table address set processing 201 shown in FIG. 22, the branch instruction information table 107 of FIG.
To the variable symp at.

In the code increment setting process 202, "1" is currently set as the initial value of the code increment indicating that it is uncertain whether to generate a branch instruction for 2 bytes or a branch instruction for 3 bytes. It is assigned to the variable code in the branch instruction information table 107 of FIG. 13 being processed. In the address setting process 203 of the next table, the next branch instruction information table is created, and the address of the created next branch instruction information table is assigned to the variable next. In the address setting process 205 of the current table, the address of the branch instruction information table currently being processed is assigned to the chain pointer 401 pointing to the end of the branch instruction information table of FIG.

Path 1 source analysis processing 105 shown in FIG.
Is executed to the end of the file, and after the completion, the optimization process 106 for optimizing the branch instruction is executed. In the optimization process 106, the start address substitution process 301 shown in FIG.
The chain pointer 400 that points to the beginning of the branch instruction information table shown in (a) is assigned to the variable cp, and the branch instruction corresponds to 2 bytes or 3 in the flag initialization processing 305 of FIG.
As the initial value, "0" is substituted into the variable flag indicating that it has been determined in bytes.

The increase amount determination processing 306 determines whether the branch instruction of the branch instruction information table 107 indicated by the variable cp is a 2-byte branch instruction or a 3-byte branch instruction, and is determined. If so, the process proceeds to the branch instruction information table determination processing 320 of FIG. If not determined, how many branch instructions are subject to the optimization processing 106 in FIG. 13 from the head of the file to the branch instruction in the branch instruction information table pointed to by the variable cp by the increase amount calculation processing 307 up to the branch instruction in FIG. It is calculated whether or not there is, and the calculated number of branch instructions is substituted into the variable A. From the beginning of the file to the jump destination of the branch instruction in the branch instruction information table pointed to by the variable cp by the increase amount calculation processing 308 to the jump destination in FIG.
The number of branch instructions to be the target of the optimization processing 106 of 3 is calculated, and the calculated number of branch instructions is substituted into the variable B.

By the relative address assignment processing 309 of FIG. 23, the address of the branch instruction of the branch instruction information table pointed to by the variable cp is subtracted from the address of the branch instruction jump destination of the branch instruction information table pointed to by the variable cp, and assigned to the variable mrl. To do. Then, the variable c is determined by the symbol reference determination processing 310.
It is determined whether the branch instruction in the branch instruction information table pointed to by p is forward reference or backward reference. If the variable mrl is "0" or less, it is backward reference, and if it is "1" or more, it is forward reference. When the result of the symbol reference determination processing 310 is forward reference, the relative value is set in the variable minr, the variable mrl is substituted in the variable minr by the processing 311, and the code increase amount and the relative value are set in the variable maxr 312.
The variable mrl is substituted into the variable minr by and the variable mrl and the variable B are added to the variable maxr by the setting process 312, and the result of subtracting the variable A from the addition result is set to the variable maxr. substitute.

In the case of back reference, the relative value is set to the variable ma.
The variable mrl is set to the variable max by the setting process 313 in which xr is set.
Substituting for r, the code increase amount and the relative value are set to the variable minr by the setting process 314, the variable mrl and the variable B are added, and the result of subtracting the variable A from the added result is the variable mi.
Substitute in nr.

Next, the 2-byte branch instruction output discrimination processing 315 and the 3-byte branch instruction output discrimination processing 3 of FIG.
16 determines whether to generate a 2-byte branch instruction or a 3-byte branch instruction, and if a 3-byte branch instruction needs to be generated, a branch instruction address correction process 317 is performed. Variable bt from the branch instruction information table next to the branch instruction information table currently being processed by
"1" is added to the address of the branch instruction stored in the branch instruction information table pointed to by m. Flag setting process 31
In step 8, "1" is assigned to a variable flag indicating that the branch instruction is determined to be either 2 bytes or 3 bytes. Similarly, when it is decided to generate a 2-byte branch instruction, "1" is similarly substituted into the variable flag. further,
By the code increase amount setting process 319, "0" is assigned to the variable code indicating that the branch instruction of the branch instruction information table pointed to by the variable cp is fixed to 2 bytes or 3 bytes.

A branch instruction of 2 bytes or a branch instruction of 3 bytes is provided between the branch instruction of the branch instruction information table pointed to by the variable cp and the jump destination of the branch instruction of the branch instruction information table pointed to by the variable cp. Or there are uncertain branch instructions and all uncertain branch instructions have become 2-byte branch instructions, or when the branch instruction in the branch instruction information table pointed to by the variable cp becomes 2-byte branch instructions. Further, when all the undefined branch instructions become branch instructions of 3 bytes, when the branch instruction of the branch instruction information table pointed to by the variable cp becomes a branch instruction of 3 bytes, the branch instruction information table discrimination processing 320 Go to. In the branch instruction information table determination processing 320, it is determined whether or not there is a branch instruction information table next to the branch instruction information table pointed to by the variable cp. If there is, the pointer increment processing 321 sets the variable cp to the branch instruction information table. The size is added, the variable cp points to the next branch instruction information table, and the process proceeds to the increase amount determination processing 306 in FIG.

If there is no next branch instruction information table,
A variable fla indicating that the branch instruction has been fixed to 2 bytes or 3 bytes by the flag determination processing 322 of FIG.
It is determined whether or not g is "0", and if it is "1", there is a possibility that optimization can still be performed, so the process returns to the head address substitution processing 301 of FIG. When the variable flag is "0", the process proceeds to the symbol table correction process 323 of FIG. 24, and the symbol table correction process is performed.

Next, the optimization processing of the branch instruction will be described for the case where the file shown in FIG. 21 is input. At this time, the branch instruction information table shown in FIG. 20A is created. However, in FIG. 21, when the branch instruction is a 2-byte branch instruction, the number of bytes from the branch instruction to the jump destination of the branch instruction (jump destination address-branch instruction address) is
127 bytes from the first branch instruction 510 to the first jump destination 520, 1 from the second branch instruction 511 to the second jump destination 521
27 bytes, third branch instruction 512 to third jump destination 522
Up to 127 bytes, 120 bytes from the fourth branch instruction 513 to the fourth jump destination 523, -128 bytes from the fifth branch instruction 514 to the fifth jump destination 524, the sixth branch instruction 515
To the sixth jump destination 525 -128 bytes, the seventh branch instruction 516 to the seventh jump destination 526 -128 bytes, the eighth branch instruction 517 to the eighth jump destination 527 -128 bytes, the ninth branch instruction 518 to the 9 up to 528 1
27 bytes, 10th branch instruction 519 to 1029th destination 529
Up to -128 bytes.

When the source program file of FIG. 21 is input and the first branch instruction 510 of FIG. 21 appears as a result of line analysis in the path 1 source analysis processing 105 of FIG. 13, a branch instruction is executed in the processing of FIG. Information is set in the branch instruction information table 107 of FIG. In the address setting process 200 of the branch instruction of FIG. 22, the first branch instruction 5 of FIG.
The address next to 10 is set to the first branch instruction 51 in FIG.
It is assigned to the variable add of the branch instruction information table 430 of 0. In the address setting process 201 of the symbol table of FIG. 22, the address of the symbol table of the first jump destination 520 of FIG. 21 is assigned to the variable symp of the branch instruction information table 430 of the first branch instruction of FIG.
In the code increase amount setting process 202 of FIG. 22, "1" indicating whether to generate a 2-byte branch instruction or a 3-byte branch instruction is undetermined is set as the initial value of the code increase amount, and It is substituted into the variable code held in the branch instruction information table 430 of the first branch instruction in FIG. Figure 2
The address of the next branch instruction information table created in the address setting process 203 of the table next to No. 2 is the branch instruction information table 430 of the first branch instruction of FIG. Substitute for the variable next.

In the address setting process 205 of FIG. 22, the branch instruction information table 43 of the first branch instruction of FIG.
The address of 0 is assigned to the variable btm that points to the last branch instruction information table. With this, the branch instruction information table 430 of the first branch instruction of FIG. 20A is created. Similarly, the second branch instruction 511 and the third branch instruction 51 of FIG.
2, fourth branch instruction 513, fifth branch instruction 514, sixth branch instruction 515, seventh branch instruction 516, eighth branch instruction 51
7, the ninth branch instruction 518 and the tenth branch instruction 519 are performed, and each branch instruction information table is created. Optimization process 10 of FIG. 13 for optimizing the branch instruction after completion.
Do 6.

In the optimization process 106 of FIG. 13, the chain pointer 400 that points to the beginning of the branch instruction information table in FIG. 20A is assigned to the variable cp in the beginning address assignment process 301 of FIG. In the flag initialization processing 305 of 23, the variable “flag” indicating that the branch instruction is fixed to 2 bytes or 3 bytes is set to “0” as an initial value.
Is substituted. By the increase amount determination processing 306, the first branch instruction 51 of FIG. 21 in the branch instruction information table pointed to by the variable cp.
It is determined whether 0 is a 2-byte branch instruction or a 3-byte branch instruction. In this case, since it has not been decided, by the increase amount calculation processing 307 up to the branch instruction of FIG. 23, the optimum of FIG. The number of branch instructions that are subject to the conversion process 106 is calculated, and the calculated number of branch instructions is substituted into the variable A. In this case, since it is only the first branch instruction 510 of its own in FIG. 21, "1" is assigned to the variable A.

Increase amount calculation processing 30 up to the jump destination in FIG.
8. From the beginning of the file to the first jump destination 520 of FIG. 21, which is the jump destination of the first branch instruction 510 of FIG. 21, in the branch instruction information table pointed to by the variable cp, which is the target of the optimization process 106 of FIG. The number of instructions existing is calculated, and the calculated number of branch instructions is substituted into the variable B. In this case, the first branch instruction 510 and the second branch instruction 51 of FIG.
1, 4 of the third branch instruction 512 and the fourth branch instruction 513
Since it is a piece, "4" is substituted into the variable B. By the relative address substitution processing 309 of FIG. 23, the first of the branch instruction information table pointed to by the variable cp from the address of the first jump destination 520 which is the destination of the first branch instruction 510 of FIG. The address of the branch instruction 510 is subtracted and substituted into the variable mrl. In this case, since it is 127 bytes, "127" is substituted for the variable mrl.

Then, the symbol reference discrimination processing 3 of FIG.
2 of the branch instruction information table pointed to by the variable cp by 10
It is determined whether the first branch instruction 510 of 1 is a forward reference or a backward reference. In this case, since it is a forward reference, FIG.
The relative value of is set to the variable minr by the setting process 311 and the variable mrl is substituted into the variable minr. The code increase amount and the relative value are set to the variable maxr by the setting process 312. The result of the subtraction is substituted into the variable maxr. In this case, the variable minr
“127” is substituted into, and “130” is substituted into the variable maxr.

Next, the 2-byte branch instruction output determination processing 315 and the 3-byte branch instruction output determination processing 3 of FIG.
With 16, it is determined whether to generate a branch instruction for 2 bytes or a branch instruction for 3 bytes. In this case, since the variable maxr is "130", the condition of the 2-byte branch instruction output determination process 315 is not satisfied, and the process proceeds to the 3-byte branch instruction output determination process 316.

The variable maxr is "130" and the variable minr
Is 127, the condition of the branch instruction output determination process 316 for 3 bytes is satisfied, and it is not determined whether the branch instruction for 2 bytes or the branch instruction for 3 bytes is generated. Proceed to the discrimination processing 320.
In the branch instruction information table determination processing 320, it is determined whether or not there is a branch instruction information table next to the branch instruction information table pointed to by the variable cp. In this case, since the next branch instruction information table exists, the process proceeds to the pointer increment processing 321, and the size of the branch instruction information table is added to the variable cp so that the variable cp points to the next branch instruction information table. 21 and the third branch instruction 5 of FIG. 21.
The same processing as that of the first branch instruction 510 is performed for 12.

Second branch instruction 511 and third branch instruction 5
Similarly to the first branch instruction 510, 12 also does not determine whether to generate a 2-byte branch instruction or a 3-byte branch instruction. Next, the fourth branch instruction 513 is processed. Figure 2
By the increase amount determination processing 306 of 3, it is determined whether the fourth branch instruction 513 in FIG. 21 of the branch instruction information table pointed to by the variable cp is a 2-byte branch instruction or a 3-byte branch instruction. . In this case, since it has not been decided, the optimization of FIG. 13 is performed from the head of the file to the fourth branch instruction 513 of FIG. 21 in the branch instruction information table pointed to by the variable cp by the increase amount calculation processing 307 up to the branch instruction of FIG. The number of branch instructions to be processed 106 is calculated, and the calculated number of branch instructions is assigned to the variable A.
In this case, the first branch instruction 510 and the second branch instruction 5 in FIG.
Since there are four, 11, the third branch instruction 512 and the fourth branch instruction 513, “4” is assigned to the variable A.

Increase amount calculation processing 30 up to the jump destination in FIG.
The number of branch instructions to be subjected to the optimization process 106 in FIG. 13 is determined from the head of the file to the fourth jump destination 523 in the branch instruction information table pointed to by the variable cp, which is the jump destination of the fourth branch instruction 513 in FIG. It is calculated whether or not there is, and the calculated number of branch instructions is substituted into the variable B. In this case,
Since the first branch instruction 510, the second branch instruction 511, the third branch instruction 512, and the fourth branch instruction 513 of 1 are four,
Substitute “4” into variable B.

The branch instruction information table pointed to by the variable cp from the address of the fourth jump destination 523 which is the jump destination of the fourth branch instruction 513 in FIG. 21 in the branch instruction information table pointed to by the variable cp by the relative address assignment processing 309 in FIG. The address of the fourth branch instruction 513 is subtracted and substituted into the variable mrl. In this case, since it is 120 bytes, "120" is assigned to the variable mrl, and the symbol reference determination processing 310 of FIG.
It is determined whether the fourth branch instruction 513 of FIG. 21 in the branch instruction information table pointed to by the variable cp is forward reference or backward reference. In this case, since it is a forward reference, the variable mrl is changed to the variable minr by the calculation amount setting process 311 of FIG.
, The code increase amount and the relative value are set to the variable maxr by the setting process 312, the variable mrl and the variable B are added, and the result of subtracting the variable A from the added result is substituted for the variable maxr. In this case, "120" is assigned to the variable minr and "120" is assigned to the variable maxr.

Next, the 2-byte branch instruction output determination process 315 and the 3-byte branch instruction output determination process 3 of FIG.
With 16, it is determined whether to generate a branch instruction for 2 bytes or a branch instruction for 3 bytes. In this case, since the variables minr and maxr are both “120”, the condition of the branch instruction output determination process 315 for 2 bytes is satisfied, and the process proceeds to the flag setting process 318. In the flag setting process 318, it is decided that the fourth branch instruction 513 of FIG. 21 generates a branch instruction of 2 bytes, and therefore, a variable fla indicating that it is decided to be 2 bytes or 3 bytes.
Substitute “1” for g. Further, "0" is assigned to the variable code indicating that the branch instruction of the branch instruction information table pointed to by the variable cp is fixed to 2 bytes or 3 bytes by the code increase amount setting processing 319 of FIG. The process proceeds to the table determination process 320.

In the branch instruction information table determination processing 320, it is determined whether or not there is a branch instruction information table next to the branch instruction information table pointed to by the variable cp. In this case, since the next branch instruction information table exists, the process proceeds to the pointer increment processing 321, the variable cp is added with the size of the branch instruction information table, and the variable cp points to the next branch instruction information table. 23, the process proceeds to the increase amount determination process 306.

The fifth branch instruction 514 of FIG. 21 in the branch instruction information table pointed to by the variable cp by the increase amount determination processing 306.
Is determined to be a 2-byte branch instruction or a 3-byte branch instruction. In this case, since it has not been decided, the optimization of FIG. 13 is performed from the head of the file to the fifth branch instruction 514 of FIG. The number of branch instructions to be processed 106 is calculated, and the calculated number of branch instructions is assigned to the variable A. In this case, there are four first branch instruction 510, second branch instruction 511, third branch instruction 512, and fifth branch instruction 514 in FIG. 21, so “4” is assigned to variable A.

Increase amount calculation processing 30 up to the jump destination in FIG.
The number of branch instructions subject to the optimization process 106 of FIG. 13 from the head of the file to the fifth jump destination 524 which is the jump destination of the fifth branch instruction 514 of FIG. It is calculated whether or not there is, and the calculated number of branch instructions is substituted into the variable B. In this case,
Since the first branch instruction 510, the second branch instruction 511, the third branch instruction 512, and the fifth branch instruction 514 of 1 are four,
Substitute “4” into variable B.

The branch instruction information table pointed to by the variable cp from the address of the fifth jump destination 524, which is the jump destination of the fifth branch instruction 514 shown in FIG. 21, in the branch instruction information table pointed to by the variable cp by the relative address substitution processing 309 shown in FIG. The address of the fifth branch instruction 514 is subtracted and is substituted into the variable mrl. In this case, since it is -128 bytes, "-128" is assigned to the variable mrl. Then, the symbol reference determination processing 310 of FIG. 23 determines whether the branch instruction 514 of FIG. 21 in the branch instruction information table pointed to by the variable cp is a forward reference or a backward reference. In this case it's a back reference, so
The result of adding the relative value in FIG. 23 to the variable maxr by substituting the variable mrl into the variable maxr by the setting processing 313, adding the code increase amount and the relative value to the variable minr by the setting processing 314, and adding the variable mrl and the variable B. The result of subtracting the variable A from is substituted into the variable minr. In this case, "-128" is assigned to the variable minr, and "-128" is assigned to the variable maxr.

Next, the 2-byte branch instruction output determination processing 315 and the 3-byte branch instruction output determination processing 3 of FIG.
With 16, it is determined whether to generate a branch instruction for 2 bytes or a branch instruction for 3 bytes. In this case, since the variables maxr and minr are both "-128", the condition of the 2-byte branch instruction output determination processing 315 is satisfied, and it is decided that the 2-byte branch instruction is generated, and the flag is set. Go to processing 318.

In the flag setting process 318, it is decided that the fifth branch instruction 514 of FIG. 21 generates a branch instruction for 2 bytes, so that the variable flag indicating that it is decided for 2 bytes or 3 bytes is "1". Is substituted. Furthermore, a variable code indicating that the branch instruction of the branch instruction information table pointed to by the variable cp is fixed to 2 bytes or 3 bytes by the code increase amount setting process 319 of FIG.
Substitute “0” for the branch instruction information table determination process 32.
Go to 0. In the branch instruction information table discrimination processing 320,
It is determined whether or not there is a branch instruction information table next to the branch instruction information table pointed to by the variable cp. In this case, since the next branch instruction information table exists, the process proceeds to pointer increment processing 321 and the size of the branch instruction information table is added to the variable cp so that the variable cp points to the next branch instruction information table. 23, the same processing as that of the fifth branch instruction 514 is performed on the sixth branch instruction 515 and the seventh branch instruction 516 of FIG.

There is no branch instruction which is the target of the optimization processing 106 of FIG. Since the value obtained by subtracting the address is "-128" or more, the sixth branch instruction is determined to generate a branch instruction for 2 bytes. Both the seventh branch instruction 516 and the eighth branch instruction 517 are determined to generate a branch instruction of 2 bytes, like the sixth branch instruction. Next, the ninth branch instruction 5
18 processing and the tenth branch instruction 519 are performed. The tenth branch instruction 519 to be the target of the optimization processing 106 in FIG. 2 exists between the ninth branch instruction 518 and the ninth jump destination 528, and both the tenth branch instruction 519 are determined as branch instructions of 2 bytes. If so, the ninth branch instruction 518 is also determined to be a 2-byte branch instruction, and if the tenth branch instruction 519 is determined to be a 3-byte branch instruction, the ninth branch instruction 518 is also determined to be a 3-byte branch instruction. Since it is decided, the ninth branch instruction 518 is not decided unless the tenth branch instruction 519 is decided.

Similarly for the tenth branch instruction 519, if the ninth branch instruction 518 is not determined, it is not determined whether a 2-byte branch instruction or a 3-byte branch instruction is generated. When the processing up to the tenth branch instruction 519 is completed, the processing proceeds to the flag determination processing 322. In the flag determination processing 322, when it is determined whether a branch instruction for 2 bytes or a branch instruction for 3 bytes is determined, the variable flag set to "1".
Is determined to be "1".

When the variable flag is "1", it means that there is a branch instruction in which it is decided whether to generate a branch instruction for 2 bytes or a branch instruction for 3 bytes.
It has not been determined whether a branch instruction for 2 bytes or a branch instruction for 3 bytes will be generated until the branch instruction for which it is decided whether to generate a branch instruction for bytes or a branch instruction for 3 bytes. A branch instruction that cannot be determined whether to generate a 2-byte branch instruction or a 3-byte branch instruction because it is definite will generate a 2-byte branch instruction or a 3-byte branch instruction. Since there is a possibility that it is possible to determine whether to generate, the process proceeds to the head address substitution processing 301. This completes the first optimization process 106 in FIG.

The branch instructions decided to generate a 2-byte branch instruction are the fourth branch instruction 513, the fifth branch instruction 514, the sixth branch instruction 515, the seventh branch instruction 516, and the eighth branch instruction of FIG. There are five instructions 517. Next, the second optimization processing 106 of FIG. 13 is performed. The third branch instruction 512 and the third jump destination 522 in FIG. 21 have no branch instruction to be the target of the optimization processing 106 in FIG. Since the address is subtracted and the value is "127" or less, the third branch instruction 512 is determined to generate a branch instruction for 2 bytes.

When the optimization process 106 of FIG. 2 is performed a third time, there is a branch instruction to be the optimization process 106 of FIG. 13 between the second branch instruction 511 and the second jump destination 521 of FIG. Since the value obtained by subtracting the address of the second branch instruction 511 from the address of the second jump destination 521 is "127" or less, the second branch instruction is determined to generate a branch instruction of 2 bytes. Fourth optimization process 1 in FIG.
When 06 is executed, there is no branch instruction to be the target of the optimization processing 106 of FIG. 2 between the first branch instruction 510 and the first jump destination 520 of FIG. The value obtained by subtracting the address of the one-branch instruction 510 is "12.
7 ”or less, the first branch instruction 510 is determined to generate a 2-byte branch instruction.

In the fifth optimization processing 106 of FIG. 13,
The first branch instruction 510 of FIG. 21 in the branch instruction information table pointed to by the variable cp is 2 by the increase amount determination processing 306 of FIG.
It is determined whether a branch instruction for bytes or a branch instruction for 3 bytes is confirmed. In this case, since it has been decided, the process proceeds to the branch instruction information table discrimination processing 320 of FIG. In the branch instruction information table determination processing 320, the variable c
It is determined whether or not there is a branch instruction information table next to the branch instruction information table pointed to by p. In this case, since the first branch instruction 510 of FIG. 21 is not the last branch instruction,
4 pointer increment processing 321 and proceed to variable c
The size of the branch instruction information table is added to p, and the variable c
23 so that p points to the next branch instruction information table.
Then, the process proceeds to the increase amount determination processing 306.

The second branch instruction 511, the third branch instruction 512, the fourth branch instruction 513, the fifth branch instruction 514 of FIG.
Similarly to the first branch instruction 510, the sixth branch instruction 515, the seventh branch instruction 516, and the eighth branch instruction 517 are also defined as the 2-byte branch instruction or the 3-byte branch instruction, so the first branch instruction The same processing as 510 is repeated. Next, the ninth branch instruction 518 cannot be determined as a 2-byte branch instruction or a 3-byte branch instruction unless the 10th branch instruction 519 is determined as a 2-byte branch instruction. Similarly, if the ninth branch instruction 518 is not determined to be a 2-byte branch instruction or a 3-byte branch instruction, the tenth branch instruction 519 is also a 2-byte branch instruction or a 3-byte branch instruction. Cannot be determined to the branch instruction of.

In the fifth optimization processing 106 of FIG. 13, 2 is obtained.
The variable flag is “0” because there is no definite branch instruction for either the byte branch instruction or the 3-byte branch instruction. Since the variable flag is “0” by the flag determination processing 322 of FIG. 24, the symbol table correction processing 3
Proceed to 23. Since the symbol table correction processing 323 has determined the symbol value on the assumption that a 2-byte branch instruction is generated when the symbol table is created, the branch instruction determined to generate a 3-byte branch instruction is If there is, a process of adding to the address value of the symbol for the number of times the branch instruction for 3 bytes is generated is performed. The optimization process 106 of FIG. 13 is completed at the fifth time.

[0074]

As described above, in the conventional assembler branch instruction optimization processing method, processing is performed in ascending order of the address of the branch instruction. If there is one branch instruction that is continuous and intersects, the branch instruction optimization process
Since it has to be performed once, it takes a long time to optimize the branch instruction.

The present invention eliminates such drawbacks, and an object of the present invention is to provide an assembler device having means for reducing the number of passes of optimization processing.

[0076]

The invention according to claim 1 is an input means for inputting a source program file in which a branch instruction is described in the same description format regardless of the size of the relative address up to the branch destination, and the above-mentioned. Each time a branch instruction appears in the source program file, a memory for storing a table having a pointer to the next table, a branch instruction address, a pointer to the symbol table, and code increment information for the branch instruction, and an address The first table connection means for connecting the tables in the ascending order and the table connected by the first table connection means are processed in the ascending order of the addresses of the branch instructions, and the branch instructions correspond to the shortest object code. The object module file that creates the object module file In the assembler device including a file creating means, a pointer to the previous table is added to the table and the tables are connected in a chain in descending order of the address. A means for alternately performing the processing of performing the branch instruction in the descending order of address with reference to the tables connected by the two-table connecting means and the processing of performing the branch instruction in the descending order of the address of the branch instruction, and remaining after the processing by this means is executed. And a means for processing the branch instruction.

According to the second aspect of the present invention, input means for inputting a source program file in which a branch instruction is described in the same description format regardless of the relative address up to the branch destination, and the branch instruction are source program files. Every time it appears in the branch instruction, a memory for storing a table having a pointer to the next table for the branch instruction, the address of the branch instruction, a pointer pointing to the symbol table, and code increment information, and the table is chained in ascending order of address. By referring to the table connected by the first table connection means and the first table connection means, the processing is performed in ascending order of the address of the branch instruction, and the object module file in which the branch instruction is associated with the shortest object code is created. Object module file creation means to create and In the provided assembler device, a second table linking means for adding a pointer to the previous table to the table and chaining the tables in descending order of address, and the object module file creating means are the second table linking means. First means for referring to the linked table in the descending order of the address of the branch instruction, second means for decreasing the address of the branch instruction, and jump destination of the branch instruction when processing is performed by the first means. And a means for determining a branch instruction group that depends on the object code size of the other party as an optimum object code for the branch instruction group that intersects with each other.

[0078]

According to the present invention corresponding to claim 1, each time a branch instruction appears in the source program file, a table linked by a bidirectional chain having information on the branch instruction is created and stored in the memory. Based on this table, optimization is performed from the ascending order of addresses and from the descending order of addresses, and if there are branch instructions that intersect each other and are affected by the number of bytes on the other side, the third time Generates the instruction with the shortest number of bytes in the optimization process. As a result, in the conventional technique, the number of consecutive forward-referenced branch instructions plus the number of passes of the optimization process is required, but in the present invention, the number of passes of the optimization process can be reduced from one to three.

In the invention according to claim 2, each time a branch instruction appears in the source program file, a table in which the information of the branch instruction is connected to the appearance address by a bidirectional chain is created and stored in the memory. Next, based on this table, optimization is performed from the ascending order of addresses and from the descending order of addresses, and when the optimization is performed from the descending order of addresses, the branch instructions are crossed and interfere with each other. Optimization processing is performed for each group. As a result, in the conventional technique, the number of consecutive forward-referenced branch instructions + the number of passes of the optimization process is required. However, in the present invention, since the process is completed in one to two passes, the processing time is reduced. Can be shortened.

[0080]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an embodiment of the invention corresponding to claim 1 will be described with reference to the drawings. FIG. 1 is a flow chart of an embodiment of the assembler processing system of the present invention. Figure 3
5 is a flowchart of an embodiment of a branch instruction information table creating process of the present invention. 4 and 5 are flow charts of an embodiment of the optimization processing system of the present invention. FIG. 5 shows a process in which a part surrounded by a broken line is added to realize the present invention with respect to FIG. 11 described in the conventional example. FIG. 6A shows an embodiment of the branch instruction information table created by the present invention. FIG. 8 is an example of a source program file.

The source program file of FIG. 8 is input to the assembler described in the prior art, and the line analysis is performed by the source analysis processing 100 for creating the bidirectional path 1 table of FIG. When the branch instruction 510 appears, the information of the branch instruction is set in the bidirectional branch instruction information table 104 of FIG. 1 by the processing of FIG. The bidirectional branch instruction information table 104 includes a chain pointer 440 that points to the next table in FIG. 6A, a chain pointer 441 that points to the previous table, and a branch instruction address 442.
It is composed of a chain pointer 443 which points to the symbol table and a code increment 444.

Address set processing 20 of the branch instruction of FIG.
0, the next address of the first branch instruction 510 of FIG.
The variable is added to the variable add held in the branch instruction information table 430 of the first branch instruction in (a). In the address setting process 201 of the symbol table of FIG. 3, the first jump destination 520 of FIG.
Of the address of the symbol table of FIG. 6 is stored in the branch instruction information table 430 of the first branch instruction of FIG.
To. 2 in the code increment setting process 202 of FIG.
The branch of the first branch instruction in FIG. 6A is set to “1” indicating that it is uncertain whether to generate a branch instruction for bytes or a branch instruction for 3 bytes, as an initial value of the code increment amount. It is assigned to the variable code of the instruction information table 430.

In the address setting process 203 of the next table of FIG. 3, the next branch instruction information table is created, and the address of the created next branch instruction information table is set to the branch instruction of the first branch instruction of FIG. 6A. The variable next is held in the information table 430. In the address setting process 204 of the table before FIG. 3, the address of the branch instruction information table 430 of the first branch instruction of FIG. 6A is substituted for the variable back held in the next branch instruction information table. In the address setting process 205 of FIG. 3, the address of the branch instruction information table 430 of the first branch instruction of FIG. 6A is assigned to the chain pointer 401 pointing to the end. With this, the branch instruction information table 430 of the first branch instruction is created.

Similarly, the second branch instruction 51 of FIG.
1, third branch instruction 512, fourth branch instruction 513, fifth branch instruction 514, sixth branch instruction 515, seventh branch instruction 51
6, the eighth branch instruction 517, the ninth branch instruction 518, and the tenth branch instruction 519 are performed, and each branch instruction information table of FIG. 6A is created. After the end of the input file in the file end determination processing 101 of FIG. 1, the bidirectional optimization processing 102 of FIG. 1 for optimizing the branch instruction is performed.

Next, the optimization process will be described with reference to the flowchart of FIG. In the bidirectional optimization process 102 of FIG.
By the loop discrimination processing 300, it is discriminated whether the variable i indicating whether optimization is performed from the smallest address or the largest address is "0" or "2". Since the initial value of the variable i is “0”, the condition is satisfied in this case, and the process proceeds to the head address substitution processing 301.
In the start address substitution processing 301, the chain pointer 400 that points to the head of the branch instruction information table that points to the head of FIG. 1 is added to the variable i indicating whether optimization is performed or optimization is performed in the order of increasing addresses, and the branch instruction is 2 in the flag initialization processing 305.
A variable f that indicates that it has been confirmed to be bytes or 3 bytes
Substitute "0" as an initial value for lag.

Since the processing after the increase amount determination processing 306 is the same as that of the conventional technique, a 2-byte branch instruction is generated when the first bidirectional optimization processing 102 of FIG. The determined branch instruction is the fourth branch instruction 51.
The fifth branch instruction 514, the fifth branch instruction 514, the sixth branch instruction 515, the seventh branch instruction 516, and the eighth branch instruction 517.

Next, the second bidirectional optimization process 1 of FIG.
Do 02. In the bidirectional optimization process 102, the variable i indicating whether the optimization is performed from the smallest address or the largest address by the loop determination process 300 of FIG. 4 is either “0” or “2”. Determine whether. In this case, since the variable i is "1", the condition is not satisfied, and the process proceeds to the end address substitution processing 303.

In the end address substitution processing 303, the chain pointer 400 indicating the end of the branch instruction information table indicating the beginning of FIG. 6A is substituted into the variable cp, and in the loop variable substitution processing 304 of FIG. Substituting "2" into a variable i indicating whether optimization is performed in order or optimization is performed in descending order of addresses, and in the flag initialization processing 305, the branch instruction is determined to be either 2 bytes or 3 bytes. "0" is assigned as an initial value to the variable flag indicating that the action has been performed. In the increment determination process 306, it is determined whether the tenth branch instruction 519 in FIG. 8 in the branch instruction information table pointed to by the variable cp is determined to be a 2-byte branch instruction or a 3-byte branch instruction. . In this case, since it is not decided, the increase amount calculation process 3 up to the branch instruction in FIG.
From 07, the number of branch instructions to be subjected to the bidirectional optimization processing 102 of FIG. 1 is calculated from the head of the file to the tenth branch instruction 519 of FIG. 8 in the branch instruction information table pointed to by the variable cp. Substitute in variable A. In this case, the first branch instruction 510, the second branch instruction 511, the third branch instruction 512, the fourth branch instruction 513, and the fifth branch instruction 5 of FIG.
Since there are nineteen, the sixth branch instruction 515, the seventh branch instruction 516, the eighth branch instruction 517, and the ninth branch instruction 518, “9” is assigned to the variable A.

Increase amount calculation processing 308 to the jump destination in FIG.
1 from the head of the file to the tenth jump destination 529 which is the jump destination of the tenth branch instruction 519 of FIG. 8 in the branch instruction information table pointed to by the variable cp.
The number of branch instructions to be processed is calculated, and the calculated branch instruction is substituted into the variable B. In this case, the first branch instruction 510 of FIG.
Second branch instruction 511, third branch instruction 512, fourth branch instruction 513, fifth branch instruction 514, sixth branch instruction 515,
Since there are eight seventh branch instructions 516 and eight branch instructions 517, “8” is assigned to the variable B.

The branch instruction information table pointed to by the variable cp from the address of the tenth jump destination 529 which is the jump destination of the tenth branch instruction 519 of FIG. 8 in the branch instruction information table pointed to by the variable cp by the relative address substitution processing 309 of FIG. The address of the tenth branch instruction 519 is subtracted and substituted into the variable mrl.
In this case, since "-128" bytes, "-128" is assigned to the variable mrl. Then, the symbol reference determination process 310 of FIG. 4 determines whether the tenth branch instruction 519 of FIG. 8 in the branch instruction information table pointed to by the variable cp is a forward reference or a backward reference. In this case it's a back reference, so
The relative value in FIG. 4 is set in the variable maxr by the setting process 313, the variable mrl is substituted in the variable maxr, and the code increase amount and the relative value are set in the variable minr by the setting process 314.
rl and the variable B are added, and the result of subtracting the variable A from the added result is substituted for the variable minr. In this case, "-129" is assigned to the variable minr and "-128" is assigned to the variable maxr. Next, whether a 2-byte branch instruction or a 3-byte branch instruction is generated by the 2-byte branch instruction output determination processing 315 and the 3-byte branch instruction output determination processing 316 of FIG. Make a decision. In this case, since the variable minr is “−129”, the condition of the 2-byte branch instruction output determination process 315 is not satisfied, and the 3-byte branch instruction output determination process 316 is performed.
Go to.

Since the variable maxr is "-129", 3
The condition of the branch instruction output determination processing 316 for bytes is satisfied and it is not determined whether the branch instruction for 2 bytes or the branch instruction for 3 bytes is generated. Therefore, the process proceeds to the optimization number determination processing 330. Since the variable i is “2”, the determination is false, and the process proceeds to the branch instruction information table determination processing 320.
In the branch instruction information table determination processing 320, it is determined whether or not there is a branch instruction information table next to the branch instruction information table pointed to by the variable cp. In this case, since the next branch instruction information table exists, the process proceeds to the pointer increment processing 321 to add the size of the branch instruction information table to the variable cp and point to the next branch instruction information table to increase the number in FIG. Proceeding to the amount determination processing 306, the same processing as the tenth branch instruction 519 is performed on the ninth branch instruction 518 of FIG.

Similarly, for the ninth branch instruction 518, if the tenth branch instruction 519 is not determined, it is not determined whether the 2-byte branch instruction or the 3-byte branch instruction is generated.

Next, the third branch instruction 512 is processed. The branch instruction that is the target of the optimization process 106 in FIG. 2 does not exist between the third branch instruction 512 and the third jump destination 522, and the address of the third branch instruction 512 is subtracted from the address of the third jump destination 522. Since the value obtained is less than or equal to "127", the third branch instruction 512 is determined to generate a 2-byte branch instruction. 2 does not exist between the second branch instruction 511 and the second jump destination 521, and the address of the second branch instruction 511 is subtracted from the address of the second jump destination 521. Since the value obtained is "127" or less, it is determined that the second branch instruction 511 generates a 2-byte branch instruction.

There is no branch instruction which is the target of the optimization processing 106 of FIG. Since the value obtained by subtracting the address is "127" or less, the first branch instruction 510 is determined to generate a branch instruction for 2 bytes. This completes the second bidirectional optimization process 102 of FIG. The branch instruction determined to generate a 2-byte branch instruction is the first branch instruction 510, the second branch instruction 511, and the third branch instruction 51 of FIG.
Two are the second, fourth branch instruction 513, fifth branch instruction 514, sixth branch instruction 515, seventh branch instruction 516, and eighth branch instruction 517. Next, the third bidirectional optimization process 102 of FIG. 1 is performed. In the third optimization process 102, the variable i becomes “3”, and the variable cp indicates the branch instruction information table from the head of the file. It is a bidirectional branch instruction that the number of bytes has not been determined so far, and cannot be determined because they interfere with each other.

In the present embodiment, the ninth branch instruction 518 and the tenth branch instruction 519 interfere with each other and cannot be determined. The ninth branch instruction 518 is the optimization number determination processing 33.
When the variable i is 0, it is determined to be true when the variable i is "3". Since the variable mrl is “127” and is true, it is decided that the branch instruction is for 2 bytes, and the process proceeds to the flag setting process 318.

Next, the tenth branch instruction 519 is the ninth branch instruction 5
18 is determined to be a 2-byte branch instruction, the variable mrl is "-128", the variable maxr is "-128", and the variable mi.
nr becomes "-128", which becomes true in the 2-byte branch instruction output determination processing 315, and is determined as a 2-byte branch instruction. In the branch instruction information table discrimination processing 320,
Since there is no next information table, the optimization end processing determination 332
Go to. In the optimization end processing determination 332, since the variable i is “3”, the determination of the variable flag is skipped, the process proceeds to the symbol table correction processing 323, and the optimization processing ends. Therefore, the optimization process can be completed three times.

Next, an embodiment of the invention corresponding to claim 2 will be described with reference to the drawings. FIG. 12 is a flow chart of an embodiment of the assembler processing method of the present invention. 14
6 is a flowchart of an embodiment of a branch instruction information table creating process of the present invention. 15, 16, 17, and 1
8 is a flow chart of an embodiment of the optimization processing method of the present invention. FIG. 16 shows a process in which a portion surrounded by a broken line is added to realize the present invention with respect to FIG. 24 described in the conventional example. FIG. 17 and FIG. 18 are flowcharts of optimization processing of branch instruction groups that intersect each other and interfere with each other. Figure 1
9 (a) is an embodiment of the branch instruction information table created by the present invention. FIG. 21 is an example of a source program file.

FIG. 21 shows the assembler described in the prior art.
Enter the source program file of
When the first branch instruction 510 of FIG. 21 appears as a result of the line analysis in the source analysis processing 100 for creating a bidirectional table, the information of the branch instruction is processed in the processing of FIG. 14 and the bidirectional branch instruction information table of FIG. Set to 104. The bidirectional branch instruction information table 104 includes a chain pointer 440 that points to the next table in FIG. 19A, a chain pointer 441 that points to the previous table, a branch instruction address 442, and a chain pointer 443 that points to the symbol table. And a code increase amount 444.

Address set processing 2 of the branch instruction of FIG.
00, the next address of the first branch instruction 510 of FIG. 21 is set to the branch instruction information table 4 of the first branch instruction of FIG.
Substitute for the variable add of 30. In the address setting process 201 of the symbol table of FIG. 14, the address of the symbol table of the first jump destination 520 of FIG.
The variable is assigned to the variable symp of the branch instruction information table 430 of the first branch instruction of (a). Whether to generate a 2-byte branch instruction in the code increment setting process 202 of FIG.
FIG. 19A shows an initial value of the code increase amount, which is "1" indicating that it is uncertain whether to generate a branch instruction for bytes.
The first branch instruction is assigned to the variable code in the branch instruction information table 430. In the address setting process 203 of the next table in FIG. 14, the next branch instruction information table is created, and the address of the created next branch instruction information table is set to the branch instruction information table 4 of the first branch instruction in FIG. 19A.
Substitute in the variable next of 30.

In the address setting process 204 of the previous table of FIG. 14, the address of the branch instruction information table 430 of the first branch instruction of FIG. 19A is substituted into the variable back held in the next branch instruction information table. In the address setting processing 205 of FIG. 14, the address of the branch instruction information table 430 of the first branch instruction of FIG. 19A is assigned to the chain pointer 401 pointing to the end. With this, the branch instruction information table 430 of the first branch instruction is created. Similarly, the second branch instruction 511 and the third branch instruction 512 of FIG.
A fourth branch instruction 513, a fifth branch instruction 514, a sixth branch instruction 515, a seventh branch instruction 516, an eighth branch instruction 517,
The ninth branch instruction 518 and the tenth branch instruction 519 are performed, and each branch instruction information table of FIG. 19A is created. After the input file is completed in the file end determination processing 101 in FIG. 12, the bidirectional optimization processing 102 in FIG. 12 for optimizing the branch instruction is performed.

Next, the optimization processing will be described with reference to the flowchart of FIG. In the bidirectional optimization process 102 of FIG. 12,
By the loop discrimination processing 300 of FIG. 15, it is determined whether or not the variable i indicating whether optimization is performed from the smallest address or the largest address is “0”. Since the initial value of the variable i is “0”, the condition is satisfied in this case, and the process proceeds to the head address substitution processing 301. In the head address substitution processing 301, the chain pointer 400 that points to the head of the branch instruction information table that points to the head of FIG. 19A is assigned to the variable cp, and the loop variable “1” addition processing 302 of FIG. Is added to the variable i indicating whether optimization is performed or the optimization is performed in descending order of address, and a variable indicating that the branch instruction is fixed to 2 bytes or 3 bytes in the flag initialization processing 305. flag
Substitute "0" as the initial value for. Increase amount determination process 30
Since the processing from step 6 onward is the same as that of the conventional technique, 2 at the time when the first bidirectional optimization processing 102 of FIG. 12 is completed.
The five branch instructions determined to generate the branch instructions for bytes are the fifth branch instruction 513, the fifth branch instruction 514, the sixth branch instruction 515, the seventh branch instruction 516, and the eighth branch instruction 517. . Next, the second bidirectional optimization process 102 of FIG. 1 is performed.

In the bidirectional optimization process 102, whether or not the variable i indicating whether the optimization is performed from the smallest address or the largest address by the loop discrimination process 300 of FIG. 15 is "0". To determine. In this case the variable i
Since “1” is “1”, the condition is not satisfied, and the process proceeds to the end address substitution process 303. In the end address substitution processing 303, the chain pointer 400 indicating the beginning of FIG. 19A indicating the end of the branch instruction information table is assigned to the variable cp, and
In the loop variable “1” substitution process 302 of FIG. 1, “1” is added to the variable i indicating whether optimization is performed from the smallest address or the largest address, and a branch instruction is generated in the flag initialization process 305. "0" is assigned as an initial value to a variable flag indicating that is determined to be either 2 bytes or 3 bytes. In the increment determination process 306, it is determined whether the tenth branch instruction 519 of FIG. 21 in the branch instruction information table pointed to by the variable cp is determined to be a 2-byte branch instruction or a 3-byte branch instruction. . In this case, since it has not been decided, the variable c from the beginning of the file is calculated by the increase amount calculation processing 307 up to the branch instruction in FIG.
21 is calculated by the tenth branch instruction 519 in FIG. 21 in the branch instruction information table pointed to by p, and is substituted into the variable A. In this case, the first branch instruction 510, the second branch instruction 511, the third branch instruction 512, the fourth branch instruction 513, the fifth branch instruction 514, the sixth branch instruction 515, the seventh branch instruction 516 and the eighth branch instruction of FIG. Since there are nine branch instructions 517 and the ninth branch instruction 518, “9” is assigned to the variable A.

Increase amount calculation processing 308 up to the jump destination in FIG.
12 from the head of the file to the tenth jump destination 529 which is the jump destination of the tenth branch instruction 519 of FIG. 21 in the branch instruction information table pointed to by the variable cp.
Calculate how many branch instructions are subject to 02,
Substitute in variable B. In this case, the first branch instruction 5 in FIG.
10, second branch instruction 511, third branch instruction 512, fourth branch instruction 513, fifth branch instruction 514, sixth branch instruction 5
Since there are eightteen, the seventh branch instruction 516 and the eighth branch instruction 517, “8” is substituted into the variable B. In the branch instruction information table pointed to by the variable cp by the relative address assignment processing 309 of FIG. The address of the branch instruction 519 is subtracted and substituted into the variable mrl. In this case, "-12
Since it is 8 "bytes," -128 "is assigned to the variable mrl.

Then, the symbol reference discrimination processing 3 of FIG.
2 of the branch instruction information table pointed to by the variable cp by 10
It is determined whether the 1st tenth branch instruction 519 is a forward reference or a backward reference. In this case, the reference is backward, so
Is set to the variable maxr by the setting process 313, the variable mrl is substituted into the variable maxr, and the code increase amount and the relative value are set to the variable minr by the setting process 314.
And the variable B are added, and the result of subtracting the variable A from the added result is substituted for the variable minr. In this case, the variable mi
"-129" is assigned to nr, and "-1" is assigned to the variable maxr.
28 ”is substituted. Next, whether the 2-byte branch instruction output determination process 315 and the 3-byte branch instruction output determination process 316 in FIG. 16 generate a 2-byte branch instruction or a 3-byte branch instruction. Make a distinction. In this case, since the variable minr is "-129", the condition of the 2-byte branch instruction output determination process 315 is not satisfied, and the process proceeds to the 3-byte branch instruction output determination process 316.
Since the variable maxr is “−129”, the condition of the branch instruction output determination process 316 for 3 bytes is satisfied and it is not determined whether the branch instruction for 2 bytes or the branch instruction for 3 bytes is generated. The process proceeds to the optimization number determination process 330. Since the variable i is “2”, the determination is true, and the optimization processing 331 of the branch instruction group that intersects and interferes with each other.
Go to.

The flow of the optimizing process 331 of the branch instruction group which intersects and interferes with each other will be described with reference to FIGS. 17 and 18. In FIG. 17, the value of the variable cp that points to the head pointer of the branch instruction group is saved in the variable stpt, the number of intersecting branch instructions whose number of bytes is undecided is assigned to the variable und, and the number of bytes is undecided. Check the optimization of the instruction. The determination 306 of FIG. 17 to the determination 316 of FIG. 18 are the same as the determination 306 of FIG. 15 to the determination 316 of FIG. 16, and the address calculation up to the branch destination is performed. It is determined by the processing 353 and the determination 354 of FIG. 18 whether the end of the branch instruction group is reached. If not finished, process 352
Return to. If it is the end, it is determined whether the last branch instruction is a forward reference or a backward reference. In the case of forward reference, since all branch instructions in the branch instruction group can be branched into 2 bytes, the process goes to step 362. By the processing from the processing 362 to the determination 367, all the branch instruction groups are decided as 2-byte branch instructions. In the case of backward reference, the branch instruction group is continued and the process returns to the processing 351.

If it is determined in the determination 316 that the branch instruction is the 3-byte instruction, the process 317 to the determination 36.
By the processing up to 8, all branch instructions of the branch instruction group up to now are determined by 3-byte instructions. In this embodiment, the branch instruction information table pointer pointed to by the variable cp is assigned to the variable stpt in the process 350 of FIG. Next process 35
In step 1, the number of unresolved branch instructions from the branch instruction to the branch destination is calculated and assigned to the variable und. In this case, the branch instruction 518 of FIG. 21 is an undetermined branch instruction, and “1” is assigned to the variable und. Variable c in process 352
The pointer of the next branch instruction information table is set to p. The branch information table 428 of the branch instruction 518 in FIG. 21 is stored in the variable cp.

In the judgment 306, it is judged whether or not the branch instruction pointed to by the variable cp is fixed. If it has been confirmed, the process returns to the process 352. In this case, since it is undetermined, it becomes false and the process proceeds to step 307. Determination 3 of processing 307 to FIG.
The process up to 16 is the same as that in FIGS. 15 and 16. Therefore, the process proceeds to the determination of determination 316 in FIG. Since the determination is false, the process proceeds to step 353, and the variable und is decremented by "1". At that time, the variable und becomes “0”. Next discrimination 3
At 54, it is determined whether the variable und is "0". Variable u
Since nd is “0”, the determination is true, and the process proceeds to determination 355. In the determination 355, it is determined whether or not the branch instruction pointed to by the variable cp is a forward reference. The branch instruction 518 in FIG. 21 is a forward reference. Therefore, the determination is true, and the process advances to the process 362. The processing from the processing 362 is processing for determining branch instructions that interfere with each other as a 2-byte branch instruction. Process 3
At 62, the value of the variable cp is substituted for the variable tcp to obtain the variable st.
Processing is performed to fix all undetermined branch instructions up to the branch information table pointed to by pt as 2-byte branch instructions. In this case, the branch instruction 518 and the branch instruction 519 of FIG. 21 are fixed as a 2-byte branch instruction.

After the processing of FIG. 18 is completed, the determination 32 of FIG.
The process starts from 0. In the determination 320, it is determined whether or not there is a branch instruction information table next to the branch instruction information table pointed to by the variable cp. In this case, since the next branch instruction information table exists, the processing proceeds to step 321, the size of the branch instruction information table is added to the variable cp, and the next branch instruction information table is pointed to.
In step 06, the same processing as that of the tenth branch instruction 519 is performed on the third branch instruction 512 of FIG. Third branch instruction 512
Between the third jump destination 522 and the third jump destination 522, there is no branch instruction that is the target of the optimization processing 106 of FIG.
Since the value obtained by subtracting the address of the third branch instruction 512 from the address of is less than "127", the third branch instruction is determined to generate a branch instruction of 2 bytes. The branch instruction that is the target of the optimization processing 106 in FIG. 13 does not exist between the second branch instruction 511 and the second jump destination 521, and the address of the second branch instruction 511 is subtracted from the address of the second jump destination 521. Since the value obtained is "127" or less, it is determined that the second branch instruction 511 generates a 2-byte branch instruction.

There is no branch instruction which is the target of the optimization processing 106 of FIG. 13 between the first branch instruction 510 and the first jump destination 520, and the first branch instruction 510 is changed from the address of the first jump destination 520. Since the value obtained by subtracting the address is equal to or smaller than "127", the second branch instruction 511 is determined to generate a 2-byte branch instruction. This completes the second bidirectional optimization process 102 of FIG.

The branch instruction determined to generate a 2-byte branch instruction is the first branch instruction 510, the second branch instruction 511, the third branch instruction 512, and the fourth branch instruction 5 of FIG.
13, fifth branch instruction 514, sixth branch instruction 515, seventh branch instruction 516, eighth branch instruction 517, ninth branch instruction 5
The optimization of all the branch instructions was completed with 10 of the 18th and 10th branch instructions. Optimization end processing determination 33
In 2, since the variable i is “2”, the determination of the variable flag is skipped, the process proceeds to step 323, and the optimization process ends. Therefore, the optimization process can be completed twice.

[0111]

As described above, according to the present invention, optimization is performed alternately from the smallest address and the largest address. Therefore, in the prior art, continuous forward reference branch instructions are executed. In the present invention, the optimization process is performed twice or three times regardless of the number of consecutive forward-referenced branch instructions, whereas the number of optimizations for the number of optimizations is required. Further, the invention according to claim 2 has an effect that it can be reduced to once or twice.

[Brief description of drawings]

FIG. 1 is a flowchart showing the overall operation of the first embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of a conventional example.

FIG. 3 is a flowchart showing the contents of branch instruction information table creation processing according to the first embodiment of the present invention.

FIG. 4 is a detailed flowchart of the optimization process of the first embodiment of the present invention.

FIG. 5 is a detailed flowchart of the optimization process of the first embodiment of the present invention.

FIG. 6 is a diagram showing the contents of a branch instruction information table according to the first embodiment of the present invention.

FIG. 7 is a diagram showing the contents of a conventional branch instruction information table.

FIG. 8 is a diagram showing the contents of an assembler source program.

FIG. 9 is a flowchart showing the contents of a conventional branch instruction information table creation process.

FIG. 10 is a flowchart showing the contents of optimization processing of a conventional example.

FIG. 11 is a flowchart showing the contents of an optimization process of a conventional example.

FIG. 12 is a flowchart showing the overall operation of the second embodiment of the present invention.

FIG. 13 is a flowchart showing the operation of a conventional example.

FIG. 14 is a flowchart showing the contents of a branch instruction information table creation process of the second embodiment of the present invention.

FIG. 15 is a flowchart showing the contents of optimization processing according to the second embodiment of the present invention.

FIG. 16 is a flowchart showing the contents of optimization processing of the second embodiment of the present invention.

FIG. 17 is a flowchart showing the contents of optimization processing of the second embodiment of the present invention.

FIG. 18 is a flowchart showing the contents of optimization processing according to the second embodiment of the present invention.

FIG. 19 is a diagram showing the contents of a branch instruction information table according to the second embodiment of the present invention.

FIG. 20 is a diagram showing the contents of a conventional branch instruction information table.

FIG. 21 is a diagram showing the contents of an assembler source program.

FIG. 22 is a flowchart showing the contents of conventional branch instruction information table creation processing.

FIG. 23 is a flowchart showing the contents of optimization processing of a conventional example.

FIG. 24 is a flowchart showing the contents of optimization processing of a conventional example.

[Explanation of symbols]

400 Chain pointer that points to the beginning 401 Chain pointer that points to the end 410 Chain pointer that points to the table before the first branch instruction 411 Chain pointer that points to the table before the second branch instruction 412 Chain that points to the table before the third branch instruction Pointer 413 Chain pointer that points to the table before the fourth branch instruction 414 Chain pointer that points to the table before the fifth branch instruction 415 Chain pointer that points to the table before the sixth branch instruction 416 Pointer to the table before the seventh branch instruction Chain pointer 417 Chain pointer that points to the table before the eighth branch instruction 418 Chain pointer that points to the table before the ninth branch instruction 419 Chain pointer that points to the table before the tenth branch instruction 420 Next to the first branch instruction Chain pointing to a table Pointer 421 Chain pointer pointing to the next table of the second branch instruction 422 Chain pointer pointing to the table of the third branch instruction 423 Chain pointer 424 Pointing to the table of the fourth branch instruction 424 Next table of the fifth branch instruction Chain pointer to point 425 Chain pointer to point to the table next to the sixth branch instruction 426 Chain pointer to point to the table next to the seventh branch instruction 427 Chain pointer to point to the table next to the eighth branch instruction 428 Next to the ninth branch instruction Chain pointer pointing to a table 429 Chain pointer pointing to a table next to a tenth branch instruction 430 Branch instruction information table 431 of a first branch instruction Branch instruction information table 432 of a second branch instruction Branch instruction information table 433 of a third branch instruction Branch instruction information Bull 434 Branch instruction information table of fifth branch instruction 435 Branch instruction information table of sixth branch instruction 436 Branch instruction information table of seventh branch instruction 437 Branch instruction information table of eighth branch instruction 438 Branch instruction information of ninth branch instruction Table 439 Branch instruction information table for tenth branch instruction 440 Chain pointer pointing to the next table 441 Chain pointer pointing to the previous table 442 Branch instruction address 443 Chain pointer pointing to the symbol table 444 Code increment 500 Source program file 501 Continuous Forward reference branch instruction group 502 Continuous backward reference branch instruction group 503 Crossing branch instruction 510 First branch instruction 511 Second branch instruction 512 Third branch instruction 513 Fourth branch instruction 514 Fifth branch instruction 515 Sixth Branch Instruction 516 7th branch instruction 517 8th branch instruction 518 9th branch instruction 519 10th branch instruction 520 1st jump destination 521 2nd jump destination 522 3rd jump destination 523 4th jump destination 524 5th jump destination 525 6th jump instruction Destination 526 7th destination 527 8th destination 528 9th destination 529 10th destination

Claims (2)

[Claims] 1. Input means for inputting a source program file in which a branch instruction is described in the same description format regardless of the relative address up to the branch destination, and the branching each time the branch instruction appears in the source program file. For the instruction, a memory for storing a table having a pointer to the next table, an address of a branch instruction, a pointer to the symbol table, and code increase amount information, and a first table connecting means for connecting the above tables in a chain in ascending order of address. And referring to the tables connected by the first table connection means, perform processing in the ascending order of the addresses of the branch instructions,
In an assembler device provided with an object module file creating means for creating an object module file in which a branch instruction is associated with the shortest object code, a pointer is added to the previous table in the above table to chain the tables in descending order of address. The second table linking means for connecting with each other and the object module file creating means refer to the tables linked by the second table linking means and perform the processing in the descending order of the address of the branch instruction in ascending order of the address of the branch instruction. An assembler device comprising: a means for executing the processing alternately with the processing to be performed; and a means for processing a branch instruction left after the processing is executed by this means. 2. Input means for inputting a source program file in which a branch instruction is described in the same description format regardless of the relative address up to the branch destination, and the branching each time the branch instruction appears in the source program file. For the instruction, a memory for storing a table having a pointer to the next table, an address of a branch instruction, a pointer to the symbol table, and code increase amount information, and a first table connecting means for connecting the above tables in a chain in ascending order of address. And referring to the tables connected by the first table connection means, perform processing in the ascending order of the addresses of the branch instructions,
In an assembler device provided with an object module file creating means for creating an object module file in which a branch instruction is associated with the shortest object code, a pointer is added to the previous table in the above table to chain the tables in descending order of address. The second table linking means for connecting with each other and the object module file creating means refer to the tables linked by the second table linking means in the order of descending branch instruction addresses, and the branch instruction address. The second object to be executed in the ascending order of the first and second instruction groups which are dependent on each other's object code size with respect to the branch instruction group in which the jump destinations of the branch instructions cross each other when the processing by this first means is performed. And a means for determining That assembler apparatus.