JPH052559A - Bus transfer system - Google Patents

Abstract

PURPOSE:To execute input/output processing at a high speed by allowing a memory connected to a CPU to execute specific transfer operation. CONSTITUTION:The CPU 20, the memory 30 and other plural devices 40 to 4n are connected to a common address/data bus 10. Each of the memory 30 and the devices 40 to 4n receives an address signal from the CPU 20, returns an ACK signal meaning access available state when the received signal is a valid address, and at the end of data transfer operation, immediately sends a Ready signal for permitting the succeeding transfer operation. Thereby, the loading/unloading of the memory 30 and the devices 40 to 4n can be instantaneously detected, and when the Read signal is returned, the succeeding operation processing can be executed prior to the return of a DACK signal. Consequently the input/output processing can be executed at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus transfer system,
In particular, it relates to a data bus transfer method between a CPU and a memory.

[0002]

2. Description of the Related Art In a conventional data transfer system, when a memory receives an address signal sent from a CPU and the address is valid, the memory performs a write operation or a read operation and operates when the operation is completed. The DACK signal indicating the end was returned to the CPU. When the CPU receives this DACK signal, it shifts to the next bus transfer operation.

If the address is not valid, the memory did not send the DACK signal back to the CPU. Therefore, in the CPU, if the DACK signal is not received even after a lapse of a certain period of time, the CPU shifts to the next bus transfer operation.

[0004]

However, in the above-mentioned conventional example, the CPU does not perform the next bus transfer operation until the DACK signal is received or a certain period of time elapses. Therefore, there is an inconvenience that the next operation cannot be started until the DACK signal is returned from the memory, or at least the time required for one cycle of memory access has elapsed.

[0005]

SUMMARY OF THE INVENTION The object of the present invention is to improve the inconvenience of the conventional example, and in particular, to have the function of allowing the CPU to confirm the validity of the address signal sent from the CPU earlier,
It is to provide a bus transfer method having a function that allows U to shift to the next operation as soon as possible.

[0006]

Therefore, according to the present invention, when a memory connected to a CPU via a common address / data bus receives an address signal from the CPU, it is checked whether the address signal is valid. If the address is valid, an ACK signal indicating that access is possible is returned, and immediately after the data transfer operation is completed, a Ready signal that permits the next transfer operation is sent. This aims to achieve the above-mentioned object.

[0007]

(1) When data is written from the CPU to the memory: When the address signal is sent from the CPU to the address bus, the memory takes in the address signal. The memory checks whether the address signal is valid, and when it is valid, returns an ACK signal at the timing of the next clock signal, and when they do not match, it does not return an ACK signal. Upon receiving the ACK signal, the CPU sends the write data to the data bus. The memory performs a write operation, and returns a Ready signal when it is ready to be processed even when the next access comes. CPU is R
When the ready signal is received, the next bus transfer operation is performed.
If the address is not valid, the CPU does not receive the ACK signal, and immediately shifts to the next processing.

(2) When the stored data is read from the CPU to the memory: When the CPU sends an address signal to the address bus, the memory takes in the address signal. The memory checks whether the address signal is valid, and when it is valid, returns an ACK signal at the timing of the next clock signal.
Do not send back the K signal. Further, the memory sends the stored data to the data bus when the address signal is valid.
When the CPU receives the ACK signal, the CPU takes in data from the data bus. The memory returns the Ready signal when it is ready to be processed even when the next access comes. When the CPU receives the Ready signal, it performs the next bus transfer operation. If the address is not valid, the CPU does not receive the ACK signal, and immediately shifts to the next processing.

[0009]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. In the embodiment of FIG. 1, the common address / data bus 10 has a CPU 20 and a memory 30.
And a plurality of other devices 40 to 4n are connected. And the memory 30 and other devices 4
Each of 0 to 4n receives an address signal from the CPU 20 and returns an ACK signal indicating that it is accessible if it is a valid address, and immediately after the data transfer operation is completed, a Ready signal which permits the next transfer operation is immediately transmitted. It has a function. Here, as other devices, there are a printer, a hard disk, a display, and the like.

Next, the operation of this embodiment will be described with reference to the bus transfer time chart shown in FIG.

(1) A case of writing data from the CPU 20 to the memory 30 will be described. CPU
Address signal 2 is sent from 20 to address bus 10. Address strobe (ADS) by CPU 20
Signal 3 is activated (low active in FIG. 2). The memory 30 takes in the address signal 2 when the address strobe (ADS) signal 3 becomes active.
The memory 30 checks whether the address signal 2 is valid. The memory 30 returns the ACK signal 4 at the timing of the next clock signal 1 when the address signal 2 is valid, and does not return the ACK signal 4 when they do not match. When the CPU 20 receives the ACK signal 4, it sends the write data to the data bus 10. Memory 30
Performs a write operation, and returns a Ready signal 5 when it is ready for processing even when the next access comes.
Upon receiving the Ready signal 5, the CPU 20 performs the next bus transfer operation. On the other hand, the memory 30 returns the DACK signal 6 when the writing operation is completed. if,
If the address is not valid in
Since the CK signal 4 is not received, the process immediately shifts to the next process.

(2) A case where a read operation of stored data from the CPU 20 to the memory 30 is performed will be described. C
The address signal 2 is sent from the PU 20 to the address bus 10. Address strobe (AD
S) signal 3 is activated (low active in FIG. 2). The memory 30 is an address strobe (ADS)
When the signal 3 becomes active, the address signal 2 is fetched. The memory 30 checks whether the address signal 2 is valid. When the address signal 2 is valid, the memory 30 outputs A at the timing of the next clock signal 1.
CK signal 4 is returned, and when they do not match, ACK signal 4 is not returned. Further, the memory 30 sends the stored data to the data bus 10 when the address signal 2 is valid. When the CPU 20 receives the ACK signal 4, it performs a process of fetching data from the data bus 10. Memory 3
0 returns the Ready signal 5 when it is ready to be processed even when the next access comes. CPU20 is Re
When the ady signal 5 is received, the next bus transfer operation is performed.
On the other hand, when the memory 30 completes the read operation, D
The ACK signal 6 is returned. If the address is not valid in, the CPU 20 does not receive the ACK signal 4, so that the process immediately proceeds to the next process.

(3) A case where the CPU 20 performs an output operation to another device 40 will be described. The address signal 2 is sent from the CPU 20 to the address bus 10.
Address strobe (ADS) signal 3 by CPU 20
Are made active (low active in FIG. 2).
The other device 40 takes in the address signal 2 when the address strobe (ADS) signal 3 becomes active.
The other device 40 checks whether the address signal 2 is valid. The other device 40 returns the ACK signal 4 at the timing of the next clock signal 1 when the address signal 2 is valid, and does not return the ACK signal 4 when they do not match. When the CPU 20 receives the ACK signal 4, it outputs the output data to the data bus 10. The other device 40 performs the read operation of the data on the data bus 10 and returns the Ready signal 5 when it is ready to be processed even when the next access comes. CPU20
When the Ready signal 5 is received, the following bus transfer operation is performed. On the other hand, the other device 40 returns the DACK signal 6 when the output operation is completely completed. If the address is not valid in, the CPU 20 does not receive the ACK signal 4, so that the process immediately proceeds to the next process.

[0014]

As described above, according to the present invention, when a memory connected to a CPU via a common address / data bus receives an address signal from the CPU, it is checked whether the address signal is valid. , If it is a valid address, it returns an ACK signal indicating that it is accessible, and immediately after the data transfer operation ends, it sends a Ready signal that permits the next transfer operation. You can instantly know whether the device is mounted or not mounted, and Ready
By returning the signal, the next operation processing can be performed before the DACK signal is returned. Therefore, it is possible to provide an unprecedented excellent bus transfer method capable of performing input / output processing at high speed.

[Brief description of drawings]

FIG. 1 is a bus connection diagram showing an embodiment of the present invention.

FIG. 2 is a bus transfer time chart of the present invention.

[Explanation of symbols]

 2 address signal 4 ACK signal 5 ready signal 6 DACK signal 10 address / data bus 20 CPU 30 memory

Claims (1)

Claims: 1. C via a common address / data bus.
In the system in which the PU and the memory are connected, the memory receives the address signal from the CPU, returns a signal indicating that the address is accessible if the address is valid, and immediately after the data transfer operation ends, A bus transfer method characterized in that a signal for permitting the transfer operation of is transmitted.