JPH05252044A - Oversample d/a converter - Google Patents

Abstract

PURPOSE:To quicken the processing speed by revising the configuration of a circuit of a secondary noise generation type oversample D/A converter so as to reduce the number of times of adding operations in the circuit. CONSTITUTION:Four times of adding operations at maximum have been required for a conventional D/A converter for one sample from an input of an input signal X till an output of an output signal Z, but the output signal is outputted by three times of addition operations in this case at maximum by using adders 1, 2, 3. Furthermore, since the coefficient of multipliers 7, 9, 10 is all 2's power, they are configured by the wiring such as shift registers, inverters.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oversampling D / A converter, and more particularly to a secondary noise shaping type oversampling D / A converter for LSI for video signals.

[0002]

2. Description of the Related Art Conventionally, an oversampling D / A converter of this type has a circuit as shown in FIG. The oversampling D / A converter improves the S / N ratio by oversampling, which selects a sampling frequency higher than the signal frequency, and at the same time, advances the digitization of the entire circuit to reduce
The purpose is to convert to SI. For details, refer to the material, Nikkei Electronics 1988.25 P277-Oversampling A / D / A conversion technology Yukawa,
Have been introduced to. In FIG. 2, the digital input signal X
And the output signal of the delay device 29 is subtracted by the adder 21. Next, the difference signal which is the output of the adder 21 is integrated by the integrator 30 including the delay device 23 and the adder 22. Further, the integration is performed by the integrator 31, but feedback control is applied to the system of this circuit so that the outputs of the two integrators become minimum. The output signal Y ₂ of the integrator 31 is quantized by the quantizer 27, and its output signal is 1 bit D /
The A converter 28 converts the analog signal and outputs the analog signal. Here, the transfer function of this circuit is obtained for the input signal Y ₂ of the quantizer 27 by using the Z transform as follows.

[0003]

[0004]

As described above, in the conventional over-sampling D / A converter, the continuous signal within one sample is output before the digital input signal is output as the analog output signal by the 1-bit D / A converter. (Or necessary for serial processing) is added four times. When this is operated by oversampling, there is a problem that the operation speed required for each adder becomes high and it is difficult to realize it.

[0005]

The oversampling D / A converter of the present invention comprises a first adder for inputting a digital input signal and a first loopback signal input from the outside, and the first adder. Second adder for inputting the output signal of the adder and the second loopback signal, and a third adder for inputting the output signal of the second adder and the third loopback signal A quantizer for inputting the output signal of the third adder; a 1-bit D / A converter for inputting the input signal of the quantizer and outputting an analog output signal to the outside; A first delay unit for inputting an output signal;
A first multiplier that inputs the output signal of the delay device and outputs the first loopback signal; and a second multiplier that inputs the output signal of the first delay device and outputs the second loopback signal. Delay device, a second multiplier and a third multiplier for inputting the output signal of the third adder, an output signal of the second multiplier and a fourth loopback signal are input. The output signal of the fourth adder and the output of the third multiplier are input to the fourth adder.
And a fourth delayer for receiving the output signal of the fourth adder and outputting the third loopback signal.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, the oversampling D / A converter includes adders 1, 2, 3, 9, a quantizer 4, a 1-bit D / A converter 5, delay devices 6, 8, 11, 13, and a multiplier 7. , 9 and 10 and handles an input signal X, a quantizer input signal Y ₂ , a quantizer output signal Y ₁ , and an output signal Z. Here, since the coefficients of the multipliers 7, 9, and 10 are all powers of 2, the multiplier can be actually configured by a circuit required by wiring, such as a bit shift and an inverter.

The output signal Y ₁ of the quantizer 4 is delayed by one sample time by the delay unit 6. The output of the delay device 6 is multiplied by the multiplier 7, and the input signal X and the adder 1 are added.
Is added at the output of. After one more sample time, the output of the delay unit 6 is delayed by one sample time, and the adder 2
Is added to the output of the adder 1. The output signal Y ₂ of the quantizer 4 is feedback-controlled with respect to the input signal of 2 sample times. Similarly, with respect to the input signal Y ₂ of the quantizer, feedback control of 2 sample times is applied by the delay devices 11 and 13. The control for the output signal Y1 and the input signal Y2 of the quantizer 4 is
Since they are performed at the same time, the speed of the circuit is improved. Next, the transfer function of this circuit is obtained by using the Z transform, as follows.

[0008]

Therefore, the equation is the oversampled D / A of FIG.
It is a formula of the input signal Y ₂ of the quantizer 4 of the converter circuit. Here, when the expression of the input signal Y ₂ of the quantizer 27 of the oversampling D / A converter circuit of FIG. 2 shown in the conventional example is compared with the expression, the expression is equal to the expression and both expressions agree with each other. This means that the same operation is guaranteed for the same input signal. Paying attention to the circuit of FIG. 1, the number of additions required from the input of the input signal to the adder 1 to the output of the output signal Z of the 1-bit D / A converter 5, that is, within one sample The number of additions required for serial processing is 3
The number of additions is reduced by one compared to the conventional circuit. By reducing the number of additions, the operating speed of each adder can be reduced.

[0010]

As described above, according to the present invention, the number of continuous additions in one sample is reduced from 4 to 3, so that the operation speed required for each adder can be reduced. Therefore, the speed of the converter as a whole is increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional oversampled D / A converter.

[Explanation of symbols]

1, 2, 3, 12 adder 4 quantizer 5 1-bit D / A converter 6, 8, 11, 13 delay device 7, 9, 10 multiplier X input signal Y ₂ quantizer input signal Y ₁ quantum Output signal Z output signal

Claims (1)

[Claims] 1. A first adder for inputting a digital input signal and a first loopback signal input from the outside,
A second adder for inputting the output signal of the first adder and the second loopback signal, and a third adder for inputting the output signal of the second adder and the third loopback signal. An adder, a quantizer that inputs the output signal of the third adder, a 1-bit D / A converter that inputs the input signal of the quantizer and outputs an analog output signal to the outside, and the quantum Delay unit for inputting the output signal of the multiplexer, a first multiplier for receiving the output signal of the first delay unit and outputting the first loopback signal, and the first delay unit Second delay unit that inputs the output signal of the second loopback signal and a second delay unit that inputs the output signal of the third adder
And a third multiplier, a fourth adder for inputting the output signal of the second multiplier and the fourth loopback signal, and an output signal of the third multiplier. A third delay device that outputs the fourth loopback signal; and a fourth delay device that inputs the output signal of the fourth adder and outputs the third loopback signal. Oversampled D / A converter.