JPH05252007A - Clock duty compensation circuit - Google Patents

Abstract

PURPOSE:To obtain a clock duty compensation circuit compensating a clock duty to a desired value with simple configuration. CONSTITUTION:The leading and trailing of an input clock CK2 are smoothed by a low pass filter 10. Its output signal S1 is inverted by an inverter 13 into an inverted clock CK4, it is integrated by a resistor R16 and a capacitor C19 and a DC level SB4 is fed to a noninverting input of an operational amplifier 15. The inverted clock CK4 is inverted by an inverter 14 into an inverting clock CK3, it is integrated by a resistor R17 and the capacitor C19 and a resulting DC level SB3 is fed to an inverting input of the operational amplifier 15. The operational amplifier 15 adds a difference between the levels SB4 and SB3 to the said signal S1 via a resistor R18 to correct the bias and the result is fed to the inverter 13 to correct a logic value discrimination timing thereby varying the clock duty of the inverted clocks CK4, CK3 as a prescribed value.

Description

Detailed Description of the Invention

[0001]

This invention relates to a duty (Dut)
The present invention relates to a clock duty compensation circuit that compensates a duty to a desired value even if y) is a varying clock.

[0002]

2. Description of the Related Art In recent years, in order to meet various needs of high-speed broadband services, studies on the introduction of optical communication systems into subscriber systems have been actively conducted.

For example, the optical transmission rate is 6 Mbps, 32
Mbps, 52 Mbps, 156 Mbps, 622 mp
An optical transmission module (electric signal to optical signal conversion module) compatible with transmission speeds such as s, 2.4 Gbps, etc. is being developed.

In such an optical transmission module, there is a demand for miniaturization, high reliability, low power consumption and low cost of the optical interface section.

For example, FIG. 2 shows a functional block diagram of an optical transmission module according to a conventional example.

In FIG. 2, the NRZ data DA0 is supplied to the code conversion circuit 3. Meanwhile, input clock CK0
(The clock duty: the time ratio of the high level and the low level is, for example, 1: 1, that is, 50%. The frequency is f0.) Is supplied to the tuning circuit 4. The tuning circuit 4 is a tuning circuit using a crystal oscillator or the like, and the tuning frequency is set to f0. The tuning circuit 4 outputs the sine wave signal S0 having the frequency f0 and supplies it to the limiter circuit 5. The limiter circuit 5 limits the supplied sine wave signal S0 having the frequency f0 within a predetermined range and outputs a duty cycle as a rectangular wave.
A clock CK1 of 50% is obtained and supplied to the code conversion circuit 3. The code conversion circuit 3 performs a logical product or the like on the supplied NRZ data by the supplied clock CK1 to perform RZ.
The data DA1 is converted and supplied to the light emitting element drive circuit 7. The light emitting element drive circuit 7 converts the RZ data DA1 into a drive signal for driving the light emitting element 8 and supplies the drive signal to the light emitting element 8. The light emitting element 8 converts the optical signal DA2 according to the supplied drive signal and outputs the optical signal DA2 to the optical transmission line.

[0007]

In the optical transmission module as described above, the input clock CK0 is actually obtained by dividing the clock oscillated with the crystal oscillator as the original oscillation by the clock circuit PWB (module) or the like. In many cases, it is generated and supplied to the optical transmission module.

The clock CK0 supplied in such a case
In order to perform high-speed optical transmission like the above optical transmission speed example,
A high-speed clock is supplied. For example, RZ data is 32M
In bps, the pulse cycle of 1 clock is 1 / 32MHz
(Sec) = 31.25 nsec, and when the duty of this one clock is 50%, the high-level pulse width is 15.625 nsec. Even with a short signal line transmission line, such a clock with a short pulse width is affected by the electromagnetic field generated by the digital signals of other circuits, and the fluctuation of the pulse width or pulse period, for example. Receive. Such a variation becomes a large percentage (not negligible) variation when a high-speed clock is used, and for example, the duty of the clock may vary within a range of about 50% ± 10%.

If such a duty variation occurs, the output RZ data DA1 of the code conversion circuit 3 is also varied in duty, and the duty of the light-modulated optical signal is also influenced and varied. In addition, when the RZ data and the clock are extracted from the optical signal by the optical receiving module on the receiving side, the duty ratio of the optical signal is received while fluctuating.
Since there is a problem that the Z data and the clock cannot be extracted, the tuning circuit 4 extracts only the constant frequency f0 and the limiter circuit 5 limits it to obtain the clock CK1 of 50% duty. Since a tuning circuit is configured by using a crystal oscillator or the like in 4, it is difficult to integrate it.
Was limited by the configuration of.

The present invention has been made in view of the above problems, and an object of the present invention is to compensate a duty to a desired value with a simple configuration even if a clock whose duty is fluctuated is taken in. A clock duty compensation circuit capable of

[0011]

In order to achieve the above object, the present invention is realized by the first invention including the following characteristic means.

That is, a filter means (for example, a low-pass filter) which takes in a clock signal and outputs a filter signal in which the rising and falling edges of this clock signal are smoothed is judged by the first threshold level. First inverts and outputs a first inversion signal
Second inversion means (for example, a logic gate inverter, an operational amplifier inverter, etc.) and the first inversion signal which is judged by the second threshold level and inverted, and outputs the second inversion signal. Means (for example, a logic gate inverter or an operational amplifier inverter), an average level of the first inverted signal (for example, DC level), and an average level of the second inverted signal (for example, DC). Level) and a difference means for outputting the difference signal (eg, DC level), and the filter signal or the first threshold level is corrected according to the difference signal value. A corrected (eg bias corrected etc.) filtered signal is provided as an input to the first inverting means or the input filter signal at the corrected first threshold level in the first inverting means. And a correction means for determining,
The clock duty of the first and second inverted signals is compensated to a predetermined value.

The second invention is also realized by including the following characteristic means.

That is, a filter means for taking in a clock signal and outputting a filter signal in which the rising and falling edges of this clock signal are smoothed, and the above-mentioned filter signal are judged at a threshold level and inverted, and an inverted signal is output. Inversion means, reference signal output means for outputting a reference level signal for setting a predetermined clock duty, and a difference for outputting a difference signal by obtaining a difference between the average level value of the inversion signal and the reference level signal value. Means for correcting the filter signal or the threshold level in accordance with the difference signal value, and supplying the corrected filter signal as an input to the inverting means or inputting the corrected threshold level in the inverting means. Compensation means for determining the filter signal is provided to compensate the clock duty of the inverted signal to a predetermined value. It is characterized in.

[0015]

According to the first aspect of the invention, the difference between the average level value of the first inverted signal and the average level value of the second inverted signal is obtained, and the bias signal is corrected by the difference signal. Since it is supplied to the first inverting means in such a manner, the determination timing with respect to the first threshold level is corrected, and the duty of the first and second inversion signals can be changed accordingly. When the average level value of the inversion signal and the average level value of the second inversion signal become equal (that is, the duty becomes a predetermined value, for example, 50%), the differential signal value outputs 0 and the filter signal It is possible to stop the update of the bias correction value for and output the clock of a predetermined duty from the first and second inverting means.

Further, by correcting the first threshold level of the first inverting means by the difference signal, the timing for determining the logical value for the input filter signal is corrected, and the first and second values are the same as above. The duty of the inverted signal can be changed, and the average level value of the first inverted signal becomes equal to the average level value of the second inverted signal (that is, the duty becomes a predetermined value, for example, 50%).
And the difference signal value is output as 0 to stop the update of the level correction for the first threshold level and output a clock having a predetermined duty from the first and second inverting means.

According to the second aspect of the invention, the reference level signal is supplied to the difference means as a DC voltage signal corresponding to a desired duty, so that the difference from the average level value of the inverted signal of the inversion means. By determining the value and supplying it to the inverting means by performing bias correction or the like of the filter signal based on this difference value, the determination timing for the threshold level is corrected, and the duty of the inverted signal can be changed accordingly. When the average level value of the inverted signal and the reference level value become equal (that is, the desired duty), 0 is output as the difference signal value, the update of the bias correction value for the filter signal is stopped, and the reference value is obtained. A clock having a desired duty corresponding to the level value can be output from the inverting means.

Further, by correcting the threshold level of the inverting means by the difference signal of the second invention, the timing for judging the logical value for the input filter signal is corrected and the duty of the inverted signal is changed in the same manner as above. When the average level value of the inverted signal and the reference level value become equal (that is, the desired duty), the difference signal value is output as 0 and the updating of the level correction value for the threshold level is stopped. A clock having a desired duty corresponding to the reference level value can be output from the inverting means.

With the above-mentioned structure, it can be realized with a simple structure and can be compensated for a desired clock duty, which is suitable for integration.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment in which the present invention is applied to a clock duty compensation circuit of an optical transmission module will be described with reference to the drawings.

First Embodiment of Optical Transmission Module The purpose of this first embodiment is to provide an optical transmission module which has a simple structure and is capable of performing optimum code conversion even when a clock whose duty varies. To be realized.

To achieve this object, a clock duty compensating circuit for compensating the duty of an input clock whose duty is fluctuating to 50% is provided, and the input NRZ data is converted into RZ data by using this compensated clock. Then, the RZ data is converted into an optical signal.

FIG. 1 is a functional block diagram of the optical transmission module according to the first embodiment.

In FIG. 1, the optical transmission module is composed of a code conversion circuit 12, a light emitting element drive circuit 21, a light emitting element 22, and a clock duty compensation circuit 1. The clock duty compensation circuit is composed of one inverter 13, 14, an operational amplifier 15, an input low pass filter 10, resistors R17, R16, a bias resistor R18, and a capacitor C19. The input low pass filter 10 is composed of a resistor 24 and a capacitor C25.

The input NRZ data DA3 (FIG. 3 (B)) is supplied to the code conversion circuit 12. Meanwhile, input clock CK
2 (FIG. 3A) is the resistance 2 of the input low-pass filter circuit.
4 is supplied. In this input low-pass filter circuit 10, the cutoff frequency fc is, for example, fc = 1 / (2
π · R24 · C25), and the values of R24 and C25 are set so that the cutoff frequency fc and the pulse frequency f0 of the input clock CK2 have a relationship of f0 ≦ fc. More strictly, it is desirable to set in consideration of the worst possible input clock duty. The output of the input low-pass filter 10 is the input clock CK2.
Waveforms that have been distorted to some extent (smooth waveforms)
(FIG. 3 (C)) is necessary because it is easy to detect the rising timing from the low level to the high level in the inverter 13. This is because, for example, if the rising is sudden, there is a problem that it is difficult to detect the level change at the input of the inverter 13. In this way, the output signal S1 of the input low-pass filter 10 is supplied to the inverter 13.

The inverter 13 inverts the input signal S1 and supplies the inverted signal CK4 to the inverter 14 and the positive phase (+) input (non-inverting input) of the operational amplifier 15 via the resistor 16. The inverter 14 inverts the input signal CK4 and supplies the inverted signal CK3 to the code conversion circuit 12 and also the resistor R
It is supplied to the negative phase (-) input (inverting input) of the operational amplifier 15 via 17. Signal C output from the inverter 13
K4 is an integrated signal SB4 which is cut off at a high frequency by a low pass filter composed of a resistor R16 and a capacitor C19.
Are supplied to the positive phase (+) input.

Further, the output signal CK3 of the inverter 14 is also supplied to the negative phase (-) input of the integrated signal SB3 which is cut off in the high frequency band by the low pass filter composed of the resistor R17 and the capacitor C19. Cutoff frequency of the above two low pass filters 1 / (2π · R17 · C19) = f
c1 and cutoff frequency 1 / (2π ・ R16 ・ C1
9) = fc2 needs to have a relationship of fc1 = fc2, and more preferably has a relationship of R17 = R16. Then, it is desirable that the relationship with the frequency f0 of the input clock CK2 is set to the relationship of f0> fc1 = fc2. This is because the rectangular signals supplied from the inverters 13 and 14 are sufficiently integrated to obtain an average direct current (DC) level with a small level change, and a positive phase (+) input and a negative phase (-) input of the operational amplifier 15 are obtained. It is to supply to.

Then, for example, Du of the input clock CK2
When ty is 70% (that is, when the high level is 70% and the low level is 30%), the duty of the output clock CK4 of the inverter 13 is 30% (that is, the high level is 30%).
And when the low level is 70%. ), The output of the inverter 14 is inverted and the DUTY of the clock CK3 is 70.
%. Then, for example, the above clocks CK4 and CK3
Is SB4 and SB3, the magnitude relationship of the integrated value (DC level) is SB3> SB4, and the operational amplifier 15 is a differential amplifier. Output (SB4-SB3)
Output from the inverter 1 via the bias resistor R18.
Bias level correction for the differential output (SB4 to SB3) is applied to the input of the signal S1 for the signal S1.

For example, when the value of SB4 is 1 V, the SB
If the value of 3 is 2V, SB4-SB3 = -1V is added to the signal S1 and supplied to the input of the inverter 13.
In this way, the direct current (DC) level (bias level) of the signal S1 is lowered by, for example, -1V as compared with that before the correction, and therefore the inverter 13 having a predetermined threshold level operates the signal S
1 tends to detect the upper side of the waveform, and in such a tendency, the time for detecting the high level of the input waveform tends to become shorter, and the high level time width of the output waveform of the inverter 13 becomes shorter. It is operated to reduce the duty of the clock from 70% to 50%. When the above correction is performed and the value of SB4 to SB3 becomes 0, it is determined that the duty has become 50%, and the updating of the bias correction is stopped. In this way, the clocks CK3 and CK4 having a duty of 50% (FIGS. 3D and 3E) can be obtained.

By the above, the signal CK
4 and the clock duty of the signal CK3 can be compensated to 50%. The duty of the output DA4 of the code conversion circuit 12 is set to 50 by setting the clock Duty to 50%.
%, And the duty of the optical signal is also set to 50% and output to the transmission line, so that there is a high probability when a clock or data is obtained after converting the light in the optical receiving module on the receiving side into an electric signal. It can be reproduced faithfully.

The clock CK3 obtained as described above is supplied to the code conversion circuit 12. The code conversion circuit 12 logically ANDs the input NRZ data DA3 with the clock CK3 to obtain RZ data DA4 (FIG. 3 (F)) and supplies it to the light emitting element drive circuit 21 to drive the light emitting element 22. And is supplied to the light emitting element 22. The light emitting element 22 uses, for example, a laser diode or the like to convert it into an optical signal and outputs it to the transmission path.

FIG. 3 is an operation timing chart of the optical transmission module according to the first embodiment.

In FIG. 3, (A) shows the waveform of the input clock CK2 with varying duty. (B)
Is the timing of the input NRZ data DA3. (C)
FIG. 4 is a waveform diagram of the integrated output signal S1 of the input low pass filter 10. (D) is an output of the inverter 14, and is a waveform diagram of the clock CK3 at the time when the duty is compensated to 50%. (E) is an output of the inverter 13, and is a waveform diagram of the clock CK4 at the time when the duty is compensated to 50%. (F) is an output of the code conversion circuit 12, and is a waveform diagram converted into RZ data DA4.

According to the first embodiment described above, even if the clock CK2 whose clock duty varies,
Since the duty of the clock CK3 supplied to the code conversion circuit 12 can always be compensated and supplied to 50%, the RZ data obtained by code conversion can also be compensated to the duty of 50%, and this RZ data is optically converted. The optimum optical signal can be output.

Further, the clock duty compensation circuit 1 does not use a crystal oscillator as in the prior art, but is composed only of a resistor, a capacitor, an inverter and an operational amplifier, so that the circuit configuration is simple and easy to integrate. This can contribute to downsizing of the optical transmission module.

Second Embodiment of Optical Transmission Module FIG. 4 is a functional block diagram of an optical transmission module according to the second embodiment.

In FIG. 4, the clock duty compensation circuit 2 of this optical transmission module is provided with a reference power supply circuit 26 instead of the resistor R17 shown in FIG. 1, and outputs the reference voltage signal Vref to the negative side of the operational amplifier 15. The phase (-) input (inverted input) is supplied, and one end of the capacitor C19 is connected to the ground.
Other configurations are realized by the same configurations as in FIG. The same functional blocks as those in FIG. 1 are designated by the same reference numerals.

The clock duty compensation circuit 2 predetermines a reference voltage signal Vref for compensating for a predetermined clock duty from the reference power supply circuit 26 and supplies it to the negative phase (-) of the operational amplifier 15. On the other hand, the inverter 13 supplies the inverted signal CK4 to the low-pass filter composed of the resistor R16 and the capacitor C19 to obtain the average direct current (DC) level signal SB4, and inputs the positive phase (+) to the operational amplifier 15, as in FIG. Supply to (non-inverting input).

The operational amplifier 15 outputs the difference between the direct current (DC) level signal SB4 and the reference voltage signal Vref, and supplies this difference voltage signal to the inverter 13 via the bias resistor R18. By doing so, the bias voltage of the integrated signal S1 is corrected by the differential voltage signal and supplied to the inverter 13.

When the bias voltage of the integrated signal S1 changes, 1 and 0 are determined by the predetermined threshold value of the inverter 13 as described in the first embodiment, and the logical 1 for this integrated signal S1 is determined. Since the timing can be changed, the output pulse width of the inverter 13 can be changed, that is, the clock duty can be changed. Then, the direct current (DC) level signal SB4
The output of the inverter 13 is corrected until the difference between the reference voltage signal Vref and the reference voltage signal Vref becomes 0, and the reference voltage signal Vref is corrected.
Is supplied to the inverter 14 after being compensated for by a predetermined clock duty corresponding to.

The code conversion and the optical conversion after the inverter 14 are the same as those in the above-mentioned first embodiment, so that the description of the operation will be omitted.

The two stages of the inverters 13 and 14 are connected to each other so that the input NRZ data DA3 and the clock have the same phase.

According to the second embodiment described above, even if the clock CK2 whose clock duty varies,
Since the duty of the clock CK3 supplied to the code conversion circuit 12 can always be compensated and supplied to the duty corresponding to the reference voltage signal, the RZ data obtained by code conversion can also be constantly compensated for the duty. It is possible to optically convert data and output an optimum optical signal.

Further, the clock duty compensation circuit 1 does not use a crystal oscillator as in the prior art, but is composed of only a resistor, a capacitor, an inverter, an operational amplifier, and a reference power supply circuit, so that the circuit configuration is simple. Thus, the integration can be facilitated, and the optical transmission module can be miniaturized.

The clock duty can be freely changed by changing the reference voltage signal Vref.

In FIGS. 1 and 4 of the above embodiment,
Although the input low pass filter 10 is used, it is not limited to this. For example, the basic clock frequency f0 of the input clock CK2 is stored, and it can be realized by, for example, a bandpass filter on the assumption that a frequency component higher than this frequency f0 is not included. In addition, in FIG. 1 and FIG. 4 described above, the input low pass filter 10 may be configured by using an active element (for example, an operational amplifier).

In FIGS. 1 and 4 of the above embodiment,
Although the operational amplifier 15 is used, it is not limited to this. For example, it can be realized by configuring a differential circuit by using a bipolar transistor or FET. Although the inverters 13 and 14 that are digital gates are used in FIGS. 1 and 4, the invention is not limited to this. For example, it can be realized by a configuration in which the inversion is performed by an operational amplifier.

Further, in the above embodiment, the voltage is corrected by the bias of the signal S1 by the output of the operational amplifier 15, but the present invention is not limited to this. For example, instead of correcting the bias of the signal S1, inversion is performed by the operational amplifier in order to change the threshold level for logical level determination, and the threshold level for inversion is corrected by the output of the operational amplifier 15. Also, the clock duty can be compensated to a desired value.

In the optical transmission module of the above embodiment, the transmission of the optical signal has been described, but the clock duty compensation is also applied to the optical receiving module for extracting the data and the clock from the optical signal output from the optical transmission module. Circuitry can be applied. For example, when the optical receiving module receives an optical signal, the light receiving element converts the optical signal into an electric signal, and the electric signal is supplied as reception RZ data to, for example, a decoding conversion circuit. Further, when the clock is extracted from the received RZ data by the clock extraction circuit and the duty of this clock is fluctuated due to the influence of the transmission path, the fluctuating clock is detected by the clock compensation circuit of FIG. 1 or 4. It is also possible to compensate the duty to a desired value and use the compensated clock to convert the RZ data into NRZ data and output the NRZ data.

In the code conversion circuit 12 of FIGS. 1 and 4 of the above embodiment, the conversion of input NRZ data into RZ data has been described as an example, but the invention is not limited to this. For example, CMI (Co
It can also be applied to a code conversion circuit for converting into a de Mark Inversion (de Mark) code. This CMI code converts, for example, a logical 0 of the input NRZ data into 01,
It is obtained by converting 1 into 11 or 00. Also, this code conversion circuit includes several D flip-flops,
It can be easily implemented with several logic gates.

In the above embodiments, the clock duty compensation circuit is applied to the optical transmission module as an example, but the invention is not limited to this. It can also be applied to other circuits and devices that require a clock.

[0052]

As described above, according to the clock duty compensation circuits of the first and second aspects of the present invention, even if a clock with varying duty is input, a clock compensated to a desired duty value is output. can do. Also,
Since each means has a simple structure and is easy to integrate, it can contribute to downsizing of the circuit.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an optical transmission module according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram of an optical transmission module according to a conventional example.

FIG. 3 is an operation timing chart of the optical transmission module according to the first embodiment of the present invention.

FIG. 4 is a functional block diagram of an optical transmission module according to a second embodiment of the present invention.

[Explanation of symbols]

1, 2 ... Clock duty compensation circuit, 10 ... Input low-pass filter, 13, 14 ... Inverter, 15 ... Operational amplifier, 26 ... Reference power supply circuit, C19 ... Capacitor, R1
6, R17 ... resistance.

Claims (2)

[Claims] 1. A filter means for taking in a clock signal and outputting a filter signal in which the rising and falling edges of this clock signal are smoothed, and the filter signal is judged at a first threshold level and inverted, First inversion means for outputting an inversion signal of the first inversion signal, second inversion means for inversion by judging the first inversion signal at a second threshold level, and outputting a second inversion signal; Difference means for obtaining the difference between the average level of the inversion signal and the average level of the second inversion signal, and outputting the difference signal, and the filter signal or the first signal according to the difference signal value.
The threshold value level is corrected and the corrected filter signal is supplied as an input to the first inverting means, or the input filter signal is judged by the corrected first threshold level in the first inverting means. A clock duty compensating circuit comprising: a compensating means for compensating the clock duty of the first and second inverted signals to a predetermined value. 2. A filter means for taking in a clock signal and outputting a filter signal in which the rising and falling edges of this clock signal are smoothed, and deciding the filter signal at a threshold level to invert it and outputting an inverted signal. Inversion means, reference signal output means for outputting a reference level signal for setting a desired clock duty, and a difference for outputting a difference signal by obtaining a difference between the average level value of the inversion signal and the reference level signal value. Means for correcting the filter signal or the threshold level according to the difference signal value, and supplying the corrected filter signal as an input to the inverting means or inputting the corrected threshold level in the inverting means. Compensation means for determining the filter signal is provided to compensate the clock duty of the inverted signal to a predetermined value. The clock duty compensating circuit according to claim.