JP2001102878A - Differential amplifier, signal detection circuit, detection circuit for serial data signal and serial data recovery circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential amplifier, a signal detector, a detector for serial data and a serial data recovery device especially suitable for detecting the existence of signals of serial data at high speed. SOLUTION: A differential circuit composed of first an second transistor M1 and M1 for inputting the signals of serial data of differential signals and a differential circuit composed of third and fourth transistors M3 and M4 for inputting offset signals are provided and a comparator is provided for comparing the level of the node of the drains of the first and third transistors M1 and M3 with the level of the node of the drains of the second and fourth transistors M2 and M4. While no serial data signal is applied, an output level from the comparator is fixed and when the serial data signal is applied, an output for changing the level corresponding to input data can be provided. Such a signal detecting circuit enables high speed operation and can detect the existence of signals of high speed serial data in CMOS configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fiber channel and a gigabit Ethernet (Gigabit Ethernet).
The present invention relates to a differential amplifier, a signal detection circuit, a serial data signal detection circuit, and a serial data recovery circuit suitable for high-speed serial communication such as bit Ethernet).

[0002]

2. Description of the Related Art Development of high-speed serial communication using twisted pair cables and optical fibers, such as Fiber Channel and Gigabit Ethernet, has been promoted. In such high-speed serial communication, when serial data is transmitted as an optical signal using an optical fiber as a transmission medium, photoelectric conversion is performed at a receiving end, and the signal is received as a differential electric signal.

When data is received through a high-speed serial transmission line, whether a transmission medium is connected or not, whether received data can be reproduced at an error rate less than a specified error rate, whether the signal amplitude is equal to or more than a predetermined value, is determined. Is determined by detecting
As a result, if the amplitude of the received signal is equal to or larger than a certain threshold, the signal reproduction processing is performed. If the amplitude of the received signal is equal to or smaller than a certain threshold, the signal reproduction processing is stopped, and the next signal Processing is performed to prepare for the reception period.

Conventionally, most of the elements adapted to such a serial interface are manufactured by a bipolar manufacturing process, and a signal detection circuit for detecting the presence or absence of a serial signal is constituted by, for example, a circuit as shown in FIG. Have been.

In FIG. 8, an input terminal 101 is derived from the base of a transistor Q101. Transistor Q
The collector of 101 is connected to the power supply line 103. The emitter of transistor Q101 is connected to ground line 104 via resistor R101 and to the base of transistor Q102. Transistor Q10
2 are connected to the power supply line 103. The emitter of transistor Q102 is connected to ground line 104 via capacitor C101 and to the base of transistor Q103. Transistor Q103
Are connected to the power supply line 103. The emitter of transistor Q103 is connected to ground line 104 via resistor R102 and to output terminal 102.

The transistor Q101 operates as an emitter follower, and a signal from the input terminal 101 is supplied to the base of the transistor Q102 via the transistor Q101.

A capacitor C101 is connected to the emitter of the transistor Q102, and the transistor Q102 is connected to the input terminal 101 via the transistor Q101.
Until the potential of the input signal applied to the base of the transistor reaches the maximum, the capacitor C101 is charged, so that the potential of the emitter of the transistor Q102 increases.

Thereafter, the transistor Q
When the potential of the input signal applied to the base of transistor Q102 via transistor 101 decreases, transistor Q1
02 is cut off, and the electric charge of the capacitor C101 is held.

Therefore, the peak value of the input signal is held at the emitter potential of transistor Q102. The potential of the emitter of this transistor Q102 is applied to the output terminal 102 via an emitter follower transistor Q103.
Output from Thus, the peak level of the signal from the input terminal 101 is detected from the output terminal 102.

Since the discharge path of the electric charge of the capacitor C101 can be set by the base current of the transistor Q103, the discharge time constant can be set large.

[0011]

As described above, conventionally,
In the high-speed serial interface, as shown in FIG. 8, whether or not a signal is received is detected by a detection circuit of a bipolar transistor. This detection circuit determines whether or not the amplitude level of the received signal is equal to or more than a predetermined value. It is configured to detect.

By the way, in order to reduce power consumption,
It has been studied to configure a serial interface with CMOS transistors. When the serial interface is formed by CMOS transistors, the transistor Q10 in the serial signal detection circuit shown in FIG.
A configuration in which 1 to Q103 are directly replaced with MOS transistors can be considered.

However, CMOS transistors have gm
Since the (transconductance) is low, the time constant cannot be increased, and it is difficult to charge / discharge the peak value of the input signal to / from the capacitor. Therefore, as described above, when handling high-speed serial data, the transistors Q101 to Q10 in the serial signal detection circuit shown in FIG.
It is difficult to form a serial signal detection circuit by replacing 3 with a MOS transistor as it is.

Accordingly, it is an object of the present invention to provide a differential amplifier, a signal detection circuit, a detection circuit for a serial data signal, and a serial data recovery circuit which are particularly suitable for detecting high-speed serial data. It is in.

[0015]

According to the present invention, there is provided a first differential circuit comprising a first transistor and a second transistor whose sources or emitters are commonly connected to each other and to which a differential input signal is input. A third transistor and a fourth transistor having their sources or emitters commonly connected to each other, and a second differential circuit to which a differential offset signal is inputted, wherein a drain of the first transistor is provided. Alternatively, the differential amplifier is characterized in that a collector and a drain or a collector of a third transistor are commonly connected, and a drain or a collector of the second transistor is commonly connected with a drain or a collector of the fourth transistor. .

The present invention comprises a first transistor and a second transistor whose sources or emitters are commonly connected to each other, and a first differential circuit to which a differential input signal is inputted, and a first source or a second source. A third transistor and a fourth transistor whose emitters are commonly connected,
A second differential circuit to which a differential offset signal is input;
The drain or collector of the first transistor is commonly connected to the drain or collector of the third transistor,
, The drain or collector of the fourth transistor is commonly connected to the drain or collector of the fourth transistor, the output of the connection point between the drain or collector of the first transistor and the drain or collector of the third transistor, and the drain of the second transistor Or a comparison circuit for comparing the collector with the output of the connection point of the drain or the collector of the fourth transistor, wherein the presence or absence of an input signal is detected from the output of the comparison circuit. is there.

According to the present invention, a differential serial data input terminal to which a differential serial data signal is input, a differential offset signal input terminal to which a differential offset signal is input, and a differential serial data signal A signal output at a predetermined level when no signal is detected, and an output terminal for outputting a signal that changes in accordance with the input differential serial data when a differential serial data signal is detected. And a judgment circuit for judging whether or not serial data has been input from the output of the signal detection circuit. The signal detection circuit comprises a first transistor and a second transistor whose sources or emitters are commonly connected. A first differential circuit to which a differential input signal is input, a third transistor whose source or emitter is commonly connected, and a third transistor A second differential circuit to which a differential offset signal is input, a drain or a collector of the first transistor and a drain or a collector of the third transistor being connected in common, and a drain of the second transistor Alternatively, the collector and the drain or the collector of the fourth transistor are commonly connected, the output of the connection point between the drain or the collector of the first transistor and the drain or the collector of the third transistor, and the drain or the collector of the second transistor are connected to the second transistor. A comparison circuit for comparing an output of a connection point of a drain or a collector of the fourth transistor, and a differential serial data input terminal is derived from a gate or a base of the first transistor and a gate or a base of the second transistor; The gate or base of the third transistor and the fourth transistor Deriving a differential offset signal input terminal from over preparative or base, without to derive an output terminal from the output of the comparison circuit, determination circuit,
A serial data signal detection circuit characterized in that it is determined whether or not the output signal of the signal detection circuit changes during a predetermined time to determine whether or not a serial data signal has been input.

According to the present invention, there is provided a first PLL loop which compares input serial data with an output of an oscillator whose frequency can be controlled, and controls the oscillator based on the comparison output;
A second PLL loop that compares the reference clock with the output of the oscillator and controls the oscillator based on the comparison output, a serial data signal detection circuit that detects the presence or absence of serial data, and an output of the serial data detection circuit A switching circuit for switching between the first PLL loop and the second PLL loop. When serial data is not input, the oscillation frequency of the oscillator is controlled by the reference clock, and when serial data is input, In a serial data recovery circuit in which an oscillator is controlled by serial data, a serial data signal detection circuit receives a differential serial data input terminal to which a differential serial data signal is input, and a differential offset signal. If the differential offset signal input terminal and the differential serial data signal are A signal detection circuit having an output terminal from which a signal of a predetermined level is output, and when a signal of differential serial data is detected, a signal that changes according to the input differential serial data is output; And a judgment circuit for judging whether or not serial data has been input from the output of the signal detection circuit. The signal detection circuit includes a first transistor and a second transistor whose sources or emitters are commonly connected. A first differential circuit to which a differential input signal is input, and a third transistor and a fourth transistor whose sources or emitters are commonly connected to each other, and to which a differential offset signal is input. The second differential circuit, the drain or collector of the first transistor and the drain or collector of the third transistor are commonly connected, and the drain or collector of the second transistor is connected. The drain or collector of the fourth transistor is commonly connected to the drain or collector of the fourth transistor, the output of the connection point between the drain or collector of the first transistor and the drain or collector of the third transistor, and the drain or collector of the second transistor. A comparison circuit for comparing an output of a connection point between a drain and a collector of the fourth transistor, wherein a differential serial data input terminal is derived from the gate or base of the first transistor and the gate or base of the second transistor. The differential offset signal input terminal is derived from the gate or base of the third transistor and the gate or base of the fourth transistor, and the output terminal is derived from the output of the comparison circuit. Judge whether the output signal of the signal detection circuit changes during the The serial data recovery circuit is characterized in that it is determined whether or not the data has been input.

A differential circuit including first and second transistors to which a serial data signal of a differential signal is input;
A differential circuit including a third and a fourth transistor to which an offset signal is input is provided, and a level of a connection point between a drain of the first transistor and a drain of the third transistor, a drain of the second transistor, A comparator for comparing the level of the connection point with the drain of the fourth transistor is provided. When the serial data signal is not supplied from the comparator, the output level is constant. When the serial data signal is supplied,
An output whose level changes according to the input data is obtained. Such a signal detection circuit can operate at high speed and can detect the presence or absence of a high-speed serial data signal as a CMOS configuration.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an example of a signal detection circuit to which the present invention is applied.

In FIG. 1, an NMOS transistor M1
Is connected to the source of the NMOS transistor M2. Source of NMOS transistor M1 and NMOS
The connection point of the transistor M2 with the source is connected to the drain of the NMOS transistor M11. The source of the NMOS transistor M11 is connected to the ground line 3. N
The gate of the MOS transistor M1 is connected to the input terminal 1. The gate of the NMOS transistor M2 is the input terminal 2
Connected to.

The source of the NMOS transistor M3 and NM
The source of the OS transistor M4 is connected. NMO
Source of S transistor M3 and NMOS transistor M
4 is connected to the drain of the NMOS transistor M12. The source of the NMOS transistor M12 is connected to the ground line 3. The gate of the NMOS transistor M3 is connected to the offset input terminal 11. The gate of the NMOS transistor M4 is connected to the offset input terminal 12.

The drain of the NMOS transistor M1 and N
The drain of the MOS transistor M3 is commonly connected,
A connection point between the drain of the NMOS transistor M1 and the drain of the NMOS transistor M3 is connected to the drain and the gate of the PMOS transistor M5. At the same time, a connection point between the drain of the NMOS transistor M1 and the drain of the NMOS transistor M3 is connected to the gate of the NMOS transistor M7. The source of the PMOS transistor M5 is connected to the power supply line 4.

The drain of the NMOS transistor M2 and N
The drain of the MOS transistor M4 is commonly connected,
A connection point between the drain of the NMOS transistor M2 and the drain of the NMOS transistor M4 is connected to the drain and the gate of the PMOS transistor M6. At the same time, a connection point between the drain of the NMOS transistor M2 and the drain of the NMOS transistor M4 is connected to the gate of the NMOS transistor M8. The source of the PMOS transistor M6 is connected to the power supply line 4.

The source of the NMOS transistor M7 and NM
The source of the OS transistor M8 is connected. NMO
Source of S transistor M7 and NMOS transistor M
8 is connected to the drain of the NMOS transistor M13. The source of the NMOS transistor M13 is connected to the ground line 3.

The drain of the NMOS transistor M7 is P
Connected to the drain of MOS transistor M9. PM
The drain of the OS transistor M9 and the gate of the PMOS transistor M9 are connected, and the gate of the PMOS transistor M9 and the gate of the PMOS transistor M10 are connected. The source of the PMOS transistor M9 is connected to the power supply line 4.

The drain of the NMOS transistor M8 is P
Connected to the drain of MOS transistor M10. At the same time, the drain of the NMOS transistor M8 is connected to the input terminal of the inverting amplifier 5. The source of the PMOS transistor M10 is connected to the power supply terminal 4.

The output terminal of the inverting amplifier 5 is connected to the input terminal of the inverting amplifier 6. A resistor R1 is connected between the input terminal of the inverting amplifier 5 and its output terminal. From the output of the inverting amplifier 6, an output terminal 7 is derived.

NMOS transistors M11, M12, M
13 are commonly connected to each other, and the gates of these NMOS transistors M11, M12 and M13 are
Connected to the gate of transistor M14. The drain of the gate of the NMOS transistor M14 is connected. The source of the NMOS transistor M14 is connected to the ground terminal 3
Connected to. A current source I is provided between the power supply line 4 and the connection point of the gate and drain of the NMOS transistor M14.
0 is connected.

In the configuration shown in FIG. 1, a differential circuit is constituted by the NMOS transistor M1 and the NMOS transistor M2. Also, the NMOS transistors M3 and NM
A differential circuit is constituted by the OS transistor M4.

A drain of the NMOS transistor M1;
The drain and the source of the PMOS transistor M5 are connected to a connection point between the drain of the NMOS transistor M3 and the drain of the NMOS transistor M3.
S transistor M5 is NMOS transistor M1 and NM
It operates as a load circuit for the OS transistor M3.

The drain of the NMOS transistor M2 and the drain of the NMOS transistor M4 are commonly connected, and the drain of the NMOS transistor M2 is
A PMOS is connected to the connection point with the drain of the S transistor M4.
The drain and the source of the transistor M6 are connected, and P
The MOS transistor M6 operates as a load circuit for the NMOS transistor M2 and the NMOS transistor 4.

The NMOS transistors M1, M2,
M3 and M4 are set to the same size (gate width and gate length).

The gate of the NMOS transistor M1 and N
Input terminals 1 and 2 are led out of the gate of the MOS transistor M2, and the NMOS transistors M1 and N
The input to the differential circuit comprising the MOS transistor M2 is provided from input terminals 1 and 2.

The gate of the NMOS transistor M3 and N
Offset input terminals 11 and 12 are led out from the gate of the MOS transistor M4. The inputs to the differential circuit including the NMOS transistor M3 and the NMOS transistor M4 are offset input terminals 11 and 12 respectively.
Given by

The drain of the NMOS transistor M1 and N
The output signal SA at the node NA at the connection point with the drain of the MOS transistor M3 is supplied to the gate of the NMOS transistor M7. The output signal SB at the node NB at the connection point between the drain of the NMOS transistor M2 and the drain of the NMOS transistor M4 is
8 gates.

The NMOS transistor M7 and the NMOS transistor M8 form a differential circuit.
The differential circuit including the OS transistor M7 and the NMOS transistor M8 operates as a comparator that compares the output signal SA of the node NA with the output signal SB of the node NB.

The current mirror circuit composed of the PMOS transistor M9 and the PMOS transistor M10 is NM
It operates as an active load circuit for a differential circuit including the OS transistor M7 and the NMOS transistor M8.

NMOS transistors M11, M12, M
13, M14 constitute a current mirror circuit. N
MOS transistor M11 is NMOS transistor M1
NMOS transistor M12 operates as a current source for a differential circuit including NMOS transistors M3 and M4, and NMOS transistor M13 operates as a current source for a differential circuit including NMOS transistors M7 and M8. Operates as a current source.

When the output signal SA of the node NA is larger than the output signal SB of the node NB, the NMOS transistor M7 turns on and the NMOS transistor M8 turns off. Therefore, the output signal SC from the drain of the NMOS transistor M8 becomes high level.

When the output signal SB of the node NB is larger than the output signal SA of the node NA, the NMOS transistor M8 turns on and the NMOS transistor M7 turns off. Therefore, the output signal SC of the drain of the NMOS transistor M8 becomes low level.

The inverting amplifier 5 is negatively fed back by the resistor R1. The output of the inverting amplifier 5 is connected to the input of the inverting amplifier 6. These inverting amplifiers 5 and 6
Is for shaping the waveform of the output of the differential circuit composed of the NMOS transistor M7 and the NMOS transistor M8 and converting the output to a predetermined logic level. An output terminal 7 is derived from an output terminal of the inverting amplifier 6.

The operation of the signal detection circuit shown in FIG. 1 will be described. The input terminal 1 and the input terminal 2 are supplied with, for example, a high-speed serial data signal transmitted via a serial interface. This serial data signal is transmitted as positive and negative phase differential signals,
Input terminals 1 and 2 receive the differential serial data signal.

The offset input terminals 11 and 12 are supplied with low-level and high-level offset signals. This offset signal is supplied to input terminal 1 and input terminal 2
In order to detect whether a signal having an amplitude equal to or greater than a predetermined value is detected. The amplitude of the offset signal is set according to the amplitude of the differential serial data signal supplied to the input terminal 1 and the input terminal 2, and is smaller than the amplitude of the differential serial data signal to be detected. It is set to be the amplitude.

First, a case where a serial data signal is not supplied to the input terminals 1 and 2 will be described.

When a serial data signal is not supplied to the input terminals 1 and 2, the NMOS transistor M
The signals applied to the gates of 1 and M2 are undefined. At this time, the signal given to the input terminal 1 becomes larger than the signal given to the input terminal 2 or the signal given to the input terminal 2 becomes larger than the signal given to the input terminal 1 due to noise or the like.

First, it is assumed that the signal supplied to the input terminal 1 is larger than the signal supplied to the input terminal 2. At this time, in the differential circuit including the NMOS transistors M1 and M2, the NMOS transistor M1 is turned on and the NMOS transistor M2 is turned off.

On the other hand, since a low-level offset signal is supplied to the offset input terminal 11 and a high-level offset signal is supplied to the offset input terminal 12, the differential signal comprising the NMOS transistor M3 and the NMOS transistor M4 is provided. In the circuit, the NMOS transistor M4 is on and the NMOS transistor M3 is off.

The drain of the NMOS transistor M1 and N
Current i _A flowing through the node NA of the connection point between the drain of the MOS transistor M3 is the sum of the current i ₃ flowing through the current i ₁ and the NMOS transistor M3 through the NMOS transistor M1, a i _A = i ₁ + i ₃ Become. However, at this time, since the NMOS transistor M3 is off, the current i flowing through the node NA
_A has become a i _A = i _1.

On the other hand, the current i _B flowing through the node NB at the connection point between the drain of the NMOS transistor M 2 and the drain of the NMOS transistor M ₄ is the sum of the current i ₂ flowing through the NMOS transistor M ₂ and the current i ₄ flowing through the NMOS transistor M _4. And i _B = i ₂ + i ₄ . However, at this time, since the NMOS transistor M2 is off, the current i
_B is i _B = i ₄ .

Here, no signal is supplied to the input terminals 1 and 2, and the signal given to the input terminal 1 due to noise or the like is larger than the signal given to the input terminal 2. Therefore, the NMOS transistor M3 and the NMOS transistor M3 are provided by the differential circuit including the NMOS transistors M1 and M2.
4 has a larger current supply capability, and the current i ₄ flowing through the NMOS transistor M4 is
Higher current i ₁ flowing through the NMOS transistor M1.

Therefore, at this time, the voltage at node NB becomes lower than the voltage at node NA.

Next, it is assumed that the signal supplied to the input terminal 1 due to noise or the like is smaller than the signal supplied to the input terminal 2. At this time, the NMOS transistors M1 and NMO
In the differential circuit including the S transistor M2, NM
The OS transistor M2 turns on, and the NMOS transistor M1 turns off.

On the other hand, since the low-level offset signal is supplied to the offset input terminal 11 and the high-level offset signal is supplied to the offset input terminal 12, the differential signal comprising the NMOS transistor M3 and the NMOS transistor M4 is provided. In the circuit, the NMOS transistor M4 is on and the NMOS transistor M3 is off.

At this time, the NMOS transistor M1
The drain current i _A flowing through node NA of the connection point between the drain of the NMOS transistor M3, is a sum of the current i ₃ flowing through the current i ₁ and the NMOS transistor M3 through the NMOS transistor M1, the NMOS transistors M1 Since both the NMOS transistor M3 and the NMOS transistor M3 are off, the current at the node NA becomes i _A = 0, and no current flows through the node NA.

The current i _B flowing through the node NB at the connection point between the drain of the NMOS transistor M2 and the drain of the NMOS transistor M4 is the sum of the current i ₂ flowing through the NMOS transistor M2 and the current i ₄ flowing through the NMOS transistor M4. And the NMOS transistor M2
Since both the NMOS transistor M4 and the NMOS transistor M4 are on, i _B = i ₂ + i ₄ .

Therefore, at this time, the voltage at node NB becomes lower than the voltage at node NA.

As described above, when no serial data signal is applied to the input terminals 1 and 2,
And 2 have input terminals 11 and 12
, The voltage of the node NB is always lower than the voltage of the node NA.

Output signals SA and S of nodes NA and NB
B is supplied to the gates of the NMOS transistors M7 and M8. When the voltage of the node NB is lower than the voltage of the node NA, the NMOS transistor M7 is turned on, and NM
The OS transistor M8 turns off. Therefore, NMOS
The output of the drain of the transistor M8 becomes high level, and the signal SC always becomes high level. When the output of the drain of the NMOS transistor M8 goes high, the output of the inverting amplifier 5 goes low and the output of the output terminal 7 goes high.

As described above, when no serial data signal is supplied to the input terminals 1 and 2, the output of the output terminal 7 is constant at a high level.

Next, a case where a serial data signal is supplied to the input terminals 1 and 2 will be described.

First, it is assumed that a high-level serial data signal is supplied to the input terminal 1 and a low-level serial data signal is supplied to the input terminal 2. When a high-level serial data signal is supplied to the input terminal 1 and a low-level serial data signal is supplied to the input terminal 2, the NMOS transistor M1 in the differential circuit including the NMOS transistors M1 and M2 Turns on, and the NMOS transistor M2 turns off.

On the other hand, since a low-level offset signal is supplied to the offset input terminal 11 and a high-level offset signal is supplied to the offset input terminal 12, the differential signal comprising the NMOS transistor M3 and the NMOS transistor M4 is provided. In the circuit, the NMOS transistor M4 is on and the NMOS transistor M3 is off.

The drain of the NMOS transistor M1 and N
Current i _A flowing through node NA of the connection point between the drain of the MOS transistor M3 is the sum of the current i ₃ flowing through the current i ₁ and the NMOS transistor M3 through the NMOS transistor M1, a i _A = i ₁ + i ₃ made, but this time, the NMOS transistor M1 is turned on, the NMOS transistor M3 is turned off, the current i _a flowing through the node NA has a i _a = i _1.

The drain of the NMOS transistor M2 and N
The current i _B flowing through the node NB at the connection point with the drain of the MOS transistor M4 is the sum of the current i ₂ flowing through the NMOS transistor M2 and the current i ₄ flowing through the NMOS transistor M4, and i _B = i ₂ + i ₄ However, at this time, since the NMOS transistor M2 is off, the current i _B flowing through the node NA is i _B = i ₄ .

Here, the amplitude of the input serial data signal is larger than the amplitude of the offset voltage applied to the input terminal 11 and the input terminal 12. Therefore, NMOS
From the differential circuit composed of the transistors M3 and M4, NM
The current supply capability towards differential circuit composed of OS transistors M1 and M2 is larger, the current i ₁ flowing through the NMOS transistor M1, the NMOS transistor M4
Is larger than the current i ₄ flowing through

Therefore, at this time, the voltage at node NA becomes lower than the voltage at node NB.

Next, it is assumed that the serial data signal applied to the input terminal 1 goes low and the serial data signal applied to the input terminal 2 goes high.
A low level signal is applied to input terminal 1 and input terminal 2
Is supplied with a high-level signal, the NMOS transistor M2 is turned on and the NMOS transistor M1 is turned off in the differential circuit including the NMOS transistor M1 and the NMOS transistor M2.

On the other hand, since a low-level offset signal is supplied to the offset input terminal 11 and a high-level offset signal is supplied to the offset input terminal 12, the differential signal comprising the NMOS transistor M3 and the NMOS transistor M4 is provided. In the circuit, the NMOS transistor M4 is on and the NMOS transistor M3 is off.

At this time, the NMOS transistor M1
Current i _A flowing through the node NA at the connection point between the drain of the NMOS transistor M3 and the drain of the NMOS transistor M3 is the sum of the current i ₁ flowing through the NMOS transistor M1 and the current i ₃ flowing through the NMOS transistor M3. Since both the NMOS transistors M3 are off, the current at the node NA becomes i _A = 0, and no current flows through the node NA.

The drain of the NMOS transistor M2 and N
The current i _B flowing through the node NB at the connection point with the drain of the MOS transistor M4 is the sum of the current i ₂ flowing through the NMOS transistor M2 and the current i ₄ flowing through the NMOS transistor M4, and i _B = i ₂ + i _4. .

Therefore, at this time, the voltage at node NB becomes lower than the voltage at node NA.

As described above, when differential serial data signals are applied to input terminals 1 and 2, the relationship between the voltage at node NB and the voltage at node NA changes according to the input serial data.

Output signals SA and S of nodes NA and NB
B is supplied to the gates of the NMOS transistors M7 and M8. In the NMOS transistors M7 and M8, the output signal SA from the node NA and the output signal SB from the node NB are compared. This comparison output is output from the output terminal 7 via the inverting amplifier 5 and the inverting amplifier 6. Therefore, when a differential serial data signal is given to the input terminals 1 and 2, the output signal of the output terminal 7 becomes
It changes according to the input serial data.

As described above, in the signal detection circuit shown in FIG. 1, when a serial data signal is not supplied to the input terminals 1 and 2, the level of the output signal from the output terminal 7 becomes constant, and When a serial data signal is given to 1 and 2, the level of the output signal from the output terminal 7 changes according to the input data.

That is, as shown in FIG. 2A, the input terminal 1
And 2 are supplied with differential serial data signals, and low-level and high-level offset signals are supplied to offset input terminals 11 and 12. Note that the level of the positive-phase serial data signal supplied to the input terminal 1 is V _inp , the level of the reverse-phase serial data signal supplied to the input terminal 2 is V _inn, and the level is supplied to the offset input terminal 11. The level of the low-level offset signal is V _offn, and the level of the high-level offset signal supplied to the offset input terminal 12 is V _offp .

In this case, while the positive-phase serial data (indicated by V _inp ) supplied to the input terminal 1 is at the high level, the level of the node NA decreases, and the signals SA and The SB is as shown in FIG. 2B. The output of the inverting amplifier 5 is, as shown in FIG.
The signal is such that the logic level changes according to the input data. From the output terminal 7, this inverted signal is extracted.

The signal detection circuit shown in FIG. 1 has a CMOS configuration. Therefore, power consumption is small and cost can be reduced. In addition, high-speed operation is possible because the differential circuit is configured. Further, since it is not necessary to accumulate charges in the capacitor, a sufficiently high-speed operation is possible even with a CMOS structure having a small gm. Further, there is an advantage that the detection accuracy is high without being affected by a noise component smaller than the amplitude of the offset signal.

In the above example, the signal detection circuit is connected to the CM.
Although it is composed of an OS, it is needless to say that it can be composed of a bipolar transistor.

As described above, the signal detection circuit shown in FIG.
A differential circuit composed of S transistors M1 and M2, a differential circuit composed of NMOS transistors M3 and M4 to which an offset signal is input, a level of a connection point between a drain of the NMOS transistor M1 and a drain of the NMOS transistor M3, A differential circuit comprising NMOS transistors M7 and M8 for comparing the level of the connection point between the drain of the transistor M2 and the drain of the NMOS transistor M4 is provided. When no serial data signal is supplied, the output level becomes constant. ,
When a serial data signal is applied, an output whose level changes according to input data is obtained.

Using such a signal detection circuit, a serial data signal detection circuit that detects the presence or absence of a signal in the serial interface can be configured.

FIG. 3 shows an example of a signal detection circuit of a serial interface configured using the above-described signal detection circuit. 3, a signal detection circuit 21 is the signal detection circuit shown in FIG. This signal detection circuit 21 includes:
The signal input terminals inp and inn, the offset input terminals ofp and ofn, and the output terminal out are provided. The signal input terminal inp corresponds to the input terminal 1, the signal input terminal inn corresponds to the input terminal 2, the offset input terminal ofp corresponds to the input terminal 12, and the offset terminal o
fn corresponds to the input terminal 11. The output terminal out corresponds to the output terminal 7.

In FIG. 3, signal line 2 for serial data
The signals from 2A and 22B are supplied to the positive-phase input terminal inp and the negative-phase input terminal inn of the signal detection circuit 21. From the offset signal generating circuit 32, a high-level offset signal (V _DD + V _of / 2) and a low-level offset signal (V _DD -V _of / 2) (V _DD is the power supply voltage, V _DD
of is the amplitude _of the offset voltage). The high-level offset signal is supplied to the offset input terminal ofp of the signal detection circuit 21. The low-level offset signal is supplied to the offset input terminal ofn of the signal detection circuit 21. The output terminal out of the signal detection circuit 21 is supplied to the logic circuit 24 via the inverter 26. The logic circuit 24 determines whether or not serial data has been input from the output of the signal detection circuit 21. The logic circuit 24 determines from the output of the signal detection circuit 21 whether or not serial data is input, and outputs the determination output from the output terminal 25.

Serial data signal lines 22A and 22B
, A differential serial data signal is sent. The serial data is, for example, from 1 Gbit / sec to 4 Gbit / sec.
It is high-speed serial data of Gbit / sec. The serial data is coded by, for example, 8-10 modulation, and data in an arbitrary bit is limited in run length. That is, for example, the run length is limited so that the sequence of “1” or “0” in the transmitted serial data is, for example, within 5 bits.

The output of the signal detection circuit 21 is connected to the input terminal in.
When a signal is not supplied to p and inn, the level is constant. When a signal of differential serial data is supplied to the input terminals inp and inn, a signal that changes according to the serial data is output. The output of the signal detection circuit 21 is supplied to the logic circuit 24 via the inverter 26.

The logic circuit 24 determines, for example, once every 10 bits whether the data has been inverted. As described above, since the transmitted serial data is coded, the data is inverted once every five cycles, for example. The logic circuit 24 determines whether or not serial data has been input by determining whether or not data has been inverted during a predetermined time corresponding to, for example, five cycles. This judgment output is output from the output terminal 25.

As described above, the use of the signal detection circuit shown in FIG. 1 makes it possible to detect the presence or absence of serial data transmitted differentially.

By the way, for example, from 1 Gbit / sec to 4G
With high-speed serial data of bit / sec, it is difficult for the logic circuit 24 to directly determine whether or not data has been inverted. Therefore, as shown in FIG. 4, a frequency dividing circuit for dividing the output of the signal detecting circuit 21 may be provided. The frequency dividing circuit can be configured by a D flip-flop 27 and an inverter 28 that inverts the output of the D flip-flop 27 and feeds back the inverted signal.

In the configuration shown in FIG. 3, one signal detection circuit 21 detects the presence or absence of a serial data signal of a differential signal transmitted via the serial data signal lines 22A and 22B. ing. However, when the transmitted differential serial data signal has a DC offset, one signal detection circuit 21 may not be able to detect the signal.

That is, the levels V _inp and V _inn of the input signals of the serial data of the normal phase and the negative phase as shown in FIG.
5B, the signal level becomes eV _inp and eV _inn as shown in FIG. 5B.

As shown in FIG. 1, in the signal detection circuit 21, the current i ₁ flowing through the NMOS transistor M1 when the NMOS transistor M1 is turned on by the signal from the input terminal 1 flows through the NMOS transistor M4 by the offset signal. by greater than the current i _4, the output inversion occurs. For that purpose, the high level of the serial data of the positive phase needs to be higher than the high level of the offset signal.

When the DC fluctuation as shown in FIG. 5B occurs, as shown in FIG. 5C, the positive-phase serial data eV
The high level of _inp is the high level V _{ofp of the} offset signal.
It goes down more. Δ indicates a DC fluctuation. Therefore, one signal detection circuit 21 cannot detect serial data.

Therefore, as shown in FIG. 6, two signal detection circuits 21A and 21B may be provided. The signals from the serial data signal lines 22A and 22B are
The signal is supplied to the positive-phase input terminal inp and the negative-phase input terminal inn of the signal detection circuit 21A, and is also supplied to the signal detection circuit 21A.
To the input terminal inn of the negative phase of B and the input terminal inp of the positive phase
Supplied to Thus, the two signal detection circuits 21A
In 21B and 21B, the positive-phase signal and the reverse-phase signal of the serial data are reversed.

By doing so, one of the signal detection circuits 2
In FIG. 1A, due to the DC offset, as shown in FIG. 5C, even if the high level of the serial data eV _inp falls below the high level V _{ofp of the} offset signal and the serial data cannot be detected, the other signal detection circuit 21B Then, as shown in FIG. 5D, the serial data eV
The high level of _inn is the high level V _{ofp of the} offset signal.
Since it becomes larger, serial data can be detected.

In this example, in the logic circuit 24, from the outputs of the two signal detection circuits 21A and 21B,
The presence or absence of serial data is determined.

FIG. 7 shows an example of a serial data recovery circuit configured using the above-described signal detection circuit. For example, in a serial data interface with a transmission rate of 1.06 Gbps, a PLL (Phase Locked Loop) that locks the phase of the received serial data is provided to extract a clock of the received serial data. This PLL is provided with a phase comparison circuit that compares the phase of the received serial clock with the phase of a VCO (Voltage Controlled Oscillator), and charges are stored in a charge pump according to the output of the phase comparison circuit.
The output of this charge pump is applied to V through a loop filter.
The VCO is supplied to the CO, whereby the oscillation frequency of the VCO is controlled.

As described above, in the PLL for generating a clock phase-locked to the received serial data, it is necessary to set the oscillation frequency of the VCO close to the serial data rate when no signal is received. is there. Therefore, the presence or absence of serial data input is detected,
When there is input of serial data, the oscillation frequency of the VCO is controlled so as to lock the phase to the received serial data. When there is no input of serial data, the oscillation frequency of the VCO is controlled so as to lock to a predetermined reference clock. ing.

FIG. 7 shows that, as described above, when serial data is received, the oscillation frequency of the VCO is controlled so that the phase is locked to the received serial data, and when there is no input of serial data, a predetermined reference clock is used. This is an example of a serial data recovery circuit that controls the oscillation frequency of a VCO so as to lock.

In FIG. 7, transmitted serial data is supplied to an input terminal 51. The serial data is, for example, data at a rate of 1.06 Gbps. The serial data from the input terminal 51 is supplied to a phase comparison circuit 52 and also to a serial data signal detection circuit 55.

A reference clock is supplied to the input terminal 57. This reference clock is, for example, 1
It is a 06 MHz clock. The clock from the input terminal 57 is supplied to the phase frequency comparison circuit 58.

The VCO 53 has, for example, an oscillation frequency of 21.
It oscillates a 2 MHz clock. VCO53
Is supplied to a phase comparison circuit 52, and 1 /
The signal is supplied to the phase frequency comparison circuit 58 via the divide-by-2 circuit 60. The 212 MHz clock is supplied as one bit from the VCO 53 to the 分 frequency dividing circuit 60. V
From the CO 53 to the phase comparison circuit 52,
An M MHz clock is supplied in 10 bits.

The signal detection circuit 55 detects whether serial data is supplied to the input terminal 51 or not.
As the signal detection circuit 55, FIG. 3, FIG.
Can be used.

When it is detected that the serial data is supplied to the input terminal 51, the output of the signal detection circuit 55 goes high, for example. When serial data is not supplied to the input terminal 51, the signal detection circuit 55
Is at a low level, for example.

The output of the signal detection circuit 55 is supplied to the charge pump circuit 54 and also to the charge pump circuit 59 via the inverter 61. The operations of the charge pump circuit 54 and the charge pump circuit 59 are controlled according to the output of the signal detection circuit 55.

That is, when it is detected that the serial data is supplied to the input terminal 51, the signal detection circuit 5
5 becomes high level, the charge pump circuit 54 operates, and the charge pump circuit 59 stops operating. When serial data is not supplied to the input terminal 51, the output of the signal detection circuit 55 becomes, for example, low level, the charge pump circuit 59 operates, and the charge pump circuit 54 does not operate.

In such a circuit, when serial data is received, the oscillation frequency of the VCO 53 is controlled so that the phase is locked to the received serial data. When no serial data is input, the circuit is locked to a predetermined reference clock. Operates so that the oscillation frequency of the VCO 53 is controlled.

That is, when the serial data from the input terminal 51 is detected, the output of the signal detection circuit 55 controls the charge pump circuit 54 to operate and the operation of the charge pump circuit 59 to be stopped. Therefore, the phase comparison circuit 52 compares the phase of the serial data from the input terminal 51 with the output of the VCO 53, and the output of the phase comparison circuit 52 is supplied to the charge pump circuit 54. The charge pump circuit 54 is charged and discharged according to whether the phase error output from the phase comparison circuit 52 is advanced or delayed. The output of the charge pump circuit 54 is a resistor 6
1. Loop filter 56 composed of capacitors 62 and 63
Is supplied to the VCO 53 via the. Thereby, the oscillation frequency of the VCO 53 is controlled so as to lock to the phase of the input serial data.

On the other hand, when the serial data from the input terminal 51 is not detected by the signal detection circuit 55, the charge pump circuit 59 operates and the operation of the charge pump circuit 54 is stopped. Therefore, the phase frequency comparison circuit 58
Then, the phase and frequency of the reference clock from the input terminal 57 are compared with the phase and frequency of the output of the VCO 53, and the comparison output is supplied to the charge pump circuit 59. The charge pump circuit 59 is charged and discharged according to the comparison output from the phase frequency comparison circuit 58. The output of the charge pump circuit 59 is supplied to the VCO 53 via the loop filter 56. Thereby, the oscillation frequency of the VCO 53 is controlled so as to lock to the phase and frequency of the reference clock.

In this example, an interleave method is shown in which the oscillation frequency of the VCO 53 can be set lower than the data rate of the received serial data. However, other configurations may be used. The loop filter 56 may have various configurations other than the configuration including the resistor 11 and the capacitors 12 and 13.

The serial data from the input terminal 51 and V
Since the phase comparison circuit 52 that compares the phase with the output clock from the CO 53 generally does not have a frequency comparison function, the oscillation frequency of the VCO 53 is set near the serial data rate before receiving serial data. There is a need.

In this example, a reference clock generated based on, for example, a crystal oscillator is supplied to the input terminal 57,
By comparing the output of the VCO 53 with this reference clock and locking the phase frequency of the output of the VCO 53 and the reference clock, the oscillation frequency of the VCO 53 is set to a value near the serial data rate before receiving the serial data. Can be kept.

As described above, in this example, the signal detection circuit 5
5 to detect whether serial data is input,
When serial data is received, the oscillation frequency of the VCO 53 is controlled so that the phase is locked to the received serial data. When there is no input of serial data, the VCO 53 is locked so as to lock to a predetermined reference clock.
Oscillation frequency is controlled.

A serial signal detection circuit for detecting a serial data signal with such a high-speed serial interface has conventionally used a bipolar transistor, and it has been difficult to form a CMOS circuit. By using the serial signal detection circuit shown in FIG. 3, FIG. 4, or FIG. 6, a CMOS configuration can be realized.

Further, in this case, only the gate terminal of the first-stage comparator is added to the signal path, so that an ideal high-impedance connection can be made. In addition, the addition of capacitance to the signal steep road is relatively small due to the gate capacitance, and the advantage of the improvement effect of the manufacturing process can be enjoyed.

[0115]

According to the present invention, a differential circuit comprising first and second transistors to which serial data of a differential signal is inputted, and a third circuit to which an offset signal is inputted.
And a differential circuit including a fourth transistor, and a level of a connection point between a drain of the first transistor and a drain of the third transistor, and a level between a drain of the second transistor and a drain of the fourth transistor. A comparator for comparing the level of the connection point is provided. When the serial data signal is not applied, the output level is constant from the comparator, and when the serial data signal is applied, an output whose level changes according to the input data is obtained.

Such a signal detection circuit can operate at high speed, and can detect the presence or absence of a high-speed serial data signal as a CMOS configuration. Also, the determination level can be easily set by changing the amplitude of the offset signal. Furthermore, by performing the final signal detection determination using a logic circuit capable of implementing various determination algorithms, flexible determination can be performed.

[Brief description of the drawings]

FIG. 1 is a connection diagram of an example of a signal detection circuit to which the present invention is applied.

FIG. 2 is a waveform diagram used for describing an example of a signal detection circuit to which the present invention is applied.

FIG. 3 is a block diagram illustrating an example of a serial signal detection circuit to which the present invention is applied;

FIG. 4 is a block diagram of another example of the serial signal detection circuit to which the present invention is applied;

FIG. 5 is a waveform diagram used for explaining still another example of the serial signal detection circuit to which the present invention is applied.

FIG. 6 is a block diagram of still another example of the serial signal detection circuit to which the present invention is applied.

FIG. 7 is a block diagram illustrating an example of a serial data recovery circuit to which the present invention is applied;

FIG. 8 is a connection diagram of an example of a conventional signal serial signal detection circuit.

[Description of References] M1, M2... MOS transistors forming a first differential circuit, M3, M4,... MOS transistors forming a second differential circuit, M7, M8. Constituting MOS transistors

Continued on the front page F term (reference) 5J066 AA01 AA12 CA13 CA65 FA15 HA02 HA10 HA25 HA29 KA00 KA02 KA04 KA05 KA09 KA17 KA32 KA33 KA35 KA36 KA41 ND01 ND14 ND22 ND23 PD01 SA13 TA01 TA06 5J106 AA04 CC32 CC01 CC31 CC01 CC32 GG15 HH10 JJ00 KK02 KK18

Claims (16)

[Claims] 1. A first differential circuit comprising a first transistor and a second transistor whose sources or emitters are connected in common, and a first differential circuit to which a differential input signal is input; A second differential circuit comprising a third transistor and a fourth transistor connected in common, to which a differential offset signal is input; and a drain or collector of the first transistor and the third transistor A differential amplifier, wherein drains or collectors of transistors are commonly connected, and a drain or collector of the second transistor and a drain or collector of the fourth transistor are commonly connected. 2. The differential amplifier according to claim 1, wherein said transistor is constituted by a MOS transistor. 3. The differential amplifier according to claim 1, wherein the amplitude of the differential offset signal is set to a level smaller than the amplitude of the differential input signal. 4. A first differential circuit comprising a first transistor and a second transistor having their sources or emitters connected in common, and a first differential circuit to which a differential input signal is inputted; A second differential circuit including a third transistor and a fourth transistor which are connected in common, and to which a differential offset signal is input; a drain or a collector of the first transistor; A drain or a collector is commonly connected, a drain or a collector of the second transistor is commonly connected to a drain or a collector of the fourth transistor, and a drain or a collector of the first transistor is connected to a drain of the third transistor or The output of the collector connection point, the drain or collector of the second transistor and the fourth transistor A comparison circuit for comparing an output of a connection point between a drain and a collector of the transistor, wherein presence or absence of an input signal is detected from an output of the comparison circuit. 5. The signal detection circuit according to claim 4, wherein said transistor is constituted by a MOS transistor. 6. The signal detection circuit according to claim 4, wherein the amplitude of the differential offset signal is set to a level smaller than the amplitude of the input signal. 7. A differential serial data input terminal to which a differential serial data signal is input, a differential offset signal input terminal to which a differential offset signal is input, and the differential serial data signal A signal having a predetermined level when not detected, and an output terminal for outputting a signal that changes in accordance with the input differential serial data when the differential serial data signal is detected. A detection circuit for determining whether or not the serial data has been input from the output of the signal detection circuit, wherein the signal detection circuit includes a first transistor and a source or emitter commonly connected to each other; A first differential circuit including a second transistor, to which a differential input signal is input, and a third transistor, whose sources or emitters are commonly connected. A second differential circuit comprising a transistor and a fourth transistor, to which a differential offset signal is inputted; and a drain or a collector of the first transistor and a drain or a collector of the third transistor connected in common; A drain or a collector of the second transistor and a drain or a collector of the fourth transistor are commonly connected; an output of a connection point between a drain or a collector of the first transistor and a drain or a collector of the third transistor; A comparison circuit for comparing a drain or a collector of the second transistor with an output of a connection point of a drain or a collector of the fourth transistor; a gate or a base of the first transistor and the second
The differential serial data input terminal is derived from the gate or base of the third transistor, and the gate or base of the third transistor and the fourth
The differential offset signal input terminal is derived from the gate or base of the transistor of the above, and the output terminal is derived from the output of the comparison circuit. A serial data signal detection circuit, which determines whether or not a signal changes and determines whether or not a serial data signal has been input. 8. The serial data signal detection circuit according to claim 7, wherein said transistor is constituted by a MOS transistor. 9. The serial data signal detection circuit according to claim 7, wherein the amplitude of the differential offset signal is set to a level smaller than the amplitude of the differential serial data signal. 10. A frequency divider for dividing the output of the signal detection circuit, wherein the determination circuit determines whether the serial data is input from the divided output of the signal detection circuit. 8. The serial data signal detection circuit according to claim 7, wherein: 11. Two signal detection circuits are provided, one of the signal detection circuits is supplied with the serial data of the positive phase and the serial data of the opposite phase to the input terminal of the signal detection circuit, and the input terminal of the other signal detection circuit is supplied to the input terminal of the other signal detection circuit. And supplying the serial data of the normal phase, respectively.
8. The serial data signal detection circuit according to claim 7, wherein the determination circuit determines whether or not the serial data has been input from outputs of the two signal detection circuits. 12. A first PLL loop for comparing input serial data with an output of an oscillator whose frequency can be controlled, controlling the oscillator based on the comparison output, a reference clock, and an output of the oscillator. A second PLL loop that controls the oscillator based on the comparison output, a serial data signal detection circuit that detects the presence or absence of the serial data, and an output of the serial data detection circuit. 1
And a switching circuit for switching between the PLL loop and the second PLL loop. When the serial data is not input, the oscillation frequency of the oscillator is controlled by the reference clock, and when the serial data is input. In the serial data recovery circuit wherein the oscillator is controlled by the serial data, the serial data signal detection circuit includes a differential serial data input terminal to which a differential serial data signal is input, and a differential serial data input terminal. A differential offset signal input terminal to which an offset signal is input, a signal of a predetermined level is output when the differential serial data signal is not detected, and is input when the differential serial data signal is detected. And an output terminal for outputting a signal that changes according to the differential serial data. A signal detection circuit for determining whether or not the serial data has been input from an output of the signal detection circuit, wherein the signal detection circuit has a first source or an emitter commonly connected to each other. A first differential circuit comprising a transistor and a second transistor, to which a differential input signal is inputted; and a third transistor and a fourth transistor having their sources or emitters connected in common. A second differential circuit to which the offset signal is input, a drain or a collector of the first transistor and a drain or a collector of the third transistor are commonly connected, and a drain or a collector of the second transistor and the The drain or the collector of the fourth transistor is commonly connected, and the drain or the collector of the first transistor is connected to the upper side. A comparison circuit for comparing an output at a connection point of a drain or a collector of a third transistor and an output of a connection point between a drain or a collector of the second transistor and a drain or a collector of the fourth transistor; The gate or base of the first transistor and the second
The differential serial data input terminal is derived from the gate or base of the third transistor, and the gate or base of the third transistor and the fourth
The differential offset signal input terminal is derived from the gate or base of the transistor of the above, and the output terminal is derived from the output of the comparison circuit. A serial data recovery circuit, which determines whether a signal changes or not and determines whether a serial data signal is input. 13. The serial data recovery circuit according to claim 12, wherein said transistor comprises a MOS transistor. 14. The amplitude of the differential offset signal is
13. The serial data recovery circuit according to claim 12, wherein the level is smaller than the amplitude of the differential serial data signal. 15. A frequency dividing circuit for dividing the output of the signal detecting circuit, the frequency dividing of the output of the signal detecting circuit, and the judging circuit producing the divided output of the signal detecting circuit. 13. The serial data recovery circuit according to claim 12, wherein it is determined whether or not said serial data has been input from said device. 16. Two signal detection circuits are provided, one of the signal detection circuits is supplied with the serial data of the positive phase and the serial data of the opposite phase to the input terminal thereof, and the other input terminal of the signal detection circuit is supplied with the negative phase. And supplying the serial data of the normal phase, respectively.
13. The serial data recovery circuit according to claim 12, wherein the determination circuit determines whether or not the serial data has been input from outputs of the two signal detection circuits.