JPH05251949A - Optical receiver circuit - Google Patents
Optical receiver circuitInfo
- Publication number
- JPH05251949A JPH05251949A JP4046960A JP4696092A JPH05251949A JP H05251949 A JPH05251949 A JP H05251949A JP 4046960 A JP4046960 A JP 4046960A JP 4696092 A JP4696092 A JP 4696092A JP H05251949 A JPH05251949 A JP H05251949A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transistor
- light receiving
- call
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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- Amplifiers (AREA)
- Optical Communication System (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は光受信回路に関し、特に
受光素子からの信号を増幅前置増幅回路を備えた光受信
回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical receiver circuit, and more particularly to an optical receiver circuit equipped with a preamplifier circuit for amplifying a signal from a light receiving element.
【０００２】[0002]
【従来の技術】図２は従来のこの種の光受信回路の一例
を示す図である。この光受信回路は受光素子７が受光し
た信号を抵抗器１０を帰還抵抗とするトランスインピー
ダンス型前置増幅器で電流電圧変換し、次段の回路、例
えば等化増幅回路１３や識別再生回路１４に接続され、
通信時、無通信時にかかわらず全回路に電源が常時給電
されている。なお１と４はとトランジスタ、８は整流器
である。2. Description of the Related Art FIG. 2 is a diagram showing an example of a conventional optical receiving circuit of this type. In this optical receiving circuit, a signal received by the light receiving element 7 is converted into a current-voltage by a transimpedance type preamplifier using a resistor 10 as a feedback resistor, and then converted into a circuit in the next stage, for example, the equalizing amplifier circuit 13 or the discrimination reproducing circuit 14. Connected,
Power is constantly supplied to all circuits regardless of communication or non-communication. In addition, 1 and 4 are transistors, and 8 is a rectifier.
【０００３】[0003]
【発明が解決しようとする課題】従来この光受信回路で
は、前置増幅回路以降の回路も常時給電された状態であ
り非通信時における消費電力が大きいという欠点があっ
た。Conventionally, this optical receiver circuit has a drawback in that the circuits after the preamplifier circuit are always supplied with power and the power consumption during non-communication is large.
【０００４】本発明は、非通信時には前置増幅回路以降
の回路の電源を遮断し、有通信時のみ次段の回路に電源
を供給する事が可能なコールバイコール給電制御回路付
の光受信回路を提供する事にある。The present invention is an optical receiver circuit with a call-by-call power supply control circuit capable of cutting off the power supply of the circuits after the preamplifier circuit during non-communication and supplying power to the circuit of the next stage only during communication. To provide.
【０００５】[0005]
【課題を解決するための手段】本発明の光受信回路は、
光受光素子とトランスインピーダンス型前置増幅回路で
構成される光受信回路において、常時給電された前置増
幅回路のフロントエンドトランジスタのエミッタにカレ
ントミラー回路を付加し、ミラー側に接続された抵抗器
に流れる電流が光入力信号の有無によって変化するのを
検値してコールバイコール給電電源を制御することを特
徴とする。The optical receiving circuit of the present invention comprises:
In a light receiving circuit composed of a light receiving element and a transimpedance type preamplifier circuit, a resistor connected to the mirror side by adding a current mirror circuit to the emitter of the front-end transistor of the preamplifier circuit that is constantly fed. It is characterized in that the call-by-call power supply is controlled by detecting that the current flowing through the circuit changes depending on the presence or absence of an optical input signal.
【０００６】さらに本発明の光受信回路は、より詳しく
表わせば、受光素子とトランスインピーダンス型前置増
幅回路を有する光受信回路において、前記トランスイン
ピーダンス型前置増幅回路のフロントエンドであるトラ
ンジスタ１のエミッタにトランジスタ２のコレクタ及び
ベース、更にトランジスタ３のベースが接続され、前記
トランジスタ２及びトランジスタ３のエミッタはそれぞ
れ地気に接続され、前記トランジスタ３のコレクタは抵
抗器５を介して電源Ｖccに接続され、さらに前記トラン
ジスタ３のコレクタは基準電圧を片端入力とする比較器
６の別入力端子に接続されることを特徴とする。More specifically, the optical receiving circuit of the present invention is, in more detail, an optical receiving circuit having a light receiving element and a transimpedance type preamplifier circuit. The collector and the base of the transistor 2 and the base of the transistor 3 are connected to the emitter, the emitters of the transistor 2 and the transistor 3 are respectively connected to the ground, and the collector of the transistor 3 is connected to the power source V cc via the resistor 5. Further, the collector of the transistor 3 is connected to another input terminal of the comparator 6 which inputs the reference voltage at one end.
【０００７】[0007]
【実施例】図１は本発明の一施例の構成を示す回路図で
ある。この回路では光信号を電気信号に変換する受光素
子７と、この受光素子７のアノードにフロトンエンドで
あるトランジスタ１のベースが接続され、このトランジ
スタ１のコレクタは抵抗器９を介して電源Ｖccに接続さ
れると共にトランジスタ４のベースに接続され、トラン
ジスタ４のコレクタは電源Ｖccに接続され、またトラン
ジスタ４のエミッタはレベルシフト用ダイオード８を介
して抵抗器１１の片端に接続され、この抵抗器１１のも
う一方の端子は地気に接続される。前記レベルシフト用
ダイオード８のカソードは抵抗器１０を介して前記トラ
ンジスタ１のベースに接続され、前記トランジスタ１の
エミッタはトランジスタ２のベースとコレクタさらにト
ランジスタ３のベースにそれぞれ接続され、前記トラン
ジスタ２及びトランジスタ３のエミッタはそれぞれ地気
に接続され、前記トランジスタ３のコレクタは、抵抗器
５を介して電源Ｖccに接続されるとともに、片端に基準
電圧源１３が接続された比較器６のもう一端の入力に接
続される。さらに前記比較器６の出力は電源をＯＮ・Ｏ
ＦＦできるコールバイコール給電制御回路１２に接続さ
れ、このコールバイコール給電制御回路１２の電源出力
は等化増幅回路１３及び識別再生回路１４の電源に接続
されており、前記等化増幅回路１３の入力は前記レベル
シフト用ダイオード８のカソードに接続され、前記等化
増幅回路１３の出力は識別再生回路１４の入力に接続さ
れる。1 is a circuit diagram showing the configuration of an embodiment of the present invention. In this circuit, a light receiving element 7 for converting an optical signal into an electric signal and a base of a transistor 1 which is a Freton end are connected to an anode of the light receiving element 7, and the collector of the transistor 1 is connected to a power source V cc via a resistor 9. Are connected to the base of the transistor 4, the collector of the transistor 4 is connected to the power supply V cc, and the emitter of the transistor 4 is connected to one end of the resistor 11 via the level shifting diode 8. The other terminal of 11 is connected to the earth. The cathode of the level shifting diode 8 is connected to the base of the transistor 1 via a resistor 10, and the emitter of the transistor 1 is connected to the base and collector of the transistor 2 and the base of the transistor 3, respectively. The emitters of the transistors 3 are respectively connected to the ground, and the collectors of the transistors 3 are connected to the power supply V cc via the resistor 5 and the other end of the comparator 6 to which the reference voltage source 13 is connected at one end. Connected to the input of. Further, the output of the comparator 6 is the power ON / O.
It is connected to a call-by-call power supply control circuit 12 capable of FF, and the power output of the call-by-call power supply control circuit 12 is connected to the power supplies of the equalization amplification circuit 13 and the identification reproduction circuit 14, and the input of the equalization amplification circuit 13 is It is connected to the cathode of the level shift diode 8, and the output of the equalizing and amplifying circuit 13 is connected to the input of the discrimination and reproducing circuit 14.
【０００８】上記のような光受信回路の構成において、
光信号が受光素子７に入力されると、その出力電流はト
ランジスタ１によって増幅され、コレクタ電流Ｉが抵抗
器９に流れ、同様にトランジスタ２にも流れる。又トラ
ンジスタ２とトランジスタ３はカレントミラー回路構成
となっているため、先に抵抗器９に流れる電流Ｉと同じ
電流がトランジスタ３及び抵抗器５にも流れ、トランジ
スタ３のコレクタのＡ点の電圧Ｖは、抵抗器５の抵抗値
をＲ5 とすると、下記の数式１の様になる。In the structure of the optical receiving circuit as described above,
When an optical signal is input to the light receiving element 7, its output current is amplified by the transistor 1 and the collector current I flows through the resistor 9 and also through the transistor 2. Further, since the transistors 2 and 3 have a current mirror circuit configuration, the same current as the current I that first flows through the resistor 9 also flows through the transistor 3 and the resistor 5, and the voltage V at the point A of the collector of the transistor 3 is generated. When the resistance value of the resistor 5 is R 5 , the following equation 1 is obtained.
【０００９】[0009]
【数１】Ｖ＝Ｖcc−Ｒ5 ×Ｉ この数式１から分かるように、受光素子７に光信号が入
力されているときは、Ａ点の電圧Ｖは低くなる。一方光
信号が入力されない無信号状態の時は、電流は受光素子
７には流れないが、抵抗器１０からフィードバックされ
た電圧により微少な電流Ｉ′がトランジスタ２に流れ
る。従って数式１から分かるように、トランジスタ３の
コレクタのＡ点の電圧Ｖ′は電圧Ｖよりは相当大きくな
る。[Number 1] V = V cc -R 5 × I As can be seen from the equation 1, when the optical signal to the light receiving element 7 is input, the voltage V at the point A becomes lower. On the other hand, in the non-signal state where no optical signal is input, no current flows through the light receiving element 7, but a minute current I ′ flows through the transistor 2 due to the voltage fed back from the resistor 10. Therefore, as can be seen from Equation 1, the voltage V ′ at the point A of the collector of the transistor 3 becomes considerably larger than the voltage V.
【００１０】図３は上記の２つの場合を説明する図であ
って、横軸は光入射パワーを、縦軸はＡ点の電圧を示し
ている。電圧ＶとＶ′の中間の電圧Ｖthは本発明に於い
ては比較器６の一方の基準電圧として使用する。FIG. 3 is a diagram for explaining the above two cases, in which the horizontal axis represents the light incident power and the vertical axis represents the voltage at point A. The voltage Vth intermediate between the voltages V and V'is used as one reference voltage of the comparator 6 in the present invention.
【００１１】次にコールバイコール給電制御回路１２の
出力端Ｂに於ける出力電圧について説明する。この制御
回路１２は図示してない内部スイッチを有していて、こ
のスイッチを制御的に開閉して電源電圧Ｖccを出力する
もので、その主力点をＢ点としている。光信号が受光素
子７に当ると、すなわち通信が始まると、Ａ点の電圧Ｖ
はＶthより小さくなるので、比較器６の出力により、Ｂ
点の出力電圧はＶccとなる。従って前述した等化増幅回
路１３及び識別回路１４に電源が供給される。一方通信
が断となると、電圧Ｖ′はＶthより大となり、比較器６
の出力により、コールバイコール給電制御回路１２の点
Ｂには出力せず、従って前述した等化増幅回路１３及び
識別再生回路１４には電源は供給されない。Next, the output voltage at the output terminal B of the call-by-call power supply control circuit 12 will be described. The control circuit 12 has an internal switch (not shown), which controls and opens / closes the switch to output the power supply voltage Vcc , and its main point is the point B. When the optical signal hits the light receiving element 7, that is, when communication is started, the voltage V at the point A
Is smaller than V th, the output of the comparator 6 causes B
The output voltage at the point is Vcc . Therefore, power is supplied to the equalizing amplifier circuit 13 and the identifying circuit 14 described above. On the other hand, when the communication is cut off, the voltage V ′ becomes higher than V th , and the comparator 6
Therefore, the power is not output to the point B of the call-by-call power supply control circuit 12, so that the equalization amplification circuit 13 and the identification reproduction circuit 14 are not supplied with power.
【００１２】図４は上記のＡ点の電圧とＢ点の電圧の関
係を示したもので、Ａ点の電圧Ｖが基準電圧Ｖccより低
いとＢ点に電源電圧Ｖccが生じ、電圧Ｖ′が基準電圧よ
り高いとＢ点に出力が生じないことを示す。FIG. 4 shows the relationship between the voltage at the point A and the voltage at the point B. When the voltage V at the point A is lower than the reference voltage V cc , the power supply voltage V cc is generated at the point B and the voltage V If 'is higher than the reference voltage, no output is generated at the point B.
【００１３】以上の説明かを纏めると、光信号入力があ
る時は前置増幅回路より次段の回路にも電源を供給し、
光信号入力が無い場合は前置増幅回路以降の回路には電
源を供給しない。To summarize the above description, when there is an optical signal input, power is supplied to the next stage circuit from the preamplifier circuit,
When there is no optical signal input, power is not supplied to the circuits after the preamplifier circuit.
【００１４】[0014]
【発明の効果】以上説明した様に本発明は光信号が入力
した時すなわち通信時には前置増幅回路を含む全回路を
給電することができ、光信号が無入力すなわち無通信時
には前置増幅回路のみ常時給電を保持し、前置増幅回路
以降の回路の電源を遮断しこれにより非通信時の消費電
力を低減できるという効果がある。As described above, according to the present invention, all the circuits including the preamplifier circuit can be fed when an optical signal is input, that is, during communication, and the preamplifier circuit can be supplied when no optical signal is input, that is, during no communication. Only in this case, the power supply is always maintained, and the power supply to the circuits after the preamplifier circuit is cut off, whereby the power consumption during non-communication can be reduced.
【図１】本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.
【図２】従来の装置の回路図である。FIG. 2 is a circuit diagram of a conventional device.
【図３】図１に示した実施例の光入射パワーとＡ点の電
圧の関係を示す図である。3 is a diagram showing the relationship between the light incident power and the voltage at point A in the embodiment shown in FIG.
【図４】図１に示した実施例のＡ点と電圧とＢ点の電圧
の関係を示す図である。FIG. 4 is a diagram showing the relationship between the voltage at point A and the voltage at point B in the embodiment shown in FIG.
１，２，３，４ トランジスタ ５ 抵抗器 ６ 比較器 ７ 受光素子 ８ レベルシフト用ダイオード ９，１０，１１ 抵抗器 １２ コールバイコール給電制御回路 1, 2, 3, 4 Transistor 5 Resistor 6 Comparator 7 Light receiving element 8 Level shift diode 9, 10, 11 Resistor 12 Call-by-call power supply control circuit
───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴木 哲也 東京都港区三田一丁目４番28号 日本電気 トランスミッションエンジニアリング株式 会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuya Suzuki 1-42 Mita, Minato-ku, Tokyo NEC Transmission Engineering Co., Ltd.
Claims (2)
前置増幅回路で構成される光受信回路において、常時給
電された前置増幅回路のフロントエンドトランジスタの
エミッタにカレントミラー回路を付加し、ミラー側に接
続された抵抗器に流れる電流が光入力信号の有無によっ
て変化するのを検値してコールバイコール給電電源を制
御することを特徴とする光受信回路。1. In a light receiving circuit composed of a light receiving element and a transimpedance type preamplifier circuit, a current mirror circuit is added to the emitter of a front-end transistor of the preamplifier circuit, which is constantly fed, and a current mirror circuit is added to the mirror side. An optical receiving circuit which controls a call-by-call power supply by detecting a change in current flowing through a connected resistor depending on the presence or absence of an optical input signal.
置増幅回路を有する光受信回路において、前記トランス
インピーダンス型前置増幅回路のフロントエンドである
トランジスタ１のエミッタにトランジスタ２のコレクタ
及びベース、更にトランジスタ３のベースが接続され、
前記トランジスタ２及びトランジスタ３のエミッタはそ
れぞれ地気に接続され、前記トランジスタ３のコレクタ
は、抵抗器５を介して電源Ｖccに接続されると共に、基
準電圧を片端入力とする比較器６の別入力端子に接続さ
れる構成を特徴とする光受信回路。2. In a light receiving circuit having a light receiving element and a transimpedance type preamplifier circuit, a collector and a base of a transistor 2, a collector and a base of a transistor 2, which is a front end of the transimpedance type preamplifier circuit, and a transistor 3 are provided. The base of is connected,
The emitters of the transistor 2 and the transistor 3 are respectively connected to the ground, the collector of the transistor 3 is connected to the power source V cc via the resistor 5, and the other of the comparator 6 having the reference voltage as one end input. An optical receiver circuit characterized by being connected to an input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4046960A JPH05251949A (en) | 1992-03-04 | 1992-03-04 | Optical receiver circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4046960A JPH05251949A (en) | 1992-03-04 | 1992-03-04 | Optical receiver circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05251949A true JPH05251949A (en) | 1993-09-28 |
Family
ID=12761853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4046960A Withdrawn JPH05251949A (en) | 1992-03-04 | 1992-03-04 | Optical receiver circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05251949A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08191273A (en) * | 1995-01-10 | 1996-07-23 | Hitachi Ltd | Subscriber's optical line terminal equipment and its feeding method |
| JP2009527951A (en) * | 2006-02-17 | 2009-07-30 | スタンダード マイクロシステムズ コーポレーション | Transmission network with optical receiver using two power supply pins and one status pin to reduce power consumption, reduce manufacturing cost and increase transmission efficiency |
| US8103174B2 (en) | 2006-06-02 | 2012-01-24 | Standard Microsystems Corporation | Transmission network having an optical receiver that utilizes dual power pins and a single status pin to lower power consumption, lower manufacturing cost, and increase transmission efficiency |
-
1992
- 1992-03-04 JP JP4046960A patent/JPH05251949A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08191273A (en) * | 1995-01-10 | 1996-07-23 | Hitachi Ltd | Subscriber's optical line terminal equipment and its feeding method |
| JP2009527951A (en) * | 2006-02-17 | 2009-07-30 | スタンダード マイクロシステムズ コーポレーション | Transmission network with optical receiver using two power supply pins and one status pin to reduce power consumption, reduce manufacturing cost and increase transmission efficiency |
| JP2011217412A (en) * | 2006-02-17 | 2011-10-27 | Standard Microsystems Corp | Transmission network having optical receiver that utilizes dual power pins and one single status pin to lower power consumption, lower manufacturing cost, and increase transmission efficiency |
| JP2012085359A (en) * | 2006-02-17 | 2012-04-26 | Standard Microsystems Corp | Transmission network having optical receiver using two power supply pins and one status pin for reducing power consumption and manufacturing cost and increasing transmission efficiency |
| US8103174B2 (en) | 2006-06-02 | 2012-01-24 | Standard Microsystems Corporation | Transmission network having an optical receiver that utilizes dual power pins and a single status pin to lower power consumption, lower manufacturing cost, and increase transmission efficiency |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990518 |