JPH05251556A - Semiconductor chip - Google Patents

Semiconductor chip

Info

Publication number
JPH05251556A
JPH05251556A JP17141692A JP17141692A JPH05251556A JP H05251556 A JPH05251556 A JP H05251556A JP 17141692 A JP17141692 A JP 17141692A JP 17141692 A JP17141692 A JP 17141692A JP H05251556 A JPH05251556 A JP H05251556A
Authority
JP
Japan
Prior art keywords
recognition
semiconductor chip
dicing
recognition area
recognition mark
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17141692A
Other languages
Japanese (ja)
Other versions
JP3217459B2 (en
Inventor
Hideki Sawada
秀喜 澤田
Hiromi Ogata
弘美 緒方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP17141692A priority Critical patent/JP3217459B2/en
Priority to US08/081,392 priority patent/US5430325A/en
Publication of JPH05251556A publication Critical patent/JPH05251556A/en
Application granted granted Critical
Publication of JP3217459B2 publication Critical patent/JP3217459B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448Located on chip prior to dicing and remaining on chip after dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Dicing (AREA)

Abstract

PURPOSE:To prevent a recognition error caused by flaking of a film during a semiconductor-chip dicing step. CONSTITUTION:In a semiconductor chip 10, a dummy pattern 6 is provided between a dicing line 3 and a recognition area 2 including a recognition mark 1 and located near to the dicing line 3 so that the flaking of a film can be prevented during a dicing step. Consequently, the flaking of the film is prevented even when the film partly flakes during the dicing step, and thereby the recognition area can be protected from the flaking.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、自動機によりダイボン
ディングやワイヤボンディングする半導体チップに関
し、詳細には半導体チップ上に設定されている認識マー
クを含む認識エリアと膜剥がれから保護するためのダミ
ーパターンを形成した半導体チップに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip which is die-bonded or wire-bonded by an automatic machine, and more specifically, a recognition area including a recognition mark set on the semiconductor chip and a dummy for protecting the film from peeling. The present invention relates to a patterned semiconductor chip.

【0002】[0002]

【従来の技術】例えばファクシミリ、プリンタ等に搭載
されるLEDヘッドでは、その製造工程でLEDチップ
とICとを自動機によりワイヤボンディングするが、そ
の際に自動機はLEDチップ上に設けられている認識マ
ークと認識エリアが持つ情報に基づいてワイヤボンディ
ングを行うようになっている。
2. Description of the Related Art In an LED head mounted on, for example, a facsimile or a printer, an LED machine and an IC are wire-bonded by an automatic machine in the manufacturing process. At that time, the automatic machine is provided on the LED chip. Wire bonding is performed based on the information of the recognition mark and the recognition area.

【0003】これを図4についてもう少し詳しく説明す
る。一般に、ダイボンディングやワイヤボンディングを
行うLEDチップ等の半導体チップ10には、ダイシン
グライン3が周囲に引かれ、このライン3に沿ってダイ
シングにより個々のチップに分離され、分離された半導
体チップ10が、更にその後の工程において自動機によ
って、基板上にダイボンディングされたり、IC等にワ
イヤボンディングされる。このダイボンディングやワイ
ヤボンディング時の基準として利用されるのが、認識マ
ーク1とその周囲の認識エリア2である。自動機は認識
マーク1と認識エリア2との2値化による情報を認識し
て、所定位置でダイボンディングやワイヤボンディング
を行う。
This will be described in more detail with reference to FIG. In general, a dicing line 3 is drawn around a semiconductor chip 10 such as an LED chip that is die-bonded or wire-bonded, and individual semiconductor chips 10 are separated along the line 3 by dicing. Further, in the subsequent process, it is die-bonded on a substrate or wire-bonded to an IC or the like by an automatic machine. The recognition mark 1 and the recognition area 2 around the recognition mark 1 are used as a reference at the time of die bonding or wire bonding. The automatic machine recognizes information obtained by binarizing the recognition mark 1 and the recognition area 2 and performs die bonding or wire bonding at a predetermined position.

【0004】[0004]

【発明が解決しようとする課題】図4から分かるよう
に、認識マーク1は半導体チップ10の1隅のダイシン
グライン3付近に設定されるのが通常であり、当然なが
ら認識マーク1を含む認識エリア2もダイシングライン
3付近に存在する。ところが、ダイシング時に切断され
た端縁4(特にチップ10の角)から、半導体チップ1
0の膜が剥離することがある。この膜剥がれが認識エリ
ア2まで及ばない場合は特に問題はないが、図示のよう
に膜剥がれ(図中の斜線領域)5が認識エリア2まで達
すると、自動機の認識エラーの発生が多くなる。特に膜
剥がれ5が認識マーク1にまで至ると、認識エラーにな
る確率が一気に高まる。これは、膜剥がれ5により、認
識マーク1や認識エリア2の表面状態が正常時とは異な
り、認識マーク1と認識エリア2が本来持つ情報が変化
するため、認識エラーが発生するものと考えられてい
る。
As can be seen from FIG. 4, the recognition mark 1 is usually set in the vicinity of the dicing line 3 at one corner of the semiconductor chip 10. Of course, the recognition area including the recognition mark 1 is recognized. 2 also exists near the dicing line 3. However, from the edge 4 (particularly the corner of the chip 10) cut during dicing, the semiconductor chip 1
The film of 0 may peel off. When the film peeling does not reach the recognition area 2, there is no particular problem, but when the film peeling (hatched area in the figure) 5 reaches the recognition area 2 as shown in the figure, the recognition error of the automatic machine increases. .. In particular, when the film peeling 5 reaches the recognition mark 1, the probability of a recognition error is suddenly increased. It is considered that the film peeling 5 causes a recognition error because the surface state of the recognition mark 1 and the recognition area 2 is different from the normal state and the information originally possessed by the recognition mark 1 and the recognition area 2 is changed. ing.

【0005】従って、本発明の目的は、半導体チップの
ダイシング時に発生する膜剥がれに起因する認識エラー
を低減することにある。
Therefore, an object of the present invention is to reduce recognition errors caused by film peeling that occurs during dicing of semiconductor chips.

【0006】[0006]

【課題を解決するための手段】前記目的は、本発明の半
導体チップ、即ちダイシングライン付近に設定された認
識マークを含む認識エリアと、ダイシングラインとの間
に、ダイシング時に生ずる膜剥がれが認識エリアまで進
行するのを阻止するためのダミーパターンを形成した半
導体チップにより達成する。
Means for Solving the Problems The above-mentioned object is the semiconductor chip of the present invention, that is, a recognition area including a recognition mark set in the vicinity of a dicing line, and a film peeling occurring during dicing between the dicing line and the recognition area. This is achieved by a semiconductor chip on which a dummy pattern for preventing the progress to the above is formed.

【0007】本発明の半導体チップでは、ダミーパター
ンが膜剥がれの認識エリアへの進入を阻止する作用を有
するため、たとえダイシング時にチップ端縁から膜が剥
離しても、膜剥がれはダミーパターンまでであり、ダミ
ーパターンの内側に設定されている認識マークを含む認
識エリアには膜剥がれは生じず、膜剥がれに因る認識エ
ラーが激減する。
In the semiconductor chip of the present invention, since the dummy pattern has a function of preventing the film peeling from entering the recognition area, even if the film peels from the edge of the chip during dicing, the film peeling is limited to the dummy pattern. Therefore, film peeling does not occur in the recognition area including the recognition mark set inside the dummy pattern, and the recognition error due to film peeling is drastically reduced.

【0008】なお、ダミーパターンは、ダイシングに因
る膜剥がれを阻止できれば、その素材や形状に制限はな
く、素材としてはパターン形成のし易さなどからアルミ
ニウムが最適である。又、パターン形状は、認識エリア
まで膜剥がれが及ぶのを阻止できるものであればよく、
その幅・長さに制約はない。
The dummy pattern is not limited in its material and shape as long as it can prevent film peeling due to dicing, and aluminum is the most suitable material as it is easy to form a pattern. Further, the pattern shape may be one that can prevent the film peeling from reaching the recognition area,
There are no restrictions on its width and length.

【0009】[0009]

【実施例】以下、本発明の半導体チップを実施例に基づ
いて説明する。図1はその一例の一部平面図を示す。但
し、従来と同じ構成要素には同一符号を付してある。図
に示す半導体チップ10は、予め設定したダイシングラ
イン3に沿ってダイシングにより分離されたものであ
り、切断によりチップ10の周囲に端縁4が形成され
る。この半導体チップ10の1隅において、ダイシング
ライン3の付近には所定の認識マーク1と認識エリア2
が設定されている。
EXAMPLES A semiconductor chip of the present invention will be described below based on examples. FIG. 1 shows a partial plan view of an example thereof. However, the same components as in the related art are designated by the same reference numerals. The semiconductor chip 10 shown in the figure is separated by dicing along a preset dicing line 3, and an edge 4 is formed around the chip 10 by cutting. A predetermined recognition mark 1 and a recognition area 2 are provided in the vicinity of the dicing line 3 at one corner of the semiconductor chip 10.
Is set.

【0010】本発明の特徴であるダミーパターン6は、
アルミニウムからなり、認識エリア2とダイシングライ
ン3との間に位置し、ダイシングライン3に沿って一定
幅で延在する。特に、認識エリア2のダイシングライン
3寄りの2辺はダミーパターン6の縁に一致しており、
ダミーパターン6の縁が認識エリア2の境界線を構成し
ている。この実施例では、ダミーパターン6は半導体チ
ップ10の周囲にダイシングライン3に沿って設けられ
ているが、必ずしも周囲に設ける必要はなく、要するに
前述したように認識エリア2に膜剥がれが及ばなければ
よい。
The dummy pattern 6, which is a feature of the present invention, is
It is made of aluminum, is located between the recognition area 2 and the dicing line 3, and extends along the dicing line 3 with a constant width. In particular, the two sides of the recognition area 2 near the dicing line 3 coincide with the edges of the dummy pattern 6,
The edge of the dummy pattern 6 constitutes the boundary line of the recognition area 2. In this embodiment, the dummy pattern 6 is provided around the semiconductor chip 10 along the dicing line 3, but it is not always required to be provided around the semiconductor chip 10 as long as the film peeling does not reach the recognition area 2 as described above. Good.

【0011】このような半導体チップ10では、ダイシ
ング時に端縁4から膜が剥離しても、その進行がダミー
パターン6で食い止められ、ダミーパターン6の内側に
存在する認識マーク1は勿論のこと、認識エリア2には
膜剥がれが発生しない。従って、認識マーク1及び認識
エリア2の情報が変化しないので、自動機によるダイボ
ンディングやワイヤボンディング時に、認識エラーが起
こる可能性は極めて低い。
In such a semiconductor chip 10, even if the film is peeled from the edge 4 during dicing, the progress is stopped by the dummy pattern 6, and the recognition mark 1 existing inside the dummy pattern 6 is of course, No film peeling occurs in the recognition area 2. Therefore, since the information of the recognition mark 1 and the recognition area 2 does not change, it is extremely unlikely that a recognition error will occur during die bonding or wire bonding by an automatic machine.

【0012】図2は、本発明の他の実施例を示すLED
チップの一部平面図であり、図2の(a)は、LEDチ
ップ10の一方端のパターンを、図2の(b)はLED
チップ10の他方端のパターンを示している。図2にお
いて、7は、マスクアライメントであり、8は各LED
のワイヤボンディング用のパッドである。また、この実
施例LEDチップ10の偶角10aには、ダイシングラ
イン3に沿ってL字状のパターン6aが形成されてお
り、このL字状のパターン6aは、図1のダミーパター
ン6と同機能を持つものである。さらに、このL字状パ
ターン6aの内側に認識マーク1aが形成されている。
LED10の同端辺10c上にある他の偶角10bに
も、同様にL字状パターン6bと認識マーク1bが形成
されている。
FIG. 2 is an LED showing another embodiment of the present invention.
2A is a partial plan view of the chip, FIG. 2A shows a pattern of one end of the LED chip 10, and FIG.
The pattern of the other end of the chip 10 is shown. In FIG. 2, 7 is a mask alignment, and 8 is each LED.
Pad for wire bonding. Further, an L-shaped pattern 6a is formed along the dicing line 3 on the even corner 10a of the LED chip 10 of this embodiment, and the L-shaped pattern 6a is the same as the dummy pattern 6 of FIG. It has a function. Further, the recognition mark 1a is formed inside the L-shaped pattern 6a.
The L-shaped pattern 6b and the recognition mark 1b are similarly formed on the other even corners 10b on the same end side 10c of the LED 10.

【0013】もっとも、偶角10aに形成されるL字状
パターン6aと認識マーク7aと、他偶角10bに形成
されるL字状パターン6bと認識マーク7bは、それぞ
れL字状パターンの2辺の長さの比と、2辺から認識マ
ークまでの距離比を異なるように設定している。これら
により、例えば認識マークを認識して、その後連続的に
ワイヤボンディングを行う際に、LEDチップ10の、
いずれの端から行うかを、十分に識別でき、パッドに正
確にワイヤボンディングできるようにしている。
However, the L-shaped pattern 6a and the recognition mark 7a formed on the even corner 10a, and the L-shaped pattern 6b and the recognition mark 7b formed on the other even corner 10b respectively have two sides of the L-shaped pattern. The length ratio and the distance ratio from the two sides to the recognition mark are set to be different. With these, for example, when recognizing the recognition mark and subsequently performing wire bonding continuously,
It is possible to sufficiently discriminate which end the wire is to be attached, and to accurately wire bond the pad.

【0014】図3は、図2で示したLEDチップ10の
L字状パターンと認識マークの異なる態様のパターン例
を示している。図3の(a)は、L字状パターン6a、
6bの2辺の長さ比、及びL字状パターン6a、6bと
認識マーク1a、1bの距離は同じであるが、認識マー
ク6aと6bが長方形であり、その姿勢を横型と縦型に
している。
FIG. 3 shows a pattern example in which the L-shaped pattern of the LED chip 10 shown in FIG. 2 and the recognition mark are different. FIG. 3A shows an L-shaped pattern 6a,
The length ratio of the two sides of 6b and the distance between the L-shaped patterns 6a, 6b and the recognition marks 1a, 1b are the same, but the recognition marks 6a and 6b are rectangular, and their postures are horizontal and vertical. There is.

【0015】図3の(b)は、認識マーク1aと1bの
姿勢を異ならせるとともに、各L字状パターン6a、6
bへの距離も異なるものとしている。また、図3の
(c)は、認識マーク1a、1bの姿勢は同じである
が、L字状パターン6a、6bへの距離を異なるものと
している。いずれの場合も、自動機でワイヤボンディン
グ等を行う場合に、LEDチップ10の、いずれの端部
から行うか、この相違を読取ることにより、方向性を識
別できるようにしている。
In FIG. 3B, the postures of the recognition marks 1a and 1b are made different, and the L-shaped patterns 6a and 6 are formed.
The distance to b is also different. Further, in FIG. 3C, the recognition marks 1a and 1b have the same attitude, but the distances to the L-shaped patterns 6a and 6b are different. In either case, when wire bonding or the like is performed by an automatic machine, the directionality can be identified by reading from which end of the LED chip 10 the difference is read.

【0016】[0016]

【発明の効果】以上説明したように、請求項1記載の発
明の半導体チップは、膜剥がれ阻止用のダミーパターン
を有するため、下記の効果を奏する。 (1)ダイシング時に起こる膜剥がれが認識マークを含
む認識エリアまではダミーパターンによって進行しない
ので、認識マーク及び認識エリアが持つ本来の情報が変
化せず、自動機によるダイボンディングやワイヤボンデ
ィング時における認識エラーの発生が激減する。 (2)(1)の結果、製造工程内での直行率の向上、及
びリワーク率の低減等によりコストが削減される。
As described above, the semiconductor chip according to the first aspect of the present invention has the following effects because it has the dummy pattern for preventing film peeling. (1) Since the film peeling that occurs during dicing does not proceed to the recognition area including the recognition mark by the dummy pattern, the original information of the recognition mark and the recognition area does not change, and the recognition is performed during die bonding or wire bonding by an automatic machine. The number of errors is drastically reduced. (2) As a result of (1), the cost is reduced by improving the orthogonality rate in the manufacturing process and reducing the rework rate.

【0017】また、請求項2記載の半導体チップは、認
識マークとL字状パターンの相対関係を一偶角と他偶角
のもので異なるようにしているので、これを読取ること
により、その方向性を識別でき、ワイヤボンディング等
を確実正確に行うことができる。
Further, in the semiconductor chip according to the second aspect, the relative relationship between the recognition mark and the L-shaped pattern is made different for one even angle and the other even angle. It is possible to identify the characteristics, and to perform wire bonding and the like reliably and accurately.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る半導体チップの一部平
面図である。
FIG. 1 is a partial plan view of a semiconductor chip according to an embodiment of the present invention.

【図2】本発明の他の実施例を示す、LEDチップの一
部平面図である。
FIG. 2 is a partial plan view of an LED chip showing another embodiment of the present invention.

【図3】図2に示すLEDチップのL字状パターンと認
識マークの相対関係の異なる他の態様例を示す図であ
る。
FIG. 3 is a diagram showing another mode example in which the relative relationship between the L-shaped pattern of the LED chip shown in FIG. 2 and the recognition mark is different.

【図4】従来例に係る半導体チップの一部平面図であ
る。
FIG. 4 is a partial plan view of a semiconductor chip according to a conventional example.

【符号の説明】[Explanation of symbols]

1 認識マーク 2 認識エリア 3 ダイシングライン 4 半導体チップの端縁 6 ダミーパターン 10 半導体チップ 1 recognition mark 2 recognition area 3 dicing line 4 edge of semiconductor chip 6 dummy pattern 10 semiconductor chip

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体チップにおいて、ダイシングライン
付近に設定された認識マークを含む認識エリアと、ダイ
シングラインとの間に、ダイシング時に生ずる膜剥がれ
が認識エリアまで進行するのを阻止するためのダミーパ
ターンを形成したことを特徴とする半導体チップ。
1. A dummy pattern for preventing film peeling, which occurs during dicing, from advancing to a recognition area between a recognition area including a recognition mark set near a dicing line and a dicing line in a semiconductor chip. A semiconductor chip characterized by being formed.
【請求項2】半導体チップにおいて、チップの一偶角
と、この一偶角と結ぶ線でチップの一端辺が形成される
他偶角に、それぞれ各角を含みダイシングラインに沿っ
て形成されるL字状パターンと、このL字状パターンの
内側に形成される認識マークとで、認識エリアを形成
し、かつ前記一偶角と他偶角のL字状パターンと認識マ
ークの相対関係を互いに異なるように形成したことを特
徴とする半導体チップ。
2. A semiconductor chip is formed along a dicing line including one corner of the chip and another corner forming one end of the chip by a line connecting the corner to each corner. A recognition area is formed by the L-shaped pattern and the recognition mark formed inside the L-shaped pattern, and the relative relationship between the L-shaped pattern and the recognition mark of the one even angle and the other even angle is defined. A semiconductor chip characterized by being formed differently.
JP17141692A 1992-01-06 1992-06-30 Semiconductor chip Expired - Fee Related JP3217459B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP17141692A JP3217459B2 (en) 1992-01-06 1992-06-30 Semiconductor chip
US08/081,392 US5430325A (en) 1992-06-30 1993-06-22 Semiconductor chip having dummy pattern

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP27392 1992-01-06
JP4-273 1992-01-06
JP17141692A JP3217459B2 (en) 1992-01-06 1992-06-30 Semiconductor chip

Publications (2)

Publication Number Publication Date
JPH05251556A true JPH05251556A (en) 1993-09-28
JP3217459B2 JP3217459B2 (en) 2001-10-09

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP17141692A Expired - Fee Related JP3217459B2 (en) 1992-01-06 1992-06-30 Semiconductor chip

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006134968A (en) * 2004-11-02 2006-05-25 Sharp Corp Formation method of dividing position recognition mark, and semiconductor circuit board, manufacturing method of same, and base material of same, and liquid crystal display panel board, liquid crystal display, and manufacturing method of same
US8786092B2 (en) 2005-06-17 2014-07-22 Rohm Co., Ltd. Semiconductor integrated circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006134968A (en) * 2004-11-02 2006-05-25 Sharp Corp Formation method of dividing position recognition mark, and semiconductor circuit board, manufacturing method of same, and base material of same, and liquid crystal display panel board, liquid crystal display, and manufacturing method of same
US8786092B2 (en) 2005-06-17 2014-07-22 Rohm Co., Ltd. Semiconductor integrated circuit device
US9041160B2 (en) 2005-06-17 2015-05-26 Rohm Co., Ltd. Semiconductor integrated circuit device

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