JPH05250817A - Phase calculation device - Google Patents

Abstract

PURPOSE:To reduce an operation amount required for calculating a phase and to make constitution suitable for integration. CONSTITUTION:By the interpolation means 18 of a first step, a signal value between two sampling points is interpolated and then by the interpolation means 19 of a second step, the interpolated signal value and the signal value between one side sampling point and the other side sampling point are interpolated. The process is repeated successively and the position of the nearest value of a threshold value among the signal value of two sampling points and all interpolated signal values is made a phase calculation result finally. Thus, the addition and subtraction amount required for division is reduced and a series of a judging means is simplified and phase calculation suitable for integration is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording device for recording / reproducing digital signals, an optical disc device, or a phase calculating device in a receiving device of a digital communication line.

[0002]

2. Description of the Related Art In a digital recording apparatus or a digital communication receiving apparatus, in order to detect a recorded or transmitted digital signal from a reproduced or received signal, binarization of the signal and reproduction of its clock signal component are performed. A data detection device is used.

In recent years, particularly in a digital recording device, a data detecting device having high performance has been required in order to achieve a high recording density, and a device by digital signal processing has been studied. In the data detection by this digital signal processing, it is necessary to calculate the distance between the sampling time and the discrimination point, that is, the phase difference between the two based on the sampled signal value (for example, Shimada et al. Digital Data Detection of Equipment "The Institute of Electronics, Information and Communication Engineers, 3rd DSP Symposium, Atami City,
(October 1989). Similarly, in identifying received data on a digital communication line, it is necessary to calculate the phase difference between the sampling phase and the clock phase of the received signal for carrier synchronization of the received signal. As an example, in the phase calculation necessary for detecting the data of the reproduction signal in the optical disk device, as shown in FIG. 4, the reproduction signal shown in FIG. 4A which is an input signal is asynchronous with the clock component of FIG. )
The data is discriminated based on the zero-crossing point, and the distance Δ (n) between the sampling time and this zero-crossing point is used.
Will be calculated. First, as shown in the figure, when two consecutive sampling values S (n) and S (n + 1) have different signs, the zero crossing point is detected, and the linear interpolation (Equation 1) The distance Δ (n) between the zero crossing point and the sampling time is calculated.

[0004]

[Equation 1]

As shown in (Equation 1), this calculation requires division. As a general method of implementing division, there is a method of using a read-only memory to write the division result in the memory in advance using the divisor and dividend as addresses. Another method is to use a divider.

An example of a phase calculator using the above-mentioned conventional divider will be described below with reference to the drawings.
FIG. 5 is a circuit diagram showing the configuration of a conventional phase calculator.
In FIG. 5, 1 is a delay device, which delays the sampling value S (n + 1) at the (n + 1) th time expressed in binary number by one sampling clock and outputs S (n). Reference numeral 2 is a subtracter, which outputs the denominator of (Equation 1). Reference numeral 3 is a subtractor, 4 is a bit shifter, 5 is a code decision unit, and 6 is a switch, which form a 1-bit divider 7 of the first stage. Reference numerals 8 and 9 denote 1-bit dividers at the second and Mth stages, respectively.

The operation of the phase calculating device having such a configuration will be described below. First, the denominator of (Equation 1) is output by the delay device 1 and the subtractor 2. The output of the subtractor 2 is shifted by 1 bit by the bit shifter 4,
As a result, one half of the value is input by the subtractor 3 to S
Subtracted from (n + 1). The sign determiner 5 takes the exclusive OR of the most significant bit of the output of the subtractor 3 and the most significant bit of the output of the bit shifter 4, and outputs it. When the output has a different sign, the subtracter 3 output is used, and when it is false, the input S
Select (n + 1) and output. Therefore, the output of switch 6 is from the absolute value of the numerator of (Equation 1) to the absolute value of the denominator of 2
When the remainder obtained by subtracting 1 is positive, the output of the subtractor 3 is selected and output, and when it is negative, S (n + 1) is selected and output. It is equal to the division of 1) and the result of the first bit. In this way, the 1-bit divider 7 operates. The same operation is performed for the second-stage 1-bit divider 8 and thereafter, and the lower bits are sequentially obtained. In addition, the 1st of the Mth stage which is the last stage
As can be easily understood, the bit divider 9 does not need to output the remainder to the next stage, so that the switch is unnecessary.
With the above series of operations, (Equation 1) can be calculated, and the distance Δ
(N) will be obtained.

[0008]

However, the conventional method using the read-only memory requires a large amount of memory and it is difficult to integrate the circuit, and the method using the divider requires a large number of additions and subtractions. Therefore, there is a problem that the circuit scale becomes large and integration is difficult.

In view of the above problems, it is an object of the present invention to provide a phase calculation device that is relatively easy to integrate by modifying the phase calculation algorithm to reduce the number of necessary additions and subtractions.

[0010]

In order to solve the above-mentioned problems, the phase calculating apparatus of the present invention comprises an interpolation means for interpolating signal values between sampled input signal values at a plurality of points, and the interpolation means. It is provided with a configuration of a determination unit that detects the position of a value closest to a specified threshold value in the generated signal value and outputs the position, and in order to simplify the configuration, a plurality of interpolation units are provided. The present invention is provided with a configuration in which the unnecessary interpolation operation that is finally unnecessary is omitted by performing the level determination on the calculation result of each step by dividing into the interpolation means of the step.

Further, a plurality of interpolating means, a plurality of level detecting means, and a plurality of switches are provided, and the one interpolating means, the one level detecting means and the one switch are taken as one unit, It is provided with a decoder which is connected in a cascade manner and which converts the output of the level determination means of each unit into a binary number representation.

[0012]

According to the present invention, the value between the two sampling points is interpolated by the interpolating means and the range of the identification points existing between the two sampling points is limited by the determination of the interpolated value. The above procedure is sequentially repeated, and the position of the finally obtained range is used as the phase calculation result.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a phase calculation device showing a basic configuration of phase calculation by interpolation according to a first embodiment of the present invention, and FIG. 3 is a signal waveform diagram for explaining the operation thereof. In FIG.
Reference numeral 1 denotes a delay device, which delays the sampling value S (n + 1) at the (n + 1) th time expressed in binary number by one sampling clock and outputs S (n). 10 is an adder for adding the input signal and 1 output of the delay device, 11 is 1 output of the adder 2
It is a bit shifter that bit-shifts and interpolates the signal value of the intermediate point, and these constitute the first-stage interpolating means 18. 12 is an adder for adding the input signal and the bit shift 11 output, 13 is a bit shifter for shifting the adder 12 output by 1 bit and interpolating the signal value at the intermediate point, 14 is addition of the bit shifter 11 output and the delay 1 output An adder 15 is a bit shifter for shifting the output of the adder 1 by 1 bit and interpolating the signal value at the intermediate point, and these constitute the second-stage interpolating means 19. Reference numeral 20 denotes an M-th stage interpolating means finally obtained by sequentially repeating the above configuration. Reference numeral 16 is a comparator that selects the signal value closest to the specified threshold value from the output of the M-th stage interpolation means 20 and outputs it as a phase calculation result. Reference numeral 17 converts the output of the comparator 16 into a binary number and outputs it. It is a decoder.

The operation of the phase calculating device having the above-described configuration will be described below with reference to FIGS. 1 and 3.
First, the delay device 1 delays the input S (n + 1) by one clock and outputs S (n). The adder 10 has S (n + 1) and S (n + 1)
(N + 1) is added, and the bit shifter 11 adds the adder 1
The output of 0 is shifted by 1 bit, that is, half of the output of the adder 10 is taken and output. In this way, the adder 10 and the bit shifter 11 that form the first-stage interpolation unit 18
And output the average value of S (n + 1) and S (n), that is, the value of the midpoint. Similarly, the midpoint of S (n + 1) and the output of the bit shifter 11 is taken by the adder 12 and the bit shifter 13 which form the second-stage interpolation means 19, and the bit shifter 14 is output by the adder 14 and the bit shifter 15. And the midpoint of S (n), and bit shifter 1
It will be output together with one output. After that, the same interpolation is performed, and finally, at the output of the M-th stage, 2
M powers of -1 values are obtained. FIG. 3 shows the case of M = 3,
7 points interpolated between S (n) and S (n + 1) are shown. The comparator 16 determines the sign of the interpolated signal value, and since the input signal value is a two's complement representation, it actually only outputs the most significant bit and outputs it as it is.
Therefore, the position where the sign is inverted in the output of the comparator 16 indicates the desired zero crossing point, and the decoder 17
Converts this position into a binary number and outputs it as the phase calculation result.

As described above, the signal value at the position between the two sampling points is obtained by interpolation, and among the obtained values, the one that is close to the threshold value is determined and that position is used as the phase calculation result. Thus, the phase calculation is performed. In the example of FIG. 1, the interpolation means is divided into M stages of interpolation means, which are subordinately performed, and the interpolation of each stage is performed as linear interpolation of the midpoint to simplify the configuration. The interpolated value may be directly obtained without sequentially obtaining the value of the midpoint, and higher-order interpolation may be performed. This high-order technique is described in, for example, multi-rate digital signal processing (R.
E. Crochiere and L.D. R. Rabin
er, "Multirate Digital Sig
nal Processing, "Prentice-"
Hall, 1983). Furthermore, regarding accuracy improvement by the cascade connection of multiple interpolations, Shimada,
Et al., "Calculating Jitter Distribution Using Interpolation," 1990 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers, A-
23, October 1990).

In the interpolation procedure, first, the signal value at the midpoint of two consecutive sampling values is obtained, and the two sampling intervals are divided into two ranges. The first step is to make a decision and then to interpolate the midpoint of this range, so that only the path of the calculation necessary for the phase calculation result finally reaches a value near the threshold value, and the calculation is greatly omitted. Is possible.

FIG. 2 is a circuit diagram showing the configuration of the phase calculator according to the second embodiment of the present invention. In FIG. 2, 21 is an adder for adding the input signal and the output of the delay device 1, 22 is an adder 2
A bit register that shifts 1 output by 1 bit and interpolates the signal value at the intermediate point, and 23 compares the output of the bit register 22 with the output of the delay device 1 and determines whether a prescribed threshold value is included between the values. A code deciding device as a level detecting means for detecting, 24 is a switch for selecting either the input signal or the output of the delay device 1 by the output of the code deciding device 23, and by these, the first stage intermediate interpolation deciding device 26 is formed.
Reference numeral 27 denotes a second-stage intermediate interpolation deciding device, which interpolates the interpolated intermediate-point value and the signal value at the intermediate point between the output of the switch 24 and the interpolated value and the first-stage intermediate value. Intermediate interpolation determiner 26
Is detected by comparing with the interpolated value by the interpolated value by the interpolated value by the interpolated value by Select. Reference numeral 28 denotes a final M-th stage intermediate interpolation judging device. Reference numeral 25 is a decoder constituted by exclusive OR, which inputs the outputs of the respective code determiners, converts them into binary numbers, and outputs them.

Next, the operation of the phase calculating device which is to be constructed in this way will be described. In FIG. 2, the adder 21 takes the sum of the input signals S (n) and S (n + 1) and outputs it, and the bit shifter 22 halves the output of the adder 21.
Is output as the interpolated value of the midpoint of S (n) and S (n + 1). The code determiner 23 uses S (n) and the bit shifter 2
If the two output codes have different signs, "1"
That is, when S (n + 1) and the output of the bit shifter 22 have different signs, "0" is output. The switch 24 sets S (n) to “0” when the output of the code determination unit 23 is “1”.
In case of, S (n + 1) is selected and output. The second-stage middle point interpolation deciding unit 27 operates similarly to the first-stage intermediate interpolation deciding unit 26, and the value of the interpolated midpoint output from the code deciding unit 23 and this At the same time as interpolating the value of the midpoint between the sampling points of different sign and, the code determination is performed, and the interpolated midpoint value and the input value of different sign are selectively output.

According to the above series of operations, the midpoints of two input signal values are interpolated, and the input signal having a different sign from the interpolated midpoint is selectively output. Since the insertion determination is performed up to the Mth stage, the output of the code determiner at each stage represents the position of the discrimination point. For example, in the case of M = 3, the relationship between the code determination result and the phase calculation result of the discrimination point is as shown in (Table 1), and the decoder 25 configured by exclusive OR expresses the output of the code determination unit in binary number. It will be converted into the phase calculation result and output.

[0020]

[Table 1]

In this series of operations, only the portion of the interpolation operation of each stage shown in the example of FIG. 1 which influences the result is selected by the switch and the unnecessary portion is omitted, so that the circuit scale becomes large. This is a miniaturization.

In this embodiment, the interpolating means has been described as a subordinate connection of a plurality of interpolating means for interpolating the midpoint, but this is a single means for interpolating three or more points. Alternatively, in order to improve the accuracy from the first-order interpolation in which two consecutive sampling values are input and the midpoint thereof is obtained, higher-order interpolation may be performed by further inputting two or more sampling values. ..

As described above, according to this embodiment, the midpoint of two input signal values is interpolated and output, and at the same time, the input signal value having a different sign from the interpolated value is selectively output. By providing a plurality of stages of the midpoint interpolation determiner and outputting the code determination result of each stage as the phase calculation output, it is possible to realize a phase calculator suitable for integration with a relatively small amount of calculation.

[0024]

As described above, according to the present invention, by providing the interpolation means, the number of signal values corresponding to the resolution required for phase calculation is interpolated between the two sampling points, and interpolated. The phase can be calculated by obtaining the phase from the position of the signal closest to the threshold value. Further, the interpolation is divided into a plurality of subordinate connections to simplify the process.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a phase calculator according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a phase calculator according to a second embodiment of the present invention.

FIG. 3 is a signal waveform diagram for explaining the operation of the phase calculator of the first embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of a conventional distance calculator.

FIG. 5 is a circuit diagram showing a configuration of a conventional distance calculator.

[Explanation of symbols]

 1 Delay device 10, 12, 14, 21 Adder 11, 13, 15, 22 Bit shifter 16 Comparator 17, 25 Decoder 18, 19, 20 Interpolation means 23 Code decision device 24 Switch 26, 27, 28 Intermediate interpolation decision device

Claims (4)

[Claims] 1. Interpolating means for interpolating and outputting signal values at a plurality of positions between two consecutive sampling points from a sampled input signal, and a predetermined threshold value at a plurality of outputs of the interpolating means. And a determining means for selecting the signal value closest to the position and outputting the position as a phase calculation result. 2. Interpolating means for interpolating and outputting a signal value S3 at the central position with two input signal values S1 and S2, and comparing the S3 with the S1 or S2 to define the values between them. And a switch for selecting and outputting one of S1 and S2 according to the output of the level detecting means. With the one level detecting means and the one switch as one unit, the output S3 of the interpolating means of each unit is cascaded as the input S1 of the next stage and the switch output is S2 of the input of the next stage. Further, the phase calculating device is provided with a decoder for appropriately converting the output of the level detecting means of each unit and outputting the phase calculation result. 3. The phase calculation device according to claim 2, wherein all the interpolation means output an average value of two signal values. 4. The interpolating means of the unit of the first stage is a high-order interpolating means, and the interpolating means of the second and subsequent stages is an interpolating means that outputs an average value of two signal values. Claim 2 characterized by the above-mentioned.
The described phase calculator.