JPH05250498A - Identifier management mechanism and information processor - Google Patents

Abstract

PURPOSE:To improve processing speed and to obtain the chip for small data drive type microprocessors. CONSTITUTION:The color control mechanism for the data drive type microcomputer is provided with a storage circuit 30 having bits storing whether color numbers are used or unused and a detection circuit 31 allocating color numbers corresponding to the unused bits in the storage circuit 30 when data packet P requesting the color supply arrives and setting the bit corresponding to the color number to the state in use. The mechanism is provided with an address decoder 34 setting the bit in use corresponding to the color numbers in the storage circuit 30 to an unused state when the data packet P requesting the color collection comes to perform the color control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention broadly relates to an information processing apparatus for centrally managing data, and more particularly to a management mechanism for an identifier to be uniquely added to data. Furthermore, the present invention can be widely applied to information processing devices with a built-in program, such as a data driven computer.

[0002]

Prior to a detailed description of the prior art, the principle of a dynamic data driven system, which is an industrial application field, will be briefly described. FIG. 4 shows a data flow graph of a program used in the data driven computer. The data flow graph is described in a form in which operation nodes are connected by arcs, and processing on data is performed by the operation nodes. That is, (1) the data arrives at the operation node along the arc. (2) In the operation node, data necessary for the operation (for example,
In the operation node (1) in FIG. 4, a predetermined operation is executed when the two pieces of data A and B all arrive along the arc. (3) The operation result data is sent again from the operation node to the next operation node along the arc. In this figure, the calculation of C = (A + B) * (AB) is shown. When this data flow graph is called from a plurality of programs at the same time, a plurality of data exist on the same arc corresponding to the caller. Therefore, as described in (2) above, when there is no method for distinguishing a plurality of data input along the same arc when detecting the arrival of data necessary for calculation in the calculation node, normal data processing is performed. It will be difficult.

As a method of distinguishing the data on the same arc, a method of using an identifier for distinguishing a plurality of call sources is effective, and is called a dynamic data driving method.
Further, the above identifier is usually called "color". In the dynamic data driven method, a functional unit (hereinafter, referred to as a color management unit) that dynamically manages colors in the system is provided. The color management unit holds the currently available colors, and the available colors issued by each caller each time the same program is called in parallel from a plurality of programs (called a shared function call). To acquire the color (color addition command), the execution of the shared function is completed, the used color is released, and the command to make it available by calling another shared function (color conversion command) is executed again. However, the colors are managed uniformly within the system.

The conventional color management unit is, for example, a specification (Japanese Patent Application Laid-Open No. 60-1190) already filed by the present applicant.
36) (hereinafter referred to as the specification (1)).
As shown in FIG. 3, a pipeline register group 51 for transferring colored tokens, a queue memory 52 made up of a FIFO for holding the colors in the colored tokens, and a color collection processing instruction for advancing the pipeline register group 51. In the pipeline processing method, the color in the color token having the color recovery processing instruction is stored in the queue memory 52, and the pipeline register group 51 is advanced. A color is read from the queue memory 52 by a pipeline processing method with respect to the colored token and embedded in the colored token having the color addition processing instruction, and the embedded color is stored in the queue memory 52.
And a control circuit 53 for sweeping out from.

A conventional color recovery process is executed by a FIFO in which a color (color number) constitutes a queue memory 52.
The color adding process is performed by storing the color from the entry side of, and taking out the color from the latter stage of the FIFO. The color numbers stored in the FIFO are unused color numbers. here,
An example of executing a collection command from a color acquisition command (Get C) is shown. FIG. 6 is a diagram for explaining the operation of the color acquisition command, which is an input packet of the color management unit (before the command is executed).
It also shows the respective states of the input / output packet (after execution of the instruction). The packet format existing in the processor is shown in FIG. 5, and is composed of a tag portion composed of an opcode, a color, and other fields and two operand data.

When a packet having the operation code get C is input to the color management unit, a usable color held in the color management unit is searched, and one of them is input to the data unit (Data) of the input packet. (L)) and output. Similarly, FIG. 7 is a diagram showing the operation of the color conversion instruction. In the case of this command, the input packet is deleted by the color management unit after the command is executed.
The state of the output packet is not described. In addition, 2 of the proceedings of the 32nd national conference of the Information Processing Society of Japan (the first half of 1986)
On pages 11 to 212, FIG. 3C, a color assigning instruction and a color converting instruction for calling a shared function are used on the assumption that this type of color management mechanism is only implemented in the system. Specific methods are also disclosed.

[0007]

In the conventional color management mechanism, (a) it was necessary to fill the color number in the FIFO every initialization. Therefore, it is necessary to add a circuit for initialization, the amount of hardware is increased, and the time required for initialization is longer than usual. (B) When it is formed as an integrated circuit because a FIFO is required, the area occupied by the color management mechanism on the chip becomes large, and downsizing cannot be achieved. Moreover, since a large amount of memory is required, the manufacturing yield is reduced. There was a drawback to drop.

The present invention has been made to solve the above problems, and an object thereof is to provide a color management mechanism which can be easily initialized and can be miniaturized when implemented as an integrated circuit.

[0009]

According to the present invention, as shown in FIG. 1, a memory circuit 30 having a plurality of bits indicating whether the color number is in use or not, and a color addition request. When the data packet P arrives, the storage circuit 30
An empty word detection circuit 31 which assigns a color number corresponding to an unused bit in the memory and sets a bit corresponding to the color number to a used state; The decoder 34 for setting the used bit corresponding to the color number to the unused state is provided.

[0010]

When a color is applied, the empty word detection circuit 31 designates a color symbol corresponding to an empty bit in the memory circuit 30, adds a color, and sets the allocated bit in use. At the time of color collection, the decoder 34 resets the bit in the memory circuit 30 corresponding to the color number to be withdrawn.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
In FIG. 1, 1 and 2 are data latches, 11 and 21 are instruction code fields, 12 and 22 are color identifier fields, 13 and 23 are first operand data fields, and 14 and 24 are second operand data fields. .. Further, 4 is an instruction decoder, 3 is a color management unit body, 5 is a first selector, and the color management unit body 3
Is an empty word detection circuit 31 for outputting one of the bits corresponding to an unused color among the bits of the 32-bit storage circuit 30, in accordance with the priority order, a second selector 32, and an address decoder 34 for detecting a color number. Encoder 33 and selector 35 for detecting the address
It consists of and.

When a packet P having an instruction code, a color number and a plurality of data arrives at the latch 1, the instruction code is stored in the instruction code field 11, the color number is stored in the color identifier field 12, and the data D1 is stored in the first data operand field 13. Then, the data D2 is latched in the second data operand field 14, respectively. The color number from the color identifier field 12 is the color management unit 3
Address decoder 34 and the color identifier field 22 of the latch 2 at the subsequent stage. The instruction code is transferred from the instruction code field 11 to the instruction decoder 4, and the instruction decoder 4 decodes the instruction code and selects either color addition (get C) or color recovery (free C) among the instructions necessary for color management. Decode what.

The signal line M becomes active when the instruction code 11 is get C or free C, and the memory circuit 3
0 is writable. Signal line N is the above instruction code 1
Active when 1 is get C. Therefore, when the instruction code 11 is get C, the first selector 5 selects the output signal of the color management unit 3 and outputs it to the operand data field 23 of the latch 2 in the next stage. The second selector 32 also selects the output signal of the decoder 34.

In the present embodiment, each 1 bit of the memory circuit 30 manages colors 0 to 31. That is, each color (number) corresponds to each bit of the memory circuit 30, and "1" or "0" is written in a certain bit. When "1" is written, it means that the color (number) is currently used, and when "0" is written, it means that it is not currently used and the color number can be given. Show. The storage state of each bit is input to the empty word detection circuit 31.

The operation of the empty word detection circuit 31 will be described before the operation of this embodiment is described. The empty word detection circuit 31 stores the storage state of each bit in the input storage circuit 30 (when it is "1", the corresponding color number is in use, and when it is "0", the corresponding color number is not available. The one having the highest priority is selected from the 32 signals having the value “0”, and all the other signals are set to “0”. This is the output circuit. The priority may be assigned in any order such as the signal line input order.

The empty word detection circuit 31 will be described with reference to FIG. The empty word detection circuit 31 in FIG. 2 is composed of a circuit having a scale for handling 32 color numbers, and divides 32 bits into four unit circuits 45 to 48 each having 8 bits, and each unit circuit is substantially the same circuit. It is composed.
Attention is now paid to the second unit circuit 46.

In this circuit, only the first appearing "1" of PB0 to PB31 among the input signals, PB0, is set to "1" and all other bits are output to the output lines WL0 to WL31. Circuit. As shown in FIG. 2, this circuit is composed of unit circuits 45 to 48 in units of 8 bits.
4 are connected in a cascade state.
The operation of this circuit will be described by focusing on one of the unit circuits. The unit circuit 46 can be functionally classified into two types of circuits, a priority detection circuit 51 and a group bit priority detection circuit 52. The priority detection circuit 51 uses the first "1" in the assigned 8 bits.
The group bit priority detection circuit 52 detects whether or not there is, and outputs the first "1" of the eight bits in charge as "1" and the other bits as "0". According to the detection result of the priority detection circuit 51, if the first "1" exists in the assigned 8 bits, the result of the group bit priority detection circuit 52 is utilized, and otherwise, it is output as "0".

The priority detection circuit 51 will be described in detail. PB8 to PB15 and CYIN are used as input signals,
The signals KILL and CYOUT are output. Signal line, CY
To IN, "1" is propagated when the first "1" is detected in the input signal on the left side of the unit circuit 46, and "0" is propagated otherwise. Therefore, CYIN of the unit circuit 45 at the leftmost end is fixed at "0". Also, K
When ILL is "0", the output signals WL8 to WL15 are "0" regardless of the values of the input signals PB8 to PB15. K
Only when ILL is “1”, the output of the bit priority detection circuit 52 is reflected in the values of the signal lines WL8 to WL15. The operation of the priority detection circuit 51 will be described below.
A description will be given according to the value of IN.

First, when CYIN is "1", 3 inputs N
The OR gate C1 allows the input signal lines PB8 to PB15.
The signal line CYOUT becomes "1" regardless of the value of. The output signal of the gate D1, that is, the signal line KILL
Is "0", the output signal lines WL8-WL15 are connected to the input signal lines PB8-PB by the gates H8-H15.
“0” is output regardless of the value of 15. Then CYIN
Is "0", and when the values of the input signal lines PB8 to PB15 are all "0", the outputs of the gates A1 and A2 are both "0", so that the signal line CYOUT is changed by the gate C1. A signal which becomes "0" and is input to the left side of the unit circuit 46 transmits information that it is "0" to the unit circuit 47 on the right side. In addition, since the output of the gate D1, that is, KILL, becomes "0", the gates H8 to H8
15, the output signal lines WL8 to WL15 are all
"0" is output.

Next, if there is at least 1 bit "1" among the values of the input signal line, PB8 to PB15, the gate A1,
Alternatively, since the output of A2 is "1", the signal line CY
OUT becomes "1", and the information that "1" already exists in the input signal is transmitted to the unit circuit 47 on the right side.
Further, the output signal of the gate D1, that is, KILL is "1".
Therefore, the result of the bit priority detection circuit 52 is output as the value of the output signal lines WL8 to WL15. The group bit priority detection circuit 52 will be described in detail.

This circuit 52 is constructed in units of 2 bits, and four of these are connected in cascade to form an input signal PB8.
It is a circuit that outputs "1" that appears first among PB15 as "1" and outputs "0" otherwise. In this figure, only 2 bits are described in detail. BCYIN, PB
8, PB9 as input signal, BCYOUT, WL8, W
Outputs L9. BCYIN starts from the leftmost end of the input signal line of the unit circuit 46 in units of 8 bits, that is, PB8. If "1" already exists, "1" is set, and otherwise, "0" is set. Is entered. Therefore, the leftmost BCYIN is fixed at "0". The operation of the group bit priority detection circuit 52 will be described according to the value of BCYIN. First, when BCYIN is "1", the output signals WL8 and WL9 are "0" by the gates G8 and G9 regardless of the values of the input signals PB8 and PB9. Also B
CYOUT is also set to "0" by the gate E1.

Next, when BCYIN is "0" and the input signals PB8 and PB9 are all "0", the output signals WL8 and WL9 are "irrespective of the value of the signal line KILL by the gates G8 and G9. It becomes 0 ". Also, BCYO
UT becomes "0" by the gate E1. The input signal P
When B8 is "1", WL9 is always "0" by the gate F1. Further, BCYOUT is output as "1" by the gate E1. When the value of the signal line KILL is "1", "1" is output to the output signal line WL8 by the gates G8 and H8. When the value of the signal line KILL is "0", "0" is output from the output signal line WL8 by the gate H8.

Next, when the input signal PB8 is "0" and PB9 is "1", the gate G8 and H8 of the WL8 outputs "0". In addition, BCYOUT is the gate E1
Outputs "1". When the value of the signal line KILL is "1", the output signal line WL9 is connected to the gates F1 and G.
"1" is output by 9 and H9. When the value of the signal line KILL is "0", the output signal line WL9 outputs "0" from the gate H9.

Next, the operation of the decoder 34 will be described. The decoder 34 is a combinational logic circuit that outputs a 32-bit 32-bit bit pattern different from each other for a 6-bit binary input signal in which "1" is 1 bit and "0" is 31 bits. Next, the operation of the encoder 33 will be described. The encoder 33 is
32 types of 3 with "1" being 1 bit and "0" being 31 bits
It is a combinational logic circuit that inputs a 2-bit bit pattern and outputs different 6-bit binary numbers for each input signal.

Now, the operation of this embodiment will be described.
First, the operation when the instruction code is get C will be described. When the instruction code 11 is get C, the instruction decoder 4 activates the signal line N. Therefore, the second selector 32 selects the output line of the empty word detection circuit 31 and propagates it to the address line of the storage circuit 30. The output signal of the empty word detection circuit 31 is 3 in the storage circuit 30.
Of the two memory circuits whose stored contents are "0", only the bit with the highest priority (referred to as the highest priority bit) is "1", and the other bits are "0" and are output. Such a signal is stored in the memory circuit 3
When input as an address of 0, the above-mentioned highest priority bit is selected for writing. on the other hand,
The selector 35 selects the power supply potential and inputs it to the write terminal of the memory circuit 30. Therefore, "1" (ie, indicating that the corresponding color number is in use) is written in the highest priority bit of the memory circuit 30.
At the same time, the first selector 5 inputs the encoding result of the empty word detection circuit 31, that is, the result of converting the acquired color number into a binary number by the encoder 33, in the first operand data field, as shown in FIG. The operation is realized.

Next, the operation when the instruction code is free C will be described. The signal line N by the instruction decoder 4
Becomes inactive. Therefore, the selector 35 selects the ground potential and inputs it to the write terminal of the memory circuit 30. At the same time, the signal line M becomes active, and the memory circuit 30 becomes writable. Further, the second selector 32 selects the output line of the decoder 34 and inputs it to the address line of the memory circuit 30. The decoder 34 decodes the input binary color number to be converted,
A bit corresponding to a color number to be converted is selected from the 32 memory circuits in the memory circuit 30. Therefore,
"0" is written in the bit corresponding to the color number to be converted.

In the present embodiment, the present invention is used for a data driven computer, but more generally, even when it is used for an information processing device that manages resources by an identifier, the effect of having the same management configuration is obtained. It is clear that it can be obtained.

[0028]

As described above, according to the present invention, a storage circuit having a bit for storing whether a color number is in use or not, and a data packet for requesting color addition arrives. A detection circuit that assigns a color number corresponding to an unused bit in the storage circuit and sets the bit corresponding to the color number to a used state,
Since a decoder for setting the used bit corresponding to the color number in the storage circuit to an unused state when the data packet of the color recovery request arrives, hardware by adding a circuit for initialization is provided. There is an effect that the amount of wear does not increase and the initialization time is shortened. Further, when it is produced as an integrated circuit, the chip is miniaturized, and the yield at the time of manufacturing the chip is improved.

[Brief description of drawings]

FIG. 1 is an overall block diagram of a color management mechanism of the present invention.

FIG. 2 is a detailed diagram of a detection circuit.

FIG. 3 is a block diagram of a conventional color mechanism.

FIG. 4 is a diagram showing a data flow graph of a conventional program.

FIG. 5 is a diagram showing a packet format.

FIG. 6 is a diagram for explaining the operation of a color addition command.

FIG. 7 is a diagram for explaining the operation of a color collection instruction.

[Explanation of symbols]

 1 Data Latch 2 Data Latch 3 Color Management Unit 4 Instruction Decoder 5 First Selector 30 Storage Circuit 31 Detection Circuit 32 Second Selector 33 Priority Encoder 34 Address Decoder P Data Packet

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] September 17, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction content]

A conventional color recovery process is executed by a FIFO in which a color (color number) constitutes a queue memory 52.
The color adding process is performed by storing the color from the entry side of, and taking out the color from the latter stage of the FIFO. The color numbers stored in the FIFO are unused color numbers. here,
An example of executing a color acquisition command (Get C) and a color recovery command is shown. FIG. 6 is a diagram for explaining the operation of the color acquisition command, and shows respective states of an input packet (before command execution) and an input / output packet (after command execution) of the color management unit. The packet format existing in the processor is shown in FIG. 5, and is composed of a tag portion composed of an opcode, a color, and other fields and two operand data.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

[0010]

When a color is added, the empty word detection circuit 31 specifies a color number corresponding to an empty bit in the memory circuit 30, adds a color, and sets the allocated bit in use. At the time of color collection, the decoder 34 resets the bit in the memory circuit 30 corresponding to the returned color number. ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] December 7, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title: Identifier management mechanism and information processing device

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention broadly relates to an information processing apparatus for centrally managing data, and more particularly to a management mechanism for an identifier to be uniquely added to data. Furthermore, the present invention can be widely applied to information processing devices with a built-in program, such as a data driven computer.

[0002]

Prior to a detailed description of the prior art, the principle of a dynamic data driven system, which is an industrial application field, will be briefly described. FIG. 4 shows a data flow graph of a program used in the data driven computer. The data flow graph is described in a form in which operation nodes are connected by arcs, and processing on data is performed by the operation nodes. That is, (1) the data arrives at the operation node along the arc. (2) In the operation node, data necessary for the operation (for example,
In the operation node (1) in FIG. 4, a predetermined operation is executed when the two pieces of data A and B all arrive along the arc. (3) The operation result data is sent again from the operation node to the next operation node along the arc. In this figure, the calculation of C = (A + B) * (AB) is shown. When this data flow graph is called from a plurality of programs at the same time, a plurality of data exist on the same arc corresponding to the caller. Therefore, as described in (2) above, when there is no method for distinguishing a plurality of data input along the same arc when detecting the arrival of data necessary for calculation in the calculation node, normal data processing is performed. It will be difficult.

As a method of distinguishing the data on the same arc, a method of using an identifier for distinguishing a plurality of call sources is effective, and is called a dynamic data driving method.
Further, the above identifier is usually called "color". In the dynamic data driven method, a functional unit (hereinafter, referred to as a color management unit) that dynamically manages colors in the system is provided. The color management unit holds the currently available colors, and the available colors issued by each caller each time the same program is called in parallel from a plurality of programs (called a shared function call). To acquire the color (color addition command), the execution of the shared function is completed, the used color is released, and the command to make it available by calling another shared function (color conversion command) is executed again. However, the colors are managed uniformly within the system.

The conventional color management unit is, for example, a specification (Japanese Patent Application Laid-Open No. 60-1190) already filed by the present applicant.
36) (hereinafter referred to as the specification (1)).
As shown in FIG. 3, a pipeline register group 51 for transferring colored tokens, a queue memory 52 made up of a FIFO for holding the colors in the colored tokens, and a color collection processing instruction for advancing the pipeline register group 51. In the pipeline processing method, the color in the color token having the color recovery processing instruction is stored in the queue memory 52, and the pipeline register group 51 is advanced. A color is read from the queue memory 52 by a pipeline processing method with respect to the colored token and embedded in the colored token having the color addition processing instruction, and the embedded color is stored in the queue memory 52.
And a control circuit 53 for sweeping out from.

A conventional color recovery process is executed by a FIFO in which a color (color number) constitutes a queue memory 52.
The color adding process is performed by storing the color from the entry side of, and taking out the color from the latter stage of the FIFO. The color numbers stored in the FIFO are unused color numbers. here,
An example of executing a color acquisition command (Get C) and a color recovery command is shown. FIG. 6 is a diagram for explaining the operation of the color acquisition command, and shows respective states of an input packet (before command execution) and an input / output packet (after command execution) of the color management unit. The packet format existing in the processor is shown in FIG. 5, and is composed of a tag portion composed of an opcode, a color, and other fields and two operand data.

When a packet having the operation code get C is input to the color management unit, a usable color held in the color management unit is searched, and one of them is input to the data unit (Data) of the input packet. (L)) and output. Similarly, FIG. 7 is a diagram showing the operation of the color conversion instruction. In the case of this command, the input packet is deleted by the color management unit after the command is executed.
The state of the output packet is not described. In addition, 2 of the proceedings of the 32nd national conference of the Information Processing Society of Japan (the first half of 1986)
On pages 11 to 212, FIG. 3C, a color assigning instruction and a color converting instruction for calling a shared function are used on the assumption that this type of color management mechanism is only implemented in the system. Specific methods are also disclosed.

[0007]

In the conventional color management mechanism, (a) it was necessary to fill the color number in the FIFO every initialization. Therefore, it is necessary to add a circuit for initialization, the amount of hardware is increased, and the time required for initialization is longer than usual. (B) When it is formed as an integrated circuit because it requires a FIFO, the area occupied by the chip of the color management mechanism is large, and it cannot be miniaturized. Moreover, since a large amount of memory is required, the manufacturing yield is reduced. There was a drawback to drop.

The present invention has been made to solve the above problems, and an object thereof is to provide a color management mechanism which can be easily initialized and can be miniaturized when implemented as an integrated circuit.

[0009]

According to the present invention, as shown in FIG. 1, a memory circuit 30 having a plurality of bits indicating whether the color number is in use or not, and a color addition request. When the data packet P arrives, the storage circuit 30
An empty word detection circuit 31 which assigns a color number corresponding to an unused bit in the memory and sets a bit corresponding to the color number to a used state; The decoder 34 for setting the used bit corresponding to the color number to the unused state is provided.

[0010]

When a color is added, the empty word detection circuit 31 specifies a color number corresponding to an empty bit in the memory circuit 30, adds a color, and sets the allocated bit in use. At the time of color collection, the decoder 34 resets the bit in the memory circuit 30 corresponding to the returned color number.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
In FIG. 1, 1 and 2 are data latches, 11 and 21 are instruction code fields, 12 and 22 are color identifier fields, 13 and 23 are first operand data fields, and 14 and 24 are second operand data fields. .. Further, 4 is an instruction decoder, 3 is a color management unit body, 5 is a first selector, and the color management unit body 3
Is an empty word detection circuit 31 for outputting one of the bits corresponding to an unused color among the bits of the 32-bit storage circuit 30, in accordance with the priority order, a second selector 32, and an address decoder 34 for detecting a color number. Encoder 33 and selector 35 for detecting the address
It consists of and.

When a packet P having an instruction code, a color number and a plurality of data arrives at the latch 1, the instruction code is stored in the instruction code field 11, the color number is stored in the color identifier field 12, and the data D1 is stored in the first data operand field 13. Then, the data D2 is latched in the second data operand field 14, respectively. The color number from the color identifier field 12 is the color management unit 3
Address decoder 34 and the color identifier field 22 of the latch 2 at the subsequent stage. The instruction code is transferred from the instruction code field 11 to the instruction decoder 4, and the instruction decoder 4 decodes the instruction code and selects either color addition (get C) or color recovery (free C) among the instructions necessary for color management. Decode what.

The signal line M becomes active when the instruction code 11 is get C or free C, and the memory circuit 3
0 is writable. Signal line N is the above instruction code 1
Active when 1 is get C. Therefore, when the instruction code 11 is get C, the first selector 5 selects the output signal of the color management unit 3 and outputs it to the operand data field 23 of the latch 2 in the next stage. The second selector 32 also selects the output signal of the decoder 34.

In the present embodiment, each 1 bit of the memory circuit 30 manages colors 0 to 31. That is, each color (number) corresponds to each bit of the memory circuit 30, and "1" or "0" is written in a certain bit. When "1" is written, it means that the color (number) is currently used, and when "0" is written, it means that it is not currently used and the color number can be given. Show. The storage state of each bit is input to the empty word detection circuit 31.

The operation of the empty word detection circuit 31 will be described before the operation of this embodiment is described. The empty word detection circuit 31 stores the storage state of each bit in the input storage circuit 30 (when it is "1", the corresponding color number is in use, and when it is "0", the corresponding color number is not available. The one having the highest priority is selected from the 32 signals having the value “0”, and all the other signals are set to “0”. This is the output circuit. The priority may be assigned in any order such as the signal line input order.

The empty word detection circuit 31 will be described with reference to FIG. The empty word detection circuit 31 in FIG. 2 is composed of a circuit having a scale for handling 32 color numbers, and divides 32 bits into four unit circuits 45 to 48 each having 8 bits, and each unit circuit is substantially the same circuit. It is composed.
Attention is now paid to the second unit circuit 46.

In this circuit, only the first appearing "1" of PB0 to PB31 among the input signals, PB0, is set to "1" and all other bits are output to the output lines WL0 to WL31. Circuit. As shown in FIG. 2, this circuit is composed of unit circuits 45 to 48 in 8-bit units.
4 are connected in a cascade state.
The operation of this circuit will be described by focusing on one of the unit circuits. The unit circuit 46 can be functionally classified into two types of circuits, a priority detection circuit 51 and a group bit priority detection circuit 52. The priority detection circuit 51 uses the first “1” in the assigned 8 bits.
Then, the group bit priority detection circuit 52 outputs the first "1" of the eight bits in charge as "1" and the other bits as "0". According to the detection result of the priority detection circuit 51, when the first "1" exists in the 8 bits in charge, the result of the group bit priority detection circuit 52 is utilized, and otherwise, it is output as "0".

The priority detection circuit 51 will be described in detail. PB8 to PB15 and CYIN are used as input signals,
The signals KILL and CYOUT are output. Signal line, CY
To IN, "1" is propagated when the first "1" is detected in the input signal on the left side of the unit circuit 46, and "0" is propagated otherwise. Therefore, CYIN of the unit circuit 45 at the leftmost end is fixed at "0". Also, K
When ILL is "0", the output signals WL8 to WL15 are "0" regardless of the values of the input signals PB8 to PB15. K
Only when ILL is “1”, the output of the bit priority detection circuit 52 is reflected in the values of the signal lines WL8 to WL15. The operation of the priority detection circuit 51 will be described below.
A description will be given according to the value of IN.

First, when CYIN is "1", 3 inputs N
The OR gate C1 allows the input signal lines PB8 to PB15.
The signal line CYOUT becomes "1" regardless of the value of. The output signal of the gate D1, that is, the signal line KILL
Is "0", the output signal lines WL8-WL15 are connected to the input signal lines PB8-PB by the gates H8-H15.
“0” is output regardless of the value of 15. Then CYIN
Is "0", and when the values of the input signal lines PB8 to PB15 are all "0", the outputs of the gates A1 and A2 are both "0", so that the signal line CYOUT is A signal which becomes "0" and is input to the left side of the unit circuit 46 transmits information that it is "0" to the unit circuit 47 on the right side. In addition, since the output of the gate D1, that is, KILL, becomes "0", the gates H8 to H8
15, the output signal lines WL8 to WL15 are all
"0" is output.

Next, if there is at least 1 bit "1" among the values of the input signal line, PB8 to PB15, the gate A1,
Alternatively, since the output of A2 is "1", the signal line CY
OUT becomes "1", and the information that "1" already exists in the input signal is transmitted to the unit circuit 47 on the right side.
Further, the output signal of the gate D1, that is, KILL is "1".
Therefore, the result of the bit priority detection circuit 52 is output as the value of the output signal lines WL8 to WL15. The group bit priority detection circuit 52 will be described in detail.

This circuit 52 is constructed in units of 2 bits, and four of these are connected in cascade to form an input signal PB8.
It is a circuit that outputs "1" that appears first among PB15 as "1" and outputs "0" otherwise. In this figure, only 2 bits are described in detail. BCYIN, PB
8, PB9 as input signal, BCYOUT, WL8, W
Outputs L9. BCYIN starts from the leftmost end of the input signal line of the unit circuit 46 in units of 8 bits, that is, PB8. If "1" already exists, "1" is set, and otherwise, "0" is set. Is entered. Therefore, the leftmost BCYIN is fixed at "0". The operation of the group bit priority detection circuit 52 will be described according to the value of BCYIN. First, when BCYIN is "1", the output signals WL8 and WL9 are "0" by the gates G8 and G9 regardless of the values of the input signals PB8 and PB9. Also B
CYOUT is also set to "0" by the gate E1.

Next, when BCYIN is "0" and the input signals PB8 and PB9 are all "0", the output signals WL8 and WL9 are "irrespective of the value of the signal line KILL by the gates G8 and G9. It becomes 0 ". Also, BCYO
UT becomes "0" by the gate E1. The input signal P
When B8 is "1", WL9 is always "0" by the gate F1. Further, BCYOUT is output as "1" by the gate E1. When the value of the signal line KILL is "1", "1" is output to the output signal line WL8 by the gates G8 and H8. When the value of the signal line KILL is "0", "0" is output from the output signal line WL8 by the gate H8.

Next, when the input signal PB8 is "0" and PB9 is "1", the gate G8 and H8 of the WL8 outputs "0". In addition, BCYOUT is the gate E1
Outputs "1". When the value of the signal line KILL is "1", the output signal line WL9 is connected to the gates F1 and G.
"1" is output by 9 and H9. When the value of the signal line KILL is "0", the output signal line WL9 outputs "0" from the gate H9.

Next, the operation of the decoder 34 will be described. The decoder 34 is a combinational logic circuit that outputs a 32-bit 32-bit bit pattern different from each other for a 6-bit binary input signal in which "1" is 1 bit and "0" is 31 bits. is there. Next, the operation of the encoder 33 will be described. The encoder 33 is
32 types of 3 with "1" being 1 bit and "0" being 31 bits
It is a combinational logic circuit that inputs a 2-bit bit pattern and outputs different 6-bit binary numbers for each input signal.

The operation of this embodiment will be described.
First, the operation when the instruction code is get C will be described. When the instruction code 11 is get C, the instruction decoder 4 activates the signal line N. Therefore, the second selector 32 selects the output line of the empty word detection circuit 31 and propagates it to the address line of the storage circuit 30. The output signal of the empty word detection circuit 31 is 3 in the storage circuit 30.
Of the two storage circuits whose stored contents are "0", only the bit with the highest priority (called the highest priority bit) is "1", and the other bits are "0" and are output. Such a signal is stored in the memory circuit 3
When input as an address of 0, the above-mentioned highest priority bit is selected for writing. on the other hand,
The selector 35 selects the power supply potential and inputs it to the write terminal of the memory circuit 30. Therefore, "1" (ie, indicating that the corresponding color number is in use) is written in the highest priority bit of the memory circuit 30.
At the same time, the first selector 5 inputs the encoding result of the empty word detection circuit 31, that is, the result of converting the acquired color number into a binary number by the encoder 33, in the first operand data field, as shown in FIG. The operation is realized.

Next, the operation when the instruction code is free C will be described. The signal line N by the instruction decoder 4
Becomes inactive. Therefore, the selector 35 selects the ground potential and inputs it to the write terminal of the memory circuit 30. At the same time, the signal line M becomes active, and the memory circuit 30 becomes writable. Further, the second selector 32 selects the output line of the decoder 34 and inputs it to the address line of the memory circuit 30. The decoder 34 decodes the input binary color number to be converted,
A bit corresponding to a color number to be converted is selected from the 32 memory circuits in the memory circuit 30. Therefore,
"0" is written in the bit corresponding to the color number to be converted.

In the present embodiment, the present invention is used for a data driven computer, but more generally, even when it is used for an information processing device that manages resources by an identifier, the effect of having the same management configuration is obtained. It is clear that it can be obtained.

[0028]

As described above, according to the present invention, a storage circuit having a bit for storing whether a color number is in use or not, and a data packet for requesting color addition arrives. A detection circuit that assigns a color number corresponding to an unused bit in the storage circuit and sets the bit corresponding to the color number to a used state,
Since a decoder for setting the used bit corresponding to the color number in the storage circuit to an unused state when the data packet of the color recovery request arrives, hardware by adding a circuit for initialization is provided. There is an effect that the amount of wear does not increase and the initialization time is shortened. Further, when it is produced as an integrated circuit, the chip is miniaturized, and the yield at the time of manufacturing the chip is improved.

[Brief description of drawings]

FIG. 1 is an overall block diagram of a color management mechanism of the present invention.

FIG. 2 is a detailed diagram of a detection circuit.

FIG. 3 is a block diagram of a conventional color mechanism.

FIG. 4 is a diagram showing a data flow graph of a conventional program.

FIG. 5 is a diagram showing a packet format.

FIG. 6 is a diagram for explaining the operation of a color addition command.

FIG. 7 is a diagram for explaining the operation of a color collection instruction.

[Description of Reference Signs] 1 data latch 2 data latch 3 color management unit 4 instruction decoder 5 first selector 30 storage circuit 31 detection circuit 32 second selector 33 priority encoder 34 address decoder P data packet

Claims (2)

[Claims] 1. An identifier management mechanism that manages at least one type of identifier according to the usage status, allocates it according to a request, and collects it, whether the identifier is in use or not in use. A plurality of storage circuits that store, and, in response to the assignment request of the identifier, an unused assignable identifier is detected from the storage states of the plurality of storage circuits, and an identifier that is actually assigned from the unused identifiers. A detection circuit that determines the priority based on a predetermined priority; a logic circuit that selects a storage circuit corresponding to an identifier to be recovered from the plurality of storage circuits in response to the recovery request of the identifier; An identifier management mechanism comprising: a storage circuit corresponding to an identifier selected by a logic circuit; and a circuit for changing from a used state to an unused state. 2. An information processing apparatus based on a data driving method, wherein the identifier management mechanism according to claim 1 is used as a color management mechanism.