JPH05250274A - Disk cache device - Google Patents

Abstract

PURPOSE:To provide the high-reliability disk cache device which can semi- permanently hold data regardless of the capacity of a battery, reduces capacity, is compact and inexpensive and can surely hold data even at the time of power failure in a store-in system for writing data in a cache memory before writing them in a disk device. CONSTITUTION:At the disk cache device provided with a control part 2a to perform control for writing data in a cache memory 2b at the time of a write command from a CPU 1, writing data in a disk device 3 after those data to be written are stored for a fixed amount, and holding unwritten data on the cache memory 2b into a non-volatile memory 2c when a power source gets down by power failure or the like, an EEPROM 2f is used as the non-volatile memory 2c, and an alternative area 2g is provided to check read back in the case of moving data to the EEPROM 2f at the time of power failure and to rewrite data when error is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk cache device for writing data to a cache memory at the time of writing, storing a fixed amount of data, and then writing the data to a disk device.

[0002]

2. Description of the Related Art Conventional disk cache devices of this type have been disclosed in, for example, Japanese Patent Laid-Open Nos. 2-249185 and 64.
-76346 and JP-A-59-135563. FIG. 4 is a block diagram showing a conventional disk cache device similar to these prior arts.

In the configuration shown in FIG. 4, 1 is a CPU for controlling the disk cache control device 2, and 2 is the above CPU.
1 shows a disk cache control device that writes data at the time of writing based on the control of 1 and accumulates a certain amount and then collectively writes the data to the disk device 3, and includes a control unit 2a,
The cache memory 2b and the non-volatile memory 2c are provided, and the non-volatile memory 2c is the SRAM 2d.
And a battery 2e.

In the disk cache device having the above structure, only the cache memory 2b is written at the time of writing, and the write to the disk device 3 adopts a store-in system in which a certain amount of data to be written is accumulated. In this store-in method, a mechanism of the non-volatile memory 2c for holding unwritten data on the cache memory 2b is required when the power supply is down due to a power failure or the like. Conventionally, as shown in FIG. The method of writing to the disk device 3 from the normal has been adopted via the SRAM 2a backed up in.

That is, as shown in FIG. 4, when data is written from the CPU 1, data is written only to the cache memory 2b, some amount of data is stored in the cache memory 2b, and then the data is collectively written to the disk device 3 in a store-in system. In the disk cache device, in order to prevent the loss of unwritten data in the cache memory 2b at the time of power failure, the nonvolatile memory 2c including the SRAM 2d and the battery 2e is used as shown in the figure to perform the following control.

(S1) Cache memory 2 during write
Data is written to both b and the nonvolatile memory 2c. (S2) When data is accumulated in the non-volatile memory 2c to some extent, the data is written in the disk device 3.

[0007]

However, the above-mentioned conventional disk cache device has the following problems. (1) SRAM 2d at the time of power failure due to the capacity of the battery 2e
Data retention time is limited. (2) The capacity of the non-volatile memory 2c cannot be increased so much from the capacity of the battery 2e. (3) If not correctly written in the non-volatile memory 2c, there is a possibility that the data cannot be reproduced even after the power failure is restored (it is not known if the memory is really correctly written unless the memory is read again). (4) To increase the data retention time, SRAM2
d and a large-capacity battery 2e are required, which is expensive.

The present invention has been made in order to solve the above-mentioned problems in the conventional example. In the store-in system, data can be held semipermanently regardless of the capacity of the battery, and a small capacity and small size Cheap,
Another object of the present invention is to provide a highly reliable disk cache device that can reliably hold data even in the event of a power failure.

[0009]

DISCLOSURE OF THE INVENTION A disk cache device according to the present invention writes data to a cache memory at the time of a write command from a CPU, and after writing a certain amount of data to be written to the disk device, a power failure occurs. In a disk cache device equipped with a control unit for controlling the unwritten data in the cache memory to be held in the nonvolatile memory when the power source is down due to such reasons, the EEPROM is used as the nonvolatile memory and the EEPROM is used at the time of power failure. An alternative area is provided for checking readback when transferring data and rewriting data when an error occurs.

[0010]

According to the present invention, normally, data is written to the cache memory and then written to the disk device after a certain amount of data to be written is accumulated. Hold unwritten data in EEPROM as non-volatile memory,
At that time, a read-back check is performed, and when an error occurs, the data is rewritten in the alternative area.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. 1 in which the same parts as those in FIG. Figure 1
4 is different from FIG. 4 in that an EEPROM 2f is used as the nonvolatile memory 2c in the disk control device 2.

That is, the nonvolatile memory 2c, which is conventionally composed of the SRAM 2d and the battery 2e, is replaced by the EEPROM.
Set to 2f. By doing so, the limitation of the battery 2e is removed, and the data can be held semipermanently. However,
Since the EEPROM 2f is limited in the number of times of rewriting, it is not written each time it is written, but only when a power failure occurs, unwritten data from the cache memory 2b to the disk device 3 is moved to the EEPROM 2f. Also, EEPR
When the data is transferred to the OM 2f, it is surely read back to check whether or not the data is written in the EEPROM 2f, and if it is not correct, the data is written in the alternative area 2g of the EEPROM 2f.

Next, the operation is shown in FIG.
This will be described with reference to the structural diagram of M2f and the control flowchart of the control unit 2a shown in FIG. Step S1: Normal write is performed only in the cache memory 2b. Step S2: At the time of power failure, the operation is held by the small capacity battery 2e, and the unwritten data in the cache memory 2b is moved to the EEPROM 2f. Step S3: At this time, in order to confirm that the data has been correctly written, ECC is added in advance and read-back check is performed (see FIG. 2). Step S4: If an ECC error occurs when reading back, it is determined that the relevant area of the EEPROM 2f is abnormal, and the data is rewritten to the alternative area 2g. Step S5: When the power failure is restored, the data evacuated to the EEPROM 2f is written to the disk device 3.

Therefore, the above embodiment has the following effects. (1) Since the EEPROM 2f is used as the non-volatile memory 2c, it is possible to hold data semipermanently regardless of the capacity of the battery 2e. (2) The capacity of the non-volatile memory 2c can be set regardless of the capacity of the battery 2e. (3) The read-back check is performed, and if it is not written correctly, the alternative process is performed, so that the data can be reliably retained. (4) The battery 2e is EE from the cache memory 2b.
Since only the data needs to be moved to the PROM 2f, a small capacity is required, and the size and cost can be reduced. (5) In the conventional method, the nonvolatile memory 2c is used even during normal operation.
The SRAM 2d must be operated at a high speed to be expensive, but in the present embodiment, the SRAM 2d does not need to be operated normally. (6) A method of saving to a small disk instead of the EEPROM 2f is also conceivable, but in the case of a disk, it takes time, not only the battery 2e has a large capacity, but also the time to save data after a power failure is restored. Take
Further, if the disk is prepared as a non-volatile memory, it becomes expensive, and this embodiment is superior.

[0015]

As described above, according to the present invention, in the store-in system in which data is written in the cache memory before writing the data in the disk device, unwritten data in the cache memory when the power supply is down due to a power failure or the like. The EEPROM is used as a non-volatile memory to hold the data, and an alternative area is provided to check the read back when transferring data to the EEPROM at the time of power failure and rewrite the data when an error occurs. It is possible to obtain a highly reliable disk cache device which is capable of holding data, has a small capacity, is small and inexpensive, and can reliably hold data even in the event of a power failure.

[Brief description of drawings]

FIG. 1 is a configuration diagram according to an embodiment of the present invention.

FIG. 2 is a structural diagram of an EEPROM 2f shown in FIG.

FIG. 3 is a control flowchart of a control unit 2a in FIG.

FIG. 4 is a configuration diagram of a conventional example.

[Explanation of symbols]

 1 CPU 2 Disk Cache Controller 2a Controller 2b Cache Memory 2c Nonvolatile Memory 2e Battery 2f EEPROM 2g Substitute Area 3 Disk Device

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] August 10, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

In the configuration shown in FIG. 4, 1 is a CPU for controlling the disk cache control device 2, and 2 is the above CPU.
1 shows a disk cache control device that writes data at the time of writing based on the control of 1 and accumulates a certain amount and then collectively writes the data to the disk device 3, and includes a control unit 2a,
A cache memory 2b and a non-volatile memory 2c are provided.
And, also, the non-volatile memory 2c is SRAM2d
And a battery 2e.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

The present invention has been made in order to solve the above-mentioned problems in the conventional example. In the store-in system, data can be held semipermanently regardless of the capacity of the battery, and a small capacity and small size Cheap,
And the purpose and provide child highly reliable disk cache device that can hold data reliably even in a power failure or the like.

Claims (1)

[Claims] 1. When data is written to a cache memory at the time of a write command from the CPU and a certain amount of data to be written is accumulated and then written to a disk device, and when the power supply is down due to a power failure or the like, the data on the cache memory is stored. In a disk cache device equipped with a control unit for controlling unwritten data to be held in a non-volatile memory, an EEPROM is used as the non-volatile memory, and read-back is checked when data is transferred to the EEPROM at the time of power failure, and data is read when an error occurs. A disk cache device having an alternative area for rewriting data.