JPH052500A - Software tester of multi-processor system - Google Patents

Abstract

PURPOSE:To realize the strict test of the execution of exclusive control by testing the exclusive control to information resources after the simultaneous use environment of plural processors for the information resources is made. CONSTITUTION:An interruption point setting part 410 sets, for example, the processing step to access shared resources 130 for each processor as the interruption point of the program executed by respective processors 100 and 110. Subsequently, by the test starting instruction, respective processors start the execution of the program, and at the time of reaching the set interruption point, the execution is interrupted forcibly by an interruption control mechanism 500, and when all processors of the test object interrupt the execution, the program after the interruption point is simultaneously instructed by an interruption releasing instructing part 420. By the re-starting of the program execution, the conditions to access simultaneously the shared information resources 130 are forcibly prepared, and by the conditions, respective processors 100 and 110 synchronize and access. Thus, the execution of the exclusive control can be strictly tested.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention tests whether or not exclusive control of information resources is normally performed in a multiprocessor system composed of a plurality of processors sharing information resources such as a main memory. It relates to a software tester for a multiprocessor system.

[0002]

2. Description of the Related Art Conventionally, there has been known a multiprocessor system including a plurality of processors sharing an information resource such as a main memory. This multiprocessor system is a tightly coupled system in which a plurality of processors are arranged in the same housing, and a coarsely coupled system in which a plurality of processors are arranged in different housings and connected by communication lines or cables. Is roughly divided into

In such a multiprocessor system, as with a general computer system, when a program is installed, it is confirmed whether the program operates according to specifications, that is, debugging is performed. However, it is difficult to debug because each processor operates in parallel according to the program installed in its own processor.

Therefore, in Japanese Patent Publication No. 60-45453, an abnormal condition to be analyzed is set as an interruption condition, and when the set interruption condition occurs, the execution of the program in each processor is interrupted. A method has been proposed in which information in a main storage device that is commonly used by each processor in an interrupted state is captured and debugging of a program is supported by this captured information.

[0005]

In a multiprocessor system of this type, however, the programs assigned to the respective processors are independently executed in parallel for each processor, so that a part of the main memory is not available. If the information resources of the shared area or all areas are shared and the processes associated with each other are to be performed, it is necessary to prevent system down or malfunction due to conflicting access to this shared information resource. Have to control. That is, for example, when considering a multiprocessor system including two processors A and B, if the processor A first accesses the shared information resource, another processor B issues an access request during the access. Even in this case, the access request of the subsequent processor B must be rejected. Further, when the two processors A and B try to access at the same time, it is necessary to control so that only one of them is allowed to access and the other is denied. Such control is generally defined as exclusive control, but when shipping a multiprocessor system as a product, test whether this exclusive control is performed normally and confirm the reliability of the product. There is a need.

In this case, the most strict test condition as to whether or not the above exclusive control can be normally performed is the case where each processor simultaneously accesses the shared resource.

However, in the prior art proposed in the above publication, the execution of the program in each processor is suspended after waiting for the occurrence of a specific abnormal state to be analyzed. Although it is possible to debug the program based on the information in the main storage device at the time of performing, it is not possible to strictly test whether the exclusive control is normally performed. That is,
In this type of multiprocessor system, even if the execution of programs in each processor is started at the same time, each program tries to access the shared information resource according to its own request, and therefore the access timing is completely asynchronous. Therefore, if the execution of each program was interrupted after waiting for the occurrence of a specific abnormal state, whether the access timings at this interruption were exactly the same,
It is completely unknown whether they were completely different or very close. Therefore, there is a problem that it is not possible to forcibly create a test condition for exclusive control and strictly test whether or not exclusive control is normally performed.

The present invention is intended to solve such a problem, and its object is to provide a software tester of a multiprocessor system capable of strictly testing whether or not exclusive control is normally performed. Is.

[0009]

In order to achieve the above object, the present invention provides an interruption point setting means for setting and instructing an interruption point of a program executed by each processor for each processor, and this interruption point setting means. A plurality of processors for the information resources are provided with an interruption cancellation instruction means for instructing cancellation of the interruption under the condition that the execution of the program is interrupted by all of the processors to be tested at the interruption point set by It is configured to create a simultaneous use environment of and to test exclusive control to information resources in this simultaneous use environment.

[0010]

According to the above means, for example, a processing step or address for accessing a shared information resource is set for each processor as an interruption point of a program executed by each processor. After this, the start of the test is instructed. Then, each processor starts the execution of the program, but when the interruption point set by the interruption point setting means is reached, the execution of the program is forcibly interrupted. Then, if all the test target processors interrupt the execution of the program, the execution of the program after the interruption point is simultaneously instructed. By restarting the execution of this program, a condition for simultaneously accessing the shared information resource is forcibly created, and under this condition, the respective processors synchronously access the shared information resource. This makes it possible to strictly test whether the exclusive control is normally performed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a functional block diagram showing the overall configuration of the embodiment, FIG. 2 is an explanatory flowchart of the interruption point setting process, and FIG. 3 is an explanatory flowchart of the interruption cancellation control process.

In FIG. 1, 100 is a first processor, 110 is a second processor, 120 is a main memory,
Reference numeral 130 denotes a shared area located in the main memory device 120 and shared by programs installed in the first and second processors 100 and 110, respectively. The first and second processors 100 and 110 and the main memory device 130 are common areas. A multiprocessor system 140 is constituted by 120.

Reference numeral 300 is an operating terminal, and 400 is a software tester.

The software tester 400 has an interrupt point setting unit 410 for setting an interrupt point of a program executed by each processor 100, 110 for each processor, and a condition that the processors 100, 110 in the system interrupt the execution of the program. It is composed of an interruption cancellation instruction unit 420 for instructing cancellation of interruption and restarting execution of the program.

A reference numeral 500 interrupts the execution of the program at the breakpoint set by the breakpoint setting section 410, detects the interrupt event of each processor 100, 110 and notifies the interrupt cancellation instruction section 420, and the interrupt cancellation instruction section. It is an interruption control mechanism that releases the interruption state of the program based on an instruction from 420, and is configured by software different from the software tester 400.

The operation of the exclusive control test will be described below with reference to FIGS. 2 and 3.

First, the test operator uses the explanation flow of FIG.
As indicated by step 1000 in the figure, each processor 10
In order to synchronize the programs operating in 0 and 110, the names of the processors 100 and 110 to be interrupted and the interruption points at which the programs are interrupted are input from the operation terminal 300, and the software tester 400 is notified.

Here, as an interruption point for interrupting the program, for example, data representing a processing step or an address for accessing the shared area 130 is input and set for each processor. At the same time, the interruption release delay time data indicating the time from the interruption to the resumption is given to the operation terminal 3
00 to instruct the software tester 400. The data representing the processor name, the interruption point, and the interruption release delay time thus set are the interruption point setting unit 4
Registered in 10.

Then, the interruption point setting unit 410 then notifies the interruption control mechanism 500 of the data indicating the name of each processor and the interruption point, as shown in step 1010. Further, the interruption point setting unit 410 notifies the interruption cancellation instructing unit 420 of the data indicating the processor name and the interruption cancellation delay time, as shown in the next step 1020.

The interruption canceling instruction section 420 then registers and holds the data indicating the processor name and the interruption cancellation delay time notified from the interruption point setting section 410, as shown in step 2000 of FIG.

The test operator specifies the names of the processors 100 and 110 to be interrupted, the interruption points and the interruption release delay time from the operation terminal 300 to the software tester 400, and then the processors 100 and 110.
To execute the program embedded in.

By executing the program, each processor 1
If the address or the processing step of the instruction word to be executed in 00 or 110 matches the content set and registered in the interruption point setting unit 410, the interruption control mechanism 500 interrupts the execution of the program of the processor 100 or 110.

As a result, the execution of the programs of the processors 100 and 110 is suspended, and this suspension event is detected by the suspension control mechanism 500. Therefore, as shown in step 2010, the interruption control mechanism 500 notifies the interruption cancellation instruction unit 420 of the interruption event of the processors 100 and 110 and the name of the processor that interrupted the program execution.

Therefore, the interruption cancellation instructing section 420, as shown at step 2020,
It is determined whether all 110 have interrupted the execution of the program. When all of the processors 100 and 110 to be suspended have not been suspended, the suspension cancellation instruction unit 420 waits until the suspension control mechanism 500 receives a suspension notification of a suspended processor that has not been suspended. As described above, until the suspension target processors 100 and 110 are all suspended, steps 2010 to 2010 are performed.
The processing of 2020 is repeated.

Next, as shown in step 2030, when all of the suspend target processors 100 and 110 suspend the execution of the program, the suspend cancel instruction unit 420 instructs the suspend control mechanism 500 to suspend all the processors 100 and 110. Instruct to cancel. In this case, when the interruption cancellation delay time is set, the interruption cancellation instruction unit 420 gives the interruption cancellation instruction after the set interruption cancellation delay time has elapsed. The interruption control mechanism 500 which has received the interruption cancellation instruction follows the instruction, as shown in the time chart of FIG.
The execution of the programs of the suspended processors 100 and 110 is restarted at the simultaneous time t.

By restarting the execution of this program, an environment for simultaneously accessing the shared area 130 of the main storage device 120 is forcibly created, and under this condition, each processor 10 is accessed.
0 and 110 access the shared area 140 at the same time in synchronization. This makes it possible to strictly test whether the exclusive control is normally performed.

In this case, the interruption release delay time td is td for the processor 100 and td for the processor 110.
When 2 is set, as shown in the time chart of FIG. 4, the processor 100 restarts the execution of the program after the lapse of td1 time after the interruption cancellation instruction from the interruption cancellation instruction unit 420 is given, and the processor 110 After the lapse of td2 hours, the execution of the program is restarted. Therefore, in this embodiment, the programs of the processors 100 and 110 can be completely synchronized and restarted at the same time, or restarted at a timing shifted by a desired time.

This makes it possible to easily test the exclusive control of the processors 100 and 110 in various timing relationships. Further, the processor to be suspended can be freely selected by the processor name. Therefore, when there are three or more processors, the combination can be freely selected and the exclusive control test can be performed.

In the above embodiment, the multiprocessor 140 is shown as a tightly coupled type, but the present invention can be similarly applied to a coarsely coupled type multiprocessor system.

Although the number of processors is two in the above example, the same can be applied to the case of three or more.

Although the processor name is set in the embodiment, it is not necessary when the number of processors is two.

[0033]

As described above, according to the present invention, in a multiprocessor system composed of a plurality of processors, an interruption point setting means for setting and instructing an interruption point of a program executed by each processor is provided. A main memory device is provided with an interruption instruction canceling means for instructing cancellation of the interruption under the condition that all of the processors to be tested interrupt the execution of the program at the interruption point set by the interruption point setting means, and restarting the execution of the program at the same time. Since the environment for simultaneous use of multiple processors for information resources such as is created and configured to test the exclusive control on the information resources in this simultaneous use environment, whether or not the exclusive control is normally performed is strict. Can be easily tested. As a result,
It is possible to provide the user with a highly reliable multiprocessor system.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is an explanatory flow chart showing a procedure of an interruption point setting process in the embodiment.

FIG. 3 is an explanatory flowchart showing a procedure of interruption cancellation instruction processing in the embodiment.

FIG. 4 is a time chart for explaining the access timing of the processor to the main memory shared area in the embodiment.

[Explanation of symbols]

 100 First Processor 110 Second Processor 120 Main Storage Device 130 Shared Area 140 Multiprocessor System 300 Operating Terminal 400 Software Tester 410 Break Point Setting Unit 420 Break Cancel Instructing Unit 500 Break Control Mechanism

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Nomura 5030 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi Ltd. Software Development Division

Claims (1)

Claim: What is claimed is: 1. A test is carried out as to whether or not exclusive control to the information resource is normally performed in a multiprocessor system including a plurality of processors sharing an information resource such as a main memory. A software tester for a multiprocessor system, wherein a break point setting means for setting and instructing a break point of a program executed by each processor and a processor to be tested at the break point set by the break point setting means All provide an instruction to cancel the interruption under the condition of interrupting the execution of the program, and provide an interruption cancellation instruction means for resuming the execution of the program at the same time, creating a simultaneous use environment of a plurality of processors for the information resource,
A software tester for a multiprocessor system characterized by testing exclusive control over information resources in this simultaneous use environment.