JPH05249058A - Interface circuit - Google Patents

Abstract

PURPOSE:To attain a construction wherein an output at a lower level is prohibited by a signal of a raised level, an output operation is stopped when the level lowers and execution of the output operation is enabled again the level of the signal lowered is raised. CONSTITUTION:An interface circuit comprises a low-level input terminal 1, an intermediate-level input terminal 2, a D-type flip-flop 8 for inhibiting a low- level output signal according to a signal from the intermediate-level input terminal 2, a high-level input terminal 3, and a D-type flip-flop 15 for inhibiting an intermediate-level output signal according to a signal from the high-level input terminal 3. Moreover, the interface circuit comprises a zero-level terminal 4 for canceling the inhibition of the low-level output signal by sending a signal to the D-type flip-flop 8, and a trigger circuit 27 for canceling the inhibition of the intermediate-level output signal by sending a signal to the other D-type flip-flop 15 according to the output of the low-level signal.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an input signal having a level of 1.
When the level goes up, it has a function to raise the level while prohibiting the output at the previous level. When the level goes down by one rank, the output is stopped by the prohibition function, and when it goes down by another rank, it goes to the previous level. The present invention relates to an interface circuit having a function of bringing an output of a higher level into a state where it can be output.

[0002]

2. Description of the Related Art Although an interface circuit that outputs according to the level of an input signal has been conventionally used,
No interface circuit has been developed in which the output is completely lost when the input level is lowered.

Therefore, in the conventional interface circuit,
When the input level dropped, the output remained at the lowered level.

[0004]

When it is desired to obtain a control signal only when the signal level increases, the conventional interface circuit cannot be used.

The present invention solves these conventional drawbacks,
It is an object of the present invention to provide an interface circuit that prohibits output at a lower level with a signal whose level has risen and enables output again when the level of a lowered signal rises.

[0006]

The interface circuit of the present invention has a low level input terminal to which a low level signal is input, a low level output terminal connected to the low level input terminal, and a signal input to the low level input terminal. A middle level input terminal to which a high signal is input and a middle level output terminal connected to the middle level input terminal, a D type flip-flop for stopping the output of the low level signal by a signal from the middle level input terminal, and the middle level input terminal A high-level input terminal to which a signal having a higher level than the signal and a high-level output terminal connected to the high-level input terminal, and a D different from the above in which the output of the intermediate-level signal is stopped by the signal from the high-level input terminal
A type flip-flop, a zero-level terminal that sends a signal to the D-type flip-flop to cancel the output stop of the low-level signal, and a signal to another D-type flip-flop by the output of the low-level signal And a trigger circuit for releasing the output stop.

[0007]

[Operation] When the level of the input signal drops to the middle level or the low level while the output is made by the high level input signal, the output disappears, and the level of the input signal lowered to the middle level rises to the high level or low level. When the input signal, which has been lowered to, rises to a medium level, output is restarted.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, in which 1 is a low level input terminal to which a low level signal is input, and 2 is a signal whose level is higher than the signal input to the low level input terminal 1. Is a high level input terminal to which a signal having a higher level than the signal input to the middle level input terminal 2 is input, and 4 is a zero level terminal of zero potential. And each of these terminals 1, 2, 3, 4
Are grounded via a noise absorbing capacitor 5, respectively.

The low level input terminal 1 is connected by a line 6 to one input terminal of a NOR gate 7, and the other terminal of the NOR gate 7 is connected to the output terminal of a D-type flip-flop 8. The output side of the NOR gate 7 is connected to the low level output terminal 10 via the inverter 9. Reference numeral 11 is a middle level output terminal, and 12 is a high level output terminal.

The intermediate level input terminal 2 is connected by a line 13 to one input terminal of a NOR gate 14 different from the NOR gate 7, and the other terminal of the NOR gate 14 is different from the D type flip-flop 8. It is connected to the output terminal of another D-type flip-flop 15.
The output side of the other NOR gate 14 is connected to the middle level output terminal 11 via the inverter 16.
Further, the middle level input terminal 2 is connected to the D type flip-flop 8 via the line 17 branched from the line 13 and the inverter 18, and the zero level terminal 4 is connected to the inverter 19 in the D type flip-flop 8. It is connected via a line 20.

The high level input terminal 3 is connected to the high level output terminal 12 via the line 21, the inverter 22, the line 23 and the inverter 24, and the D type flip-flop 15 is connected by the line 25 branched from the line 23. It is connected to the. This D-type flip-flop 15 has the above-mentioned low-level input terminal 1 on the line 6
It is connected via a line 26, a trigger circuit 27, and a line 28 that branch off from. And trigger circuit 2
Reference numeral 7 includes a condenser 29, a knot element 30, a condenser 31, resistors 32 and 33, and an OR element 34.

Next, the operation will be described with negative logic.

The NOR gates 7 and 14 output when there is no prohibition input from the D type flip-flops 8 and 15, respectively, and do not output when there is a prohibition input. The D type flip-flop 8 outputs a prohibition signal when an input is made from the intermediate level input terminal 2 via the line 17 and the inverter 18, and the D type flip-flop 1
Reference numeral 5 outputs a prohibition signal when there is an input from the high level input terminal 3 via the line 21, the inverter 22 and the line 25.

When a high level signal is being input from the high level input terminal 3, the signal input from the high level input terminal 3 is the line 21, the inverter 22, the line 23,
It is output from the high level output terminal 12 through the inverter 24. At this time, since the high level signal from the high level input terminal 3 is input to the D type flip-flop 15 via the line 25, the D type flip-flop 15 outputs a stop signal to the NOR gate 14 to output the medium level signal. Mid-level signal from input terminal 2 is mid-level output terminal 1
I cannot output from 1.

When the signal level drops from high to middle, the middle level signal from the middle level input terminal 2 cannot be output from the middle level output terminal 11 due to the stop signal held in the D type flip-flop 15. Further, since the stop signal is output to the NOR gate 7 by inputting the medium level signal to the D type flip-flop 8 through the line 17, it is also impossible to output the low level signal. In this way, when the level drops from high to medium, neither the medium level signal nor the low level signal is output, and only the high level signal can be output.

When the signal level further drops to the low level from this state, the low level signal from the low level input terminal 1 becomes
Due to the stop signal held in the D-type flip-flop 8, it cannot be output from the low level output terminal 10. Further, at this time, the low level signal is led to the trigger circuit 27 via the line 26 and the signal from the trigger circuit 27 is led to the D type flip-flop 15, so that the stop signal held in the D type flip-flop 15 is Is cleared. Therefore, when the signal level becomes the middle level again, it can be output from the middle level output terminal 11.

When the signal level further reaches the zero level, the zero level signal from the zero level terminal 4 is guided to the D type flip-flop 8 and the stop signal held in the D type flip-flop 8 is cleared. Therefore, if the signal level becomes low again, it can be output from the low level output terminal 10.

As described above, the interface circuit 35 shown in FIG. 1 does not output the output signal when the level of the input signal decreases, and outputs the output signal again when the level of the input signal increases.

Next, the interface circuit 35 described above.
An example of the use of will be described with reference to FIG.

FIG. 2 is a longitudinal sectional view showing an example of use of the interface circuit 35, which is applied to a detection device for a ventilation device of a long tunnel 36 and the like.

An interface circuit 35 is provided outside the tunnel 36, and a gas concentration sensor 37 for detecting the concentration of gas such as carbon dioxide and nitrogen oxide is provided inside the tunnel 36. 37 is connected to the input terminal of the interface circuit 35.
The gas concentration sensor 37 inputs a low-level signal to the interface circuit 35 when the concentration of carbon dioxide, nitrogen oxides, etc. in the tunnel 36 is low, and the concentration of carbon dioxide, nitrogen oxides, etc. in the tunnel 36 is reduced. A higher level signal is input to the interface circuit 35 as the signal level increases. In the above configuration, for example, by issuing a command only when the concentration of gas such as carbon dioxide and nitrogen oxides in the tunnel 36 increases, and observing the traffic condition of the vehicle, wind direction, wind strength, etc.,
It is measured in which case the concentration of gas such as carbon dioxide and nitrogen oxides is likely to rise, and the controller 39 controls the drive of the ventilation fan 38 by using this as reference data.

Of course, the present invention can also be used in various applications other than those shown in FIG.

[0024]

The present invention has the effect of continuing the output when the level of the input signal is the same or higher, and stopping the output when the level of the input signal decreases.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a vertical sectional view showing a usage example of the present invention.

[Explanation of symbols]

 1 Low level input terminal 2 Medium level input terminal 3 High level input terminal 4 Zero level terminal 8 D type flip-flop 10 Low level output terminal 11 Medium level output terminal 12 High level output terminal 15 D type flip flop 27 Trigger circuit 35 Interface circuit

Claims (1)

[Claims] 1. A low-level input terminal to which a low-level signal is input and a low-level output terminal connected to the low-level input terminal, and a medium-level input terminal to which a signal having a higher level than the signal input to the low-level input terminal is input. The connected middle level output terminal, the D-type flip-flop that stops the output of the low level signal by the signal from the middle level input terminal, and the signal having a higher level than the signal input to the middle level input terminal are input. A high-level input terminal and a high-level output terminal connected thereto, a D-type flip-flop different from the above for stopping the output of a medium-level signal by a signal from the high-level input terminal, and a signal to the D-type flip-flop. A zero level terminal that sends the signal to release the low-level signal output stop, and another D-type flip flow by the low-level signal output. And a trigger circuit that sends a signal to the device to release the output stop of the middle level signal, and an interface circuit.