JPH05243964A - Buffer - Google Patents

Abstract

PURPOSE:To provide a buffer which can propagate even an input signal slowly transiting its state, with a short delay time. CONSTITUTION:In a buffer sending an output signal based on the input signal of the two value of high/low by changing within the limit of power' source potential and ground potential, the system is provided with a high threshold circuit 2A which has a threshold set higher than the middle point potential of power source potential and ground potential, a low threshold circuit 2B which has a threshold set lower than the middle point potential, a drive circuit 5 outputting a drive signal when the input signal is within the limit between the threshold of the low threshold circuit and that of the high threshold circuit and an output circuit 9 sending the output signal based on the drive signal from the drive circuit and sending the output signal when the input signal goes up higher than the threshold of the high threshold circuit and it goes down lower than the threshold of the low threshold circuit. With this constitution, the level of the input signal is detected based on the respective thresholds of the high/low threshold circuits to send the output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer, and more specifically, it transmits a signal from the outside into an integrated circuit chip of a semiconductor integrated circuit system, or is connected to a heavily loaded data bus for signal transmission. Regarding the buffer.

[0002]

2. Description of the Related Art A conventional buffer will be described with reference to FIGS. The buffer 20 shown in FIG. 3 is a C-MO.
Transistors (P-channel and N-channel transistors) 21 to 24 formed by S are non-inverting type, and output an output signal O1 when the input signal I1 shown in FIG. 4 is input. .. The input signal I1 and the output signal O1 are designed to fully swing between the power supply voltage level Vdd and the ground level Vss, as shown in FIG. Further, the threshold voltage Vt of the buffer 20 is assumed to be the midpoint potential of the power supply voltage level Vdd and the ground level Vss.

Next, the time change of the input signal I1 and the output signal O1 will be considered. The input signal I1 begins to change from low to high at time t1 ', becomes 1 / 2.Vdd at time t2', and when it exceeds the threshold voltage Vt, from that time (t10'-t
2 ') Output signal O1 changes from low to high with a delay. Then, this output signal O1 eventually becomes the power supply voltage level Vdd.

Further, the input signal I1 starts to fall from time t4 'and falls below the threshold voltage Vt after time t5'. The output signal O1 changes from high to low with a delay of (t20'-t5 ') from the time t5'. Here, (t10'-t2 ') and (t20'-t5') are delay times correlated with the sum of the delay inside the buffer 20 and the delay due to the load.

[0005]

However, in the conventional buffer 20 having the above-described signal propagation characteristic, when the input signal I1 is a signal that changes slowly from the steady state, that is, the time until the threshold voltage Vt is reached ( t2'-t
When 1 ', t5'-t4') is long, there is a problem that the signal propagation time of the buffer 20 becomes long, which causes a problem in practical use.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a buffer capable of propagating an input signal which undergoes a state transition in a short delay time.

[0007]

In order to achieve the above object, the buffer of the present invention sends an output signal based on an input signal which changes within a range of a power supply potential and a ground potential and takes a binary value of high and low. In the buffer, a high threshold circuit that sets a threshold value higher than the midpoint potential of the power supply potential and the ground potential, a low threshold circuit that sets a threshold value lower than the midpoint potential, and the input signal is the low threshold value. A drive circuit that outputs a drive signal when the threshold value of the circuit is within the range of the threshold value of the high threshold circuit, and the output signal is sent based on the drive signal from the drive circuit, and the input signal is the high threshold circuit. The output circuit sends out the output signal when the output voltage rises above the threshold of (1) and when it drops below the threshold of the low threshold circuit.

[0008]

The operation of the buffer of the present invention constructed as above will be described below. When an input signal that changes in the range of the power supply potential and the ground potential and takes a binary value of high and low is input to the buffer and the threshold level of the low threshold circuit is exceeded, the drive circuit sets the input signal to the threshold of the high threshold circuit. Continues to output drive signals. The output circuit sends an output signal based on the drive signal. When the level of the input signal exceeds the threshold of the high threshold circuit, the drive signal of the drive circuit disappears, but at this time the output circuit continues to output the output signal based on the output of the high threshold circuit.

Eventually, the input signal begins to fall, but the output circuit continues to output the output signal based on the output of the high threshold circuit until the threshold of the high threshold circuit is reached. While the input signal falls from the threshold of the high threshold circuit to the threshold of the low threshold circuit, the drive signal is output from the drive circuit, and the output circuit outputs the output signal based on the drive signal. When the input signal further drops and becomes equal to or lower than the threshold value of the low threshold circuit, the output circuit continues to output the output signal based on the output of the low threshold circuit.

In this way, since the output signal is sent out by detecting the level of the input signal based on each threshold value of the high threshold circuit or the low threshold circuit, a short delay time is obtained even for an input signal that makes a gradual state transition. Can be propagated in.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A buffer which is an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a buffer which is an embodiment of the present invention. The buffer 1 shown in FIG. 1 has an input terminal 7 to which an input signal I that changes in a range of a power supply potential VDD and a ground potential VSS and takes a binary value of high and low, and an output signal O based on the input signal I are input. Input the output terminal 8 for outputting and the input signal I from the input terminal 7,
Threshold voltage VTH higher than the midpoint potential (1/2 VDD) of the power supply potential VDD (= 5 V) and the ground potential VSS that perform threshold processing respectively.
(= 3.5V) is set as the high threshold circuit of the inverter 2A and the threshold value VTL (= 1.5) lower than the midpoint potential thereof.
V) is set, the threshold value processing circuit 2 including the inverter 2B as a low threshold value circuit and the output signals of the inverters 2A and 2B are respectively taken in, and the logical product of these is taken to obtain the input signal I.
Level is threshold VTH of inverter 2A, inverter 2B
2-input 1-input low-active AND gate 5 as a drive circuit that outputs a drive signal within the threshold VTL range of
And an output signal O based on the drive signal from the AND gate 5.
And an output circuit 9 which outputs an output signal O when the input signal I is equal to or higher than the threshold value VTH of the inverter 2A and when the input signal I is lower than or equal to the threshold value VTL of the inverter 2B.

The output circuit 9 includes a P-type transistor 3,
It is composed of an N-type transistor 4 and a tri-state Schmidt inverter 6, the P-type transistor 3 is driven by the output signal of the inverter 2A, and the N-type transistor 4 is driven by the output signal of the inverter 2B to turn them on.
It is turned off and an output signal is sent to the output terminal 8. The Schmitt inverter 6 is driven by the drive signal from the AND gate 5, and the Schmitt inverter 6 also sends an output signal to the output terminal 8. The width of the hysteresis of the Schmitt inverter 6 is set to 3 V or more centering on the midpoint potential (1/2 VDD), about 3.7 V on the high side and about 1.3 V on the low side.

Next, the operation of the buffer of this embodiment constructed as above will be described with reference to FIG. As shown in FIG. 2, the input signal I is low before time t1,
The output signals of the inverters 2A and 2B both become high, whereby the drive signal from the AND gate 5 is low, and the Schmitt inverter 6 is in the disabled state. In this state, the N-type transistor 4
Is turned on, and the level of the output signal O at the output terminal 8 is low.

At time t1, the input signal I begins to change from low to high. When the level of the input signal I exceeds the threshold value VTL of the inverter 2B at time t2, this inverter 2
The output signal of B turns to low, and both the P-type transistor 3 and the N-type transistor 4 are turned off. On the other hand, one input of the AND gate 5 is high due to the output signal from the inverter 2A, and the other input is low due to the output signal from the inverter 2B, so that the AND gate 5 sends the drive signal to the Schmitt inverter 6. In this state, the level of the input signal I exceeds the threshold VTL of the inverter 2B and the inverter 2A
Until the threshold value VTH is reached. During this period, the Schmitt inverter 6 is in the enabled state, and the level of the output signal O at the output terminal 8 is t10-t as shown in FIG.
2 After a delay, it rises from low and exceeds the midpoint potential (1/2 VDD).

When the level of the input signal I exceeds the threshold value VTH of the inverter 2A, the output signals of the inverters 2A and 2B both become low, whereby the Schmitt inverter 6 is disabled. Instead, the P-type transistor 3 is turned on, and the level of the output signal O at the output terminal 8 remains high.

At time t4, the level of the input signal I begins to change from high to low. When the level of the input signal I falls below the threshold value VTH at time t5, the output signal of the inverter 2A becomes high, both transistors 3 and 4 are turned off, and instead the drive signal is sent from the AND gate 5 to the Schmitt inverter 6. The lever Schmitt inverter 6 is enabled, and the level of the output signal O at the output terminal 8 falls from high with a delay of t20-t5 to fall below the midpoint potential (1/2 VDD). After that, the enable state of the Schmitt inverter 6 continues until the level of the input signal I falls below the threshold value VTL of the inverter 2B.

When the level of the input signal I is lower than the threshold value VTL of the inverter 2B, all the output signals of the inverter 2B become high, thereby disabling the Schmitt inverter 6, but the N-type transistor 4 is used instead. When turned on, the level of the output signal O at the output terminal 8 remains low.

In this way, the level of the input signal I is detected based on the threshold values VTH and VTL of the inverter 2A or the inverter 2B, and the output signal O is sent out. It is possible to propagate with a delay time.

The present invention is not limited to the above-mentioned embodiments, but various modifications can be made within the scope of the invention.

[0020]

According to the present invention described in detail above, since it has the above-mentioned configuration, it is possible to provide a buffer capable of propagating a signal whose state transitions slowly with a short delay time.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a buffer that is an embodiment of the present invention.

FIG. 2 is a waveform diagram showing a state of time change of an input signal and an output signal of the buffer of this embodiment.

FIG. 3 is a circuit diagram of a conventional buffer.

FIG. 4 is a waveform diagram showing a time change state of an input signal and an output signal of a conventional buffer.

[Description of Reference Signs] 1 buffer 2A inverter 2B inverter 3 P-type transistor 4 N-type transistor 5 AND gate 6 Schmidt inverter 9 output circuit

Claims (1)

[Claims] 1. A buffer which outputs an output signal based on an input signal which changes within a range of a power supply potential and a ground potential and takes a binary value of high and low, in which the output potential is lower than a midpoint potential of the power supply potential and the ground potential. A high threshold circuit that sets a high threshold, a low threshold circuit that sets a threshold lower than the midpoint potential, and when the input signal is within the range of the threshold of the low threshold circuit and the threshold of the high threshold circuit. A drive circuit that outputs a drive signal, and outputs the output signal based on the drive signal from the drive circuit, and when the input signal rises above the threshold of the high threshold circuit and falls below the threshold of the low threshold circuit. And an output circuit which sends out the output signal when the buffer is operated.