JPH05243913A - Arithmetic and logical operating element - Google Patents

Abstract

PURPOSE:To provide an arithmetic and logical operating element capable of reducing the number of machine cycles. CONSTITUTION:The absolute value of the result of prescribed arithmetic operation is obtained through one machine cycle by constituting an arithmetic and logical operating element ALU 2 by including an arithmetic circuit 12 for executing the arithmetic processing of input data and an absolute value arithmetic circuit 13 for obtaining the absolute value of the output of the arithmetic circuit 12, and dispensing with processing about the arithmetic operation of the absolute value by the arithmetic circuit 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic logic operation unit controlled based on information obtained by decoding an instruction, and further to an arithmetic logic operation unit integrated into a semiconductor integrated circuit, for example, ISDN (Integrated Service).
The present invention relates to a technique effectively applied to an echo cancellation LSI for s Digital Network).

[0002]

2. Description of the Related Art An adaptive filter such as a transversal filter is a filter capable of adaptively changing its characteristics with respect to a change with time of an input signal. That is, the output signal for multiplying the tap coefficient by the input signal and adding the values in units of multiple taps to obtain the filter output, and the difference between the filter output and the signal from the target system to which the filter output should respond And an update operation such as a product-sum operation for updating the tap coefficient based on the error signal obtained as described above, and the characteristic is changed in real time by temporally rewriting the tap coefficient by the update operation. When such an adaptive filter is configured by a digital signal processor (hereinafter also simply referred to as DSP), the update of the tap coefficient is
This can be realized by an integral process of adding the update amount to the tap coefficient read from the memory and writing this at the same address in the memory.

The above-mentioned DSP has a multiplier as hardware together with an arithmetic and logic unit, and improves real-time digital signal processing capability by improving the efficiency of product-sum calculation. As such a unit, for example, Nikkei BP Issued Data Pro Microprocessor (MC4-303-
811 to 818, December 1988)
There is "TMS320C25".

[0004]

An absolute value operation function is one of the functions of the arithmetic logic operation unit. This absolute value operation is performed according to the instructions for the absolute value operation, but simply took one machine cycle to perform such an operation. That is, when A and B are used as input data, in order to obtain the absolute value of A + B, the operation of A + B is performed in the first one machine cycle, and the absolute value of the operation result is obtained in the next one machine cycle. , After all, A +
Two machine cycles are required to determine the absolute value of B. The same applies to the arithmetic and logic unit included in a microcomputer or the like.

The inventor of the present invention has developed an LSI that realizes an adaptive filter.
As one of the methods, we examined low power consumption of ISDN LSI, and found that, in the process, it took 2 machine cycles for processing such as absolute value calculation to hinder low power consumption. That is, the ISDN L for connecting the subscriber side terminal to the communication line from the exchange.
Since SI is fed from an exchange, there is a strong demand for low power consumption, and the clock frequency is lowered to reduce the power consumption of the LSI, so that the processing speed per unit time does not decrease due to the decrease in operating speed. Even if an attempt is made to reduce the number of machine cycles in a series of processes, it will be difficult if the absolute value calculation takes two machine cycles. The echo canceller, which cancels the echo component that wraps around from the transmitting side to the receiving side through the balancing network circuit, must deal with the uncertain factor of impedance mismatch with the communication line that is arbitrarily connected. Therefore, high processing capacity per unit time is required, and power consumption increases accordingly. Therefore, it has been found by the inventor of the present invention that there is an urgent need to guarantee the processing capacity per unit time and reduce the power consumption, especially in the echo canceller.

An object of the present invention is to provide an arithmetic logic operation unit which can reduce the number of machine cycles.
Another object of the present invention is to provide an arithmetic and logic operation unit capable of ensuring processing power per unit time and achieving low power consumption.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, an arithmetic logic operation unit including an arithmetic circuit for performing a logical operation of input data and an absolute value arithmetic circuit arranged at a subsequent stage of the arithmetic circuit to obtain an absolute value of the output of the arithmetic circuit is provided. It is what constitutes. At this time,
The absolute value arithmetic circuit is for inverting means for inverting the logical state of the output of the arithmetic circuit according to the sign bit included in the output of the arithmetic circuit, and for converting the output of the inverting means into a two's complement. And a conversion means of

[0010]

According to the above-mentioned means, the absolute value of the output of the arithmetic circuit is calculated by the absolute value arithmetic circuit arranged in the subsequent stage of the arithmetic circuit. This is unnecessary, and this acts so as to obtain the absolute value of the predetermined calculation result in one machine cycle, and further guarantees the processing capacity per unit time and achieves low power consumption.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 shows an example of an applied model for estimating the output of a target system by an adaptive filter. The adaptive filter 1 receives the difference between the output D of the target system 2 and the adaptive filter output Y as an error signal ER, and functions to minimize the error signal ER, that is, to make a response equivalent to that of the target system 2. To do. When the output of the object system 2 is an echo of the input signal in this model, the adaptive filter 1 functions as an echo canceller.

FIG. 4 shows an example of an arithmetic unit for forming the adaptive filter. In the figure, DRM is a data memory for holding a predetermined tap coefficient corresponding to an address, and SRM is a symbol memory such as a shift register functioning as the delay element. This arithmetic unit is dedicated as an adaptive filter, and an output arithmetic processing system 5 and an update arithmetic processing system 6 of the filter are separately provided.

The output calculation processing system 5 of the filter comprises an input register RB, RS1, a selector SEL, and a multiplier MULT.
1, an output register RG, an arithmetic logic unit ALU1, and an accumulator ACC. The input signals read from the symbol memory SRM are registered in the registers RS0 and RS.
The selector SEL gives the multiplier MULT1 through 1 and the tap coefficient read from the data memory DRM is given from the input register RB to the multiplier MULT1. The multiplier MULT1 multiplies those inputs and outputs the multiplication result from the output register RG to the arithmetic logic unit ALU1.
Give to. The arithmetic and logic unit ALU1 is an accumulator A.
The output value of the register RG is added to the added value held by the CC, and the result is returned to the accumulator ACC again. The value held in the accumulator ACC when the outputs of all the taps for one sample signal are added becomes the filter output.

The update operation processing system 6 includes a register ESR, a multiplier MULT2, a shifter SHIFT, and a register RDL.
T, arithmetic logic unit ALU2, and data memory DRM
It is configured to include. An error signal is held in the register ESR, the error signal and the input signal supplied from the register RS0 are multiplied by the multiplier MULT2, and the multiplication result is shifted by a predetermined bit by the shifter SHIFT and held in the register RDLT. It Arithmetic logic operation unit ALU2
Adds the tap coefficient update amount held in the register RDLT and the tap coefficient supplied from the data memory DRM. The updated tap coefficient is stored in the data memory DRM.
It is written back to the same address of.

Since the arithmetic logic unit ALU2 and the data memory DRM rewrite the value obtained by adding the update amount to the tap coefficient read from the data memory DRM to the same address of the data memory DRM and sequentially hold it. The integrator circuit is constructed so that its function is clear. At this time, the data transfer path for giving the tap coefficient read from the data memory DRM to the arithmetic and logic unit ALU2 is constituted by the dedicated bus 10. Further, the data memory DRAM is a so-called read / write operation in which a read and write operation is performed in one machine cycle that defines the operation of the arithmetic unit of FIG.
It is operated in the modified write format. Private bus 10
Is not shared by other circuit modules and is locally located,
Moreover, since the length of the bus signal line is set to the shortest, the undesired load component is extremely small, the tap coefficient can be transmitted to the arithmetic logic unit ALU2 at high speed, and the data can be transmitted without difficulty in timing. The memory DRM can be read / modify / write.

The tap coefficient read from the data memory DRM is used for the filter output operation in the common internal bus 11.
Although it is also supplied to the register RB via the above, if the dedicated bus 10 is directly connected to the common internal bus 11 at this time, the transmission of the tap coefficient on the dedicated bus 10 may be delayed, A bus driver B that also functions as a buffer between the common internal bus 11 and the dedicated bus 10.
DRV should be placed.

The tap coefficient read from the data memory DRM is used for the common internal bus 11 for the filter output calculation.
It is also supplied to the register RB via. Common internal bus 1
Although not particularly limited, the tap coefficient supplied to the register RB through 1 is 18 bits. On the other hand, the data memory DRM is not particularly limited, but each tap coefficient is set to 2
Hold in 8-bit configuration. When the tap coefficient is read from the data memory DRM, all 28 bits of the tap coefficient are used for the update operation of the tap coefficient, and the upper 18 bits thereof are used for the filter output operation. This is because the update amount is given a convergence factor in the update calculation of the tap coefficient, and the time constant of the transfer function is made small (the response sensitivity is made small).
This is because the response operation is stabilized.

FIG. 1 shows a configuration example of the arithmetic logic operation unit ALU2.

As shown in FIG. 1, the arithmetic logic operation unit ALU2 is arranged in the arithmetic circuit 12 for performing the arithmetic operation for updating the tap coefficient as described above, and is arranged in the subsequent stage of the arithmetic circuit 12 and the arithmetic circuit concerned. And an absolute value calculation circuit 13 for calculating the absolute value of the output of. The absolute value operation circuit 13 is not particularly limited, but serves as an inverting means for inverting the logical state of the output of the operation circuit 12 according to the sign bit (usually the most significant bit) included in the output Aout of the operation circuit 12. Inverter circuit (INV) 14 and a carry adder (CADD) 15 as a conversion means for converting the output of the inverter circuit 14 into a two's complement. Ain,
Bin is input data to the logical operation unit 12, and the logical operation unit 12 uses the input data Ain and B as input data.
In addition processing and the like can be performed. When absolute value acquisition is instructed by asserting the control signal ABSON output from the decoder (not shown), the absolute value operation circuit 13 obtains the absolute value of the output of the operation circuit 12. On the other hand, when the control signal ABSON is negated to the low level, absolute value acquisition is not performed, and the output Aout of the arithmetic circuit 12 remains the same logic state and the output ALUOU of the arithmetic logic operation unit ALU2.
T.

That is, when the absolute value acquisition is instructed by asserting the control signal ABSON,
In the inverter circuit 13, the logic state of the output of the arithmetic circuit 12 is inverted, and in the carry adder 15 in the subsequent stage, when the sign bit output from the inverter circuit 14 is low level, However, if the sign bit is at the high level, the data representation is converted from 1's complement to 2's complement by adding 1 (carry). When the control signal ABSON is asserted, the absolute value of the output of the arithmetic circuit 12 is obtained by such an arithmetic operation.

FIG. 2 shows a configuration example of the carry adder 15.

The carry adder 15 has a plurality of addition blocks 15-1, 15-2, ... As shown in FIG.
…,including. Those addition blocks 15-1, 15-2,
, Are all of the same configuration, and as one of them is representatively shown, a NAND gate 151 for obtaining a NAND logic of the carry signal C0 indicating the carry and the input data S0, and the carry signal C0. An OR gate 152 for obtaining an OR logic with the input data S0, a NAND gate 153 for obtaining a NAND logic between the output of the OR gate 152 and the output of the NAND gate 151, and an inverter 154 for inverting the output of the NAND gate 153.
And the addition output S0 'of the carry signal C0 and the input data S0 is obtained by
NAND gate 160 for obtaining the NAND logic between the output of the AND gate and the input data S1, an OR gate 158 for obtaining the OR logic of the output of the NAND gate 151 and the input data S1, and a NAND logic of the output of the OR gate 158 and the output of the NAND gate 160. AND gate 159 which obtains the sum of the output of NAND gate 151 and the input data S1 to obtain an addition output S1 ', and further the input data S0 and S1.
A carry output for carry by a NAND gate 155 for obtaining a NAND logic of the following, an inverter 156 arranged at the subsequent stage thereof, and an AND gate 157 for obtaining an AND logic of the output of this inverter 156 and the carry signal C0. C1 can be obtained. The carry output C1 is used as a carry input of an addition block 15-2 which is an upper block of the addition block 15-1 and carries a carry when it is at a high level.

The input data S0, S1, S2, S3, ...
, Is the output of the inverter circuit 14, and S
0, S1 ', S2', S3 ', ... Are output ALUOUT of the arithmetic and logic unit ALU2.

FIG. 5 shows an echo cancellation type waveform equalization LSI (hereinafter also simply referred to as an echo cancellation LSI) as an ISDN-compatible LSI to which the arithmetic circuit shown in FIG. 4 is applied. This echo cancellation LSI 20
Is a basic rate of 2B + D using a telephone line.
(2 audio channels of 64 Kbps and 16 Kbps
This is an LSI for performing full-duplex digital data transmission (data channel 1 channel) of transmission data, output of transmission data, identification of reception data, and cancellation (echo cancellation) of wraparound of transmission data to the receiving unit. It is performed by digital signal processing through transition control. Although not particularly limited, this echo cancellation LSI is 80 KHz
The cycle defined by the frequency is set as a processing period (unit interval) for one data, and the transition state is detected, the state is set, and the digital signal is processed in each interval.

The echo canceling LSI 20 includes an analog front end unit 21, a digital signal processing unit 22, an event information register file 23, a protocol control unit 24, a timer counter
A unit 25, a timing generator 26, an analog phase locked loop circuit 27, a U-point interface circuit 28, and an S-point interface circuit 29, and one semiconductor such as a silicon substrate by a known Bi-CMOS process, for example. Formed on a substrate.

The digital signal processing unit 22 is composed of an instruction control circuit and an arithmetic circuit, and the arithmetic circuit shown in FIG. 4 is applied to the arithmetic circuit. The command controller is the event information
By referring to the register file 23, the microprogram is executed according to a predetermined procedure, and the arithmetic circuit is made to function as an adaptive filter or the like to realize echo cancellation or the like. The analog front end unit 21 performs A / D conversion of a transmission signal and D / A conversion of a reception signal. The U-point interface circuit 28 is connected to the exchange side via a hybrid transformer or a balancing network circuit (not shown). The event information register file 23 is a register for holding transition states generated in the digital signal processing unit 22 and the protocol control unit 24.
Detects the transition state set in it and determines the operation. The protocol control unit 24 performs protocol processing such as frame processing, scrambling, and synchronization. The timer / counter unit 25 is used for state transition control and the like, and the timing generator 26 generates various operation clock signals for the echo cancellation LSI. Analog Phase Locked Loop Circuit 27
Supplies the timing generator 26 with the system clock signal supplied from the outside. The S-point interface circuit 29 interfaces with the subscriber side.

FIG. 6 shows the echo cancellation LSI 20.
An example is shown in the case of functioning as an echo canceller. In the figure, reference numeral 40 is a balancing network circuit. The transmission data output from the protocol control unit 24 is D / A converted and given to the balancing network circuit 40, and the received analog signal input to the balancing network circuit 40 is A / D converted into a digital signal. The signal is supplied to the digital signal processing unit 22.
The echo cancellation LSI 20 can perform transmission and reception in parallel with full duplex. At this time, the balancing network circuit 40 includes direct resistors R3 and R4 having a resistance voltage division ratio equal to the resistance voltage division ratio obtained by the impedance R1 and the resistance R2 of the transformer 42. Is subtracted from the voltage component applied to the transformer 42 from the line 41 to remove the voltage component of the transmission analog signal. That is, a part of the signal transmitted through the D / A conversion is prevented from sneaking into the A / D conversion side via the transformer 42. In the balancing network circuit 40, for example, the resistance division ratio is determined according to the standard that the impedance of the line 41 is set to a constant value such as 135Ω everywhere. Therefore, the impedance of the line actually has an error, and the state of the line also changes with time,
In addition, since it is impossible to predict what kind of state the line is connected to, the echo canceller 43 is required in order to reliably remove the echo component sneaking around from the transmitting side to the receiving side. The echo canceller 43 realizes an adaptive filter algorithm, and the echo component D is canceled by the signal Y.

FIG. 7 shows the echo cancellation LSI 20.
An outline of a digital subscriber transmission system utilizing the above is shown. In the figure, 31 is an exchange station, 32 is an exchange, and 33
Is an office channel unit for connecting the exchange 32 and the line U, 34 is a subscriber station, 30 is a subscriber station 3
4 is a digital service unit for connecting 4 to the line U. The echo cancellation LSI 20 is arranged in each of the subscriber station 34 and the exchange station 31. When the transmission device including the echo cancellation LSI 20 on the subscriber side, for example, the digital service unit 30 must be entirely operated by the power supply from the exchange 31, the power supply is performed, for example, in the form of superimposing DC on the transmission line U. .. Therefore, the distribution of power that can be consumed by the echo cancellation LSI 20 is limited. At this time, echo cancellation for canceling the echo component that wraps around from the transmission side to the reception side due to impedance mismatch between the balancing network circuit and the line is the impedance between the communication line that is arbitrarily connected.・ Because it is necessary to deal with the uncertain factor of mismatching and to realize it with an adaptive filter with a relatively large number of taps, particularly high processing capacity per unit time is required, and in response to this It is expected that power consumption will increase.

On the other hand, the arithmetic circuit of the digital signal processing unit 22 for realizing the adaptive filter for echo cancellation performs the arithmetic operation of the input data and the absolute value acquisition of the arithmetic result as described above. Since the arithmetic logic unit ALU2 that can be used in the machine cycle is provided, even if the operating clock frequency of the LSI is lowered to lower the operating speed, the processing capacity per unit time at that time can be prevented from being lowered. .. Therefore, in the digital signal processing unit 22 for realizing the adaptive filter for echo cancellation, which is required to have a high processing capacity per unit time, and the power consumption is expected to increase accordingly. By lowering the operating clock frequency, it is possible to guarantee the processing capacity per unit time and achieve low power consumption.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

In the above description, the invention mainly made by the present inventor is applied to the echo canceling LSI for ISDN which is the field of use which is the background of the invention, but the present invention is not limited thereto. Instead, it can be widely applied to various semiconductor integrated circuits such as an arithmetic circuit for performing processing such as voice compression, voice synthesis, wireless transmission, and image enhancement, an adaptive filter, and an LSI for realizing this.

The present invention can be applied on condition that a predetermined arithmetic processing is executed based on at least information obtained by decoding an instruction.

[0033]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the absolute value of the output of the arithmetic circuit is calculated by the absolute value arithmetic circuit arranged in the subsequent stage of the arithmetic circuit, whereby the processing for the absolute value calculation in the arithmetic circuit becomes unnecessary. The absolute value of the predetermined calculation result can be obtained in one machine cycle, and the processing capacity per unit time can be guaranteed to reduce the power consumption.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an arithmetic logic unit according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of a main part of the arithmetic logic unit.

FIG. 3 is an explanatory diagram of an example of an applied model for estimating an output of a target system by an adaptive filter.

FIG. 4 is a configuration block diagram of an adaptive filter configuration operation circuit to which the arithmetic logic operation unit is applied.

FIG. 5 is a configuration block diagram of an echo cancellation LSI to which the adaptive filter configuration arithmetic circuit is applied.

FIG. 6 is a configuration block diagram when the echo canceling LSI is caused to function as an echo canceller.

FIG. 7 is a schematic explanatory diagram of a digital subscriber transmission system using the echo cancellation LSI.

[Description of symbols] 1 Adaptive filter 2 Target system D Target system output Y Filter output ER Error signal 5 Output calculation processing system 6 Update calculation processing system MULT1 Multiplier RG register ALU1 Arithmetic logic calculator ACC Accumulator MULT2 Multiplier SHIFT shifter RDLT register ALU2 Arithmetic logic operation unit DRM data memory 10 Dedicated bus 11 Common internal bus 12 Operation circuit 13 Absolute value operation circuit 14 Inverter circuit 15 Carry adder 20 Echo cancellation LSI 22 Digital signal processing unit 43 Echo canceller

Claims (3)

[Claims] 1. An arithmetic logic operation unit controlled on the basis of information obtained by decoding an instruction, comprising an arithmetic circuit for performing arithmetic processing of input data, and an arithmetic circuit arranged after the arithmetic circuit. An arithmetic logic operation unit in which an absolute value operation circuit for obtaining an absolute value of the output of the operation circuit is formed on one semiconductor substrate. 2. The absolute value arithmetic circuit includes an inverting means for inverting the logical state of the output of the arithmetic circuit according to a sign bit included in the output of the arithmetic circuit, and an output of the inverting means. The arithmetic logic unit according to claim 1, further comprising conversion means for converting into a complement. 3. The arithmetic logic operation unit according to claim 1, which is an arithmetic circuit for adaptive filter configuration included in an echo canceller for canceling an echo component that wraps around from a transmission side to a reception side.