JPH05143187A - Semiconductor integrated circuit and data processing processor - Google Patents

Abstract

PURPOSE:To prevent analog characteristics from being deteriorated due to a digital noise in a digital/analog mixed type semiconductor integrated circuit. CONSTITUTION:In the digital/analog mixed LSI including an analog circuit 2 and a digital circuit 3, the circuit 2 includes a circuit for sampling information to be processed by the circuit 2 in a capacitor 5 in accordance with the operation timing of a switch 4. A clock signal generating means 6 forms an operation reference clock signal for stopping the change of an operation reference clock signal (b) outputted from the circuit 3 in a prescribed period T including the opening timing of the switch 4, i.e., the trailing timing of a clock signal (a). Consequently the generation of a trouble deteriorating the analog characteristics of the circuit 2 by a digital noise through the connecting capacitor of a semiconductor substrate 1 can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog mixed type semiconductor integrated circuit in which a digital circuit and an analog circuit are formed on the same semiconductor substrate, and a data processor which can be adopted as a digital circuit of this semiconductor integrated circuit. The present invention relates to a technique effectively applied to a digital / analog mixed semiconductor integrated circuit incorporated in a device in the field of communication or signal processing, such as a codec, a modem, an echo canceller, mobile radio, and image processing.

[0002]

2. Description of the Related Art A semiconductor integrated circuit in which an analog circuit and a digital circuit are mixed on one semiconductor substrate is provided by a CMOS or Bi-CMOS process.
For example, with a digital signal processor applied to digital signal processing such as filtering, equalization, echo removal, signal characteristic parameter extraction, image enhancement,
A digital / analog mixed LSI in which an analog / digital (A / D) conversion circuit that converts an analog signal into a corresponding digital signal and a digital / analog (D / A) conversion circuit that performs the opposite operation are integrated on-chip It is used in fields such as recognition, modem, and ISDN. As an example of a document describing such a digital / analog mixed LSI, there is JP-A-63-217706.

Further, a conventional data processor such as a digital signal processor which is micro-program controlled has an architecture in which micro-instructions are read one by one from the control memory and executed in sequence. Even if it supports so-called pipeline processing, it is the same. Incidentally, as an example of the document describing the digital signal processing, CQ publishing issue "transistor technology" Feb. 1989 P.I. 395
~ P. There is 401.

[0004]

However, when the analog circuit and the digital circuit mixed in the same semiconductor substrate operate synchronously, the characteristics of the analog circuit may be deteriorated by the digital noise generated by the operation of the digital circuit. The present inventor has found that. That is,
When a digital circuit operates, a relatively large current flows in the power supply line according to its operating state, the power supply voltage fluctuates, and a junction capacitance such as that formed between the diffusion layer of the transistor and the semiconductor substrate of the transistor is generated. It is charged / discharged according to the operation, which causes noise through the semiconductor substrate. Such noise is also transmitted to analog circuits sharing the semiconductor substrate. For example, A using a switched capacitor integration circuit or a plurality of appropriately weighted capacitor arrays in the analog circuit
When a / D conversion circuit or a local D / A conversion circuit is included, if a potential variation due to the influence of digital noise is given to the storage node of the capacitor through a junction capacitance or the like during sampling operation to the capacitor performed by the operation timing of the switch, We have found that an error occurs in the amount of charge to be sampled and the operation accuracy of the analog circuit is reduced. The characteristic deterioration of the analog circuit due to the digital noise is not limited to this, and it is considered that the digital noise may also be caused by the power supply fluctuation or the crosstalk with the power supply line whose level changes.

In particular, semiconductor integrated circuits tend to increase power consumption due to the demand for higher integration and higher speed operation due to advances in their manufacturing techniques, which causes a further increase in digital noise, and analog circuits. Higher precision is required with the expansion of its application field, and it is expected that the deterioration of the characteristics of the analog circuit due to the digital noise in the digital / analog mixed LSI will become a serious problem.

Therefore, the present inventor studied to operate the digital circuit and the analog circuit in a time division manner so that the digital noise does not affect the analog circuit. However, the analog circuits mixed in the same semiconductor substrate are considered. And the digital circuit must operate synchronously. At this time,
The operating speed of an analog circuit such as a D / D conversion circuit is often determined by the operating speed of the target system that it processes, performance such as bit precision, and the degree of freedom with respect to the operating speed of the analog circuit in relation to the processing system. The present inventor has found that it is desirable to stop the operation of the digital circuit when the analog circuit is operating because it becomes relatively low. However, architectures that require at least one machine cycle to execute one microinstruction, such as a conventional data processor such as a digital signal processor, are designed to stop the operation of the digital circuit during the operation of the analog circuit. We could not get enough time, but if we tried to raise the operating clock frequency of the digital signal processor, the power consumption would increase, and intensive power supply from the exchange and battery It has been found that a new problem arises in that it cannot be applied to an LSI that has a limited power distribution that can be consumed, such as power supply, and that digital noise is further increased. Therefore, the present inventor found out that it is necessary to reduce the number of machine cycles for performing a predetermined process to obtain such a margin.

An object of the present invention is to prevent deterioration of analog characteristics due to digital noise in a digital / analog mixed type semiconductor integrated circuit. Further, in order to prevent deterioration of analog characteristics due to digital noise, it is still another object to realize a time margin for stopping the operation of the digital circuit at the time of operating the analog circuit by reducing the number of machine cycles of predetermined processing. And Another object of the present invention is to reduce the number of machine cycles required for performing a predetermined process in the data processor.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, in a semiconductor integrated circuit in which an analog circuit and a digital circuit are mixedly mounted on one semiconductor substrate, a means for generating a timing for stopping the operation of the digital circuit when the analog circuit performs a predetermined operation is provided.

For example, an A / D conversion circuit using a switched capacitor integration circuit or a capacitor array and a local D
When the analog circuit includes a circuit for sampling information to be processed in the capacitor according to the operation timing of the switch, such as an A / A conversion circuit, the operation of the digital circuit is stopped only for a predetermined period including the sampling operation.

As means for generating such timing, the operation reference clock signal for stopping the change of the operation reference clock signal of the digital circuit during a predetermined period including the change timing of the clock signal for controlling the sampling switch. Clock signal generating means for forming the signal may be employed.

When the operation of the digital circuit is stopped during the operation of the analog circuit, the operation speed of the analog circuit is determined uniquely or with little freedom depending on the relationship with the operation speed of the target system to be processed and the bit accuracy. In view of the nature described above, it is desirable to obtain the time margin for stopping the operation of the digital circuit during the operation of the analog circuit by improving the processing capability of the digital circuit or reducing the number of machine cycles for a series of processing. May employ instruction control means for executing a non-operation instruction in parallel with the execution of the operation instruction in the digital circuit such as a digital signal processor. For example, the arithmetic instruction is an instruction for arithmetically operating predetermined data using a multiplier and an arithmetic unit. Further, the non-calculation instruction is different from an instruction for calculating predetermined data using a multiplier or a calculator, and the operation procedure of the digital circuit is based on the transition state of processing inside and outside the semiconductor integrated circuit mounting the digital circuit. Is a command for detecting and setting the transition state.

When the arithmetic instruction and the non-arithmetic instruction are held in a single control memory, the non-arithmetic instruction can be executed in parallel with the execution of the arithmetic instruction while reading the non-arithmetic instruction from the control memory. The instruction control means holds the specific operation instruction read from the control memory in a register or the like for a plurality of operation cycle periods, and repeatedly decodes and executes the operation instruction by the first instruction decoder in parallel,
It is advisable to adopt a configuration in which the non-operation instruction is read from the control memory and is executed while being decoded by the second instruction decoder.

Further, the instruction control means is unique to each control memory when the control memory for separating the memory space from each other is arranged in each of the control system for the operation instruction and the control system for the non-operation instruction. A program counter is provided, and the operation of the program counter of the other control system is synchronized in accordance with the instruction execution state in either the control system of the arithmetic instruction or the control system of the non-arithmetic instruction to control both control systems. It is possible to configure by providing a control unit that causes the instruction execution operation in 1) to operate in parallel at a desired timing.

Due to the nature of executing non-operation instructions in parallel with the processing of repeatedly executing a specific operation instruction, the instruction control means must repeatedly execute the same operation like the adaptive filter processing. Suitable for echo canceller.

The configuration of the instruction control means which enables parallel processing of arithmetic instructions and non-arithmetic instructions can be applied independently to the data processor.

[0018]

According to the above means, the operation of the digital circuit is stopped at the time of the predetermined operation of the analog circuit mixedly mounted on one semiconductor substrate, thereby preventing the analog characteristic deterioration or the operational accuracy deterioration of the analog circuit due to the digital noise. To do. For example, an A / D conversion circuit using a switched capacitor integration circuit or a capacitor array or a local D / A
When the analog circuit such as the conversion circuit samples the information to be processed in the capacitor according to the operation timing of the switch, the digital circuit is not operated, so the level of the storage node of the capacitor causes the potential fluctuation due to the digital noise through the junction capacitance. Instead, it operates by accumulating information with the desired accuracy.

Since the operating speed of the analog circuit is uniquely determined with little relation to the operating speed of the target system to be processed, bit precision, etc., there is no degree of freedom. It is necessary for the digital circuit side to deal with a time or processing margin that can stop the operation. At this time, in a digital circuit such as a digital signal processor, executing a non-arithmetic instruction in parallel with the execution of the arithmetic instruction realizes a reduction in the number of machine cycles required for certain processing in the digital circuit, To obtain a time or capacity margin for stopping the operation of the digital circuit when the analog circuit operates. Furthermore, reducing the number of machine cycles for a series of processes by parallelizing arithmetic and non-arithmetic processing is not limited to the digital / analog mixed semiconductor integrated circuit, and naturally improves the processing capacity of a data processor such as a digital signal processor. Contribute.

Such measures on the digital circuit side are as follows.
Since it does not need to raise the operating frequency of the digital circuit, it works so as to suppress the increase in power consumption and the increase in digital noise due to this.

A specific operation instruction read from the control memory is repeatedly decoded and executed by the first instruction decoder while being held in a register or the like for a plurality of operation cycle periods. By reading the arithmetic instruction and executing it while decoding it by the second instruction decoder, it is possible to execute the arithmetic instruction and the non-arithmetic instruction in parallel even when the arithmetic instruction and the non-arithmetic instruction are held in a single control memory. to enable.

In order to operate both control systems in parallel by controlling the state of the program counter of the other control system according to the instruction execution state of one of the control system for arithmetic instructions or the control system for non-arithmetic instructions, Even when the control system of the arithmetic instruction and the control system of the non-arithmetic instruction are controlled using their own control memories, the arithmetic instruction and the non-arithmetic instruction can be executed in parallel.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a principle embodiment of a digital / analog mixed LSI according to the present invention. In the digital / analog mixed LSI shown in the figure, an analog circuit 2, a digital circuit 3 and a clock signal generating means 6 are mounted on one semiconductor substrate 1. The digital circuit 3 is not particularly limited, but may be a digital signal
A data processing processor such as a processor is included. Also,
The analog circuit 2 includes, but is not particularly limited to, an A / D conversion circuit using a switched capacitor integration circuit or a capacitor array, a local D / A conversion circuit, and the like. In the figure, a part of a circuit for sampling the information to be processed by the analog circuit 2 in the capacitor 5 in accordance with the operation timing of the switch 4 is representatively shown. For example, if the clock signal for controlling the switch 4 is a and the operation reference clock signal of the digital circuit 3 is b, the clock signal a is inverted to the low level and the switch 4 is opened. At that time, the capacitor 5 is sampled. The amount of charge held is determined by the voltage applied to the storage electrode of the capacitor 5 when the switch 4 is about to open. The operation of the digital circuit 3 is stopped during a predetermined operation period of the analog circuit 2 including such a fall timing of the clock signal a. That is, the clock signal generating means 6 for forming the operation reference clock signal is provided so as to stop the change of the operation reference clock signal b of the digital circuit 3 in the predetermined period T including the falling timing of the clock signal a. Keep it. As a result, even if the level of the storage electrode of the capacitor 5 fluctuates through the junction capacitance of the semiconductor substrate 1 due to the digital noise generated in synchronization with the timing when the operation reference clock signal b of the digital circuit 3 changes, such level fluctuations will occur. Since the sampling timing of the capacitor 5 always deviates from the sampling timing, it is possible to completely prevent the situation where digital noise deteriorates the analog characteristics of the analog circuit 2.

FIG. 2 shows still another embodiment of the digital / analog LSI according to the present invention. The digital / analog mixed LSI shown in FIG.
The SI 10 includes an analog front end unit 11 as an example of an analog circuit, a digital signal processor 12 and the like mixed in one semiconductor substrate. The overall structure and function of the echo canceling LSI 10 will be described later, but the analog front end unit 11 includes an A / D converter and a D
/ A converter is included.

FIG. 3 shows a schematic configuration of an oversampling type A / D converter as an example of the A / D converter. The oversampling A / D converter integrates the difference voltage between the analog input voltage Ain and the output voltage of the local D / A converter 20 by the analog integrator 21 (error integration), and the integrated result is quantized by the comparator 22. Then, the result is further integrated by the digital integrator 23. The output of the digital integrator 23 is fed back to the local D / A converter 20 again. This series of feedback loops includes a local D / A converter 2
A feedback system is formed so that the output of 0 follows the analog input voltage Ain. Therefore, the output of the digital integrator 23 is the oversampling A / D.
It is taken as the output of the converter.

FIG. 4 shows a detailed example of the local D / A converter 20 and the analog integrator 21. The circuit shown in the figure is a circuit using a switched capacitor, and includes S1 to S5 and S61, S62, S71, S7.
2, S81, S82, S91 and S92 are switches such as CMOS transfer gates, CI and CS are capacitors on the analog integrator 21 side, C, 2C, 4C and 8C.
Is a capacitor on the side of the local D / A converter 20 weighted by a power of 2. The switches S2 and S5 on the analog integrator 21 side are switch-controlled by a clock signal φ1, and the switches S1, S3 and S4 are switch-controlled by a clock signal φ2. Both clock signals φ1 and φ2 are non-overlapping two-phase clock signals as shown in FIG. The clock signal φ1 defines the precharge operation according to the high level period, and controls the switches S2 and S5 to be in the ON state. At this time, the local D / A converter 20 turns on one of the left and right switches coupled to the lower electrodes of the capacitors C, 2C, 4C, and 8C according to the sign of the input digital signal to turn on the reference potential Vref or the ground. Take in the potential GND. The operation timing of this switch is synchronized with the clock signal φ1. Next, the integration operation is defined during the high level period of the clock signal φ2, and the switches S1, S3, S4 of the analog integrator 21 are defined.
Is turned on. At this time, in the local D / A converter 20, the states of the switches coupled to the lower electrodes of the capacitors C, 2C, 4C and 8C are inverted. For example, when the input digital signal is (1010), the switches S61, S72, S81, S92 are used during the precharge period.
Is on, switches S62, S71, S82, S91
Is off, the on / off state of the switch is reversed during the integration operation. In this way the local D
The output voltage of the / A converter 20 is determined, and the voltage difference from the analog input voltage Ain is integrated.

In the circuit shown in FIG. 4, the influence of noise and crosstalk through the semiconductor substrate is most affected by the operation accuracy of the analog circuit at the end of the precharge and integration operations, that is, the switches S1 to S5 and S6.
1, S62, S71, S72, S81, S82, S9
1 and S92 are turned off and the sampling charge amount of the capacitor is determined. According to the description of FIG. 4 and FIG. 5, this timing is the clock signal φ.
It is the timing when 1 and φ2 are inverted from the high level to the low level. In the echo cancellation LSI shown in FIG. 2, the operation of the digital signal processor is always stopped at that timing.

FIG. 6 shows a timing example of the operation reference clock signal of the digital signal processor 12 with respect to the clock signals φ1 and φ2. According to this example, the operation reference clock signals of the digital signal processor 12 are four-phase clock signals φ11 and φ1.
2, φ13, φ14, all of which are set to the low level during the digital signal processor 1
In No. 2, operations such as access to built-in memory and calculation are stopped. This stop period is always made to include the falling timings of the clock signals φ1 and φ2, and such timing control is performed by the echo cancel LSI 1 shown in FIG.
The timing generator 16 included in 0 performs this. Therefore, when the digital signal processor 12 operates synchronously with the analog front-end unit 11, the operation of the digital signal processor 12 at the sampling timing of the analog integrator 21 and the local D / A converter 20. Will stop,
The analog operation characteristics of the analog front end unit 11 are prevented from being deteriorated by digital noise.

When the operation of the digital circuit is stopped during the operation of the analog circuit as described above, the operation speed of the analog circuit is uniquely or slightly depending on the relationship with the operation speed of the target system processed by the analog circuit and the bit precision. Due to the nature of being decided without any degree of freedom, the time margin or processing capacity that can stop the operation of the digital circuit while the analog circuit is operating is the machine for improving the processing capacity of the digital circuit or for a series of processing. It is desirable to obtain it by reducing the number of cycles. The architecture of a digital signal processor for that purpose will be described below with reference to the echo cancellation LSI 10.

First, the overall structure of the echo cancellation LSI 10 will be described with reference to FIG. The echo cancellation LSI 10 includes an analog front end unit 11, a digital signal processor 12, an event information register file 13, a protocol control unit 14, a timer counter unit 15, a timing generator 16, and an analog. Phase locked loop circuit 17, U point interface circuit 18, and S point interface circuit 1
9, and is formed on one semiconductor substrate such as a silicon substrate by a known Bi-CMOS process or the like. The digital signal processor 12 and the event information register file 1
3 constitutes a digital signal processing unit.

The digital signal processor 1
2 is composed of a control block and a calculation block,
The control block refers to the event information register file 13, executes a microprogram according to a predetermined procedure, and causes the operation block to function as an adaptive filter or the like to realize an echo canceller or the like. The analog front end unit 11
Performs D / A conversion of transmission signals and A / D conversion of reception signals. The U point interface circuit 18 is connected to the exchange side via a hybrid transformer or a balancing network circuit (not shown). The event information register file 13 is a register for holding transition states generated in the digital signal processor 12 and the protocol control unit 14, and the units 12 and 14 are the event information register file. The transition state set in 13 is detected to determine the operation, and the transition state is set according to the processing content. The protocol control unit 14 performs protocol processing such as frame processing, transmission processing such as scrambling, and reception processing such as synchronization. The timer / counter unit 15 is used for state transition control and the like, and the timing generator 16 generates various operation clock signals for the echo cancellation LSI 10. The analog phase locked loop circuit 17 multiplies the system clock signal supplied from the outside and supplies it to the timing generator 16. The S-point interface circuit 19 interfaces with the subscriber side.

FIG. 15 shows the timing generator 16
One example is shown. Timing generator 1
Reference numeral 6 includes an analog signal generation circuit ASG, a digital signal generation circuit DSG and an enable signal generation circuit ESG. The digital signal generation circuit DSG receives the clock signals of a plurality of phases having a constant cycle supplied from the analog phase locked loop circuit 17, and forms a clock signal for operating the digital circuit. Analog signal generation circuit A
SG is an analog phase locked loop circuit 1
It receives a predetermined clock signal out of a plurality of phase clock signals supplied from 7 and forms and outputs a clock signal for analog circuit operation. Enable signal generation circuit ESG
Generates an enable signal EN by receiving the predetermined clock signal. Digital signal generation circuit D
The SG outputs a clock signal for operating a digital circuit while receiving the enable signal EN. By controlling the digital signal generation circuit DSG by the enable signal EN, the clock for digital circuit operation is kept for a predetermined period including the falling timing of the clock signal for analog circuit operation as shown in FIG. 1 or 6. No signal is output from the timing generator 16.

FIG. 7 shows the echo cancel LSI 10 described above.
An example of a functional block diagram in the case of operating the as an echo canceller or the like is shown. In the figure, 30 is an echo canceller, 31 is a decision feedback equalizer for removing intersymbol interference of signals, both of which are realized by adaptive filters. Reference numeral 32 is a slicer for slicing the input signal into, for example, four-valued levels, and outputs decision data DD composed of a 1-bit sign bit and 2-bit information bits. Three
Reference numeral 3 is an error signal detector that forms an error signal ES, and 34 is an auto-threshold controller for generating a voltage (slice voltage) Vref between four levels. The digital signal processor 12 will implement those functions according to its operating procedure.

The signal S such as transmission data output from the protocol control unit 14 is not particularly limited, but is one of four values determined by a 1-bit sign bit and 2-bit information bit. It means a 3-bit signal, which is D / A converted and given to a balancing network circuit (not shown), and a received analog signal input to the balancing network circuit is A / D converted into a digital signal to be a digital signal. -Supplied to the processor 12. The echo cancellation LSI 10 can perform transmission and reception in parallel in full duplex. At this time, the balancing network circuit removes the voltage component of the transmission analog signal from the voltage component given to the hybrid transformer from the line by taking into consideration the impedance of the hybrid transformer coupled to the line to perform D / A conversion. A part of the signal transmitted via the hybrid transformer is prevented from wrapping around to the A / D conversion side, but this wrap-around prevention is realized under the assumption that the impedance of the line is always constant. Therefore, there is an error in the impedance of the line, the state of the line changes over time, and it is impossible to predict what state the line will be connected to. An echo canceller 30 is required for reliably removing the echo component sneaking around from the receiver to the receiving side. .

The echo canceller 30 inputs one signal S within one sampling period in the circuit of FIG.
According to the algorithm of the adaptive filter shown in FIG. 12, which will be described later, calculation for all taps is performed and the filter output signal Y
To get The echo component D (see FIG. 12) is canceled by the filter output signal Y. Similarly, the decision feedback equalizer 31 also performs adaptive filter calculation. The filter outputs from the echo canceller 30 and the decision feedback equalizer 31 are subtracted from the A / D-converted signal RCV (received signal containing an echo component) in the one sample period, whereby the transmitted signal is obtained. The fur component from which some or all of the echo components and intersymbol interference components of the signal have been removed
Get the end signal FES. This far end
The signal FES is sliced into four levels by the slicer 32 and used as decision data DD. The error signal detector 33 subtracts the product of the decision data DD and the slice voltage Vref from the far end signal FES to generate an error signal ES, which is generated by the echo canceller 30 and the decision feedback controller.
Give to the equalizer 31. As a result, the echo canceller 30 and the decision feedback equalizer 31 use the error signal ES for updating the tap coefficient. During the training period, the signal S is a training signal, and the signal RCV at this time is substantially an echo component of the training signal. Echo canceller 30 and decision feedback equalizer 3
1 repeatedly operates as an adaptive filter,
The tap coefficient is updated so that the error signal ES is converged to zero so that the far-end signal FES in which the echo component is substantially completely canceled is obtained at the end of the training period. During communication after training, it operates so as to cancel the echo by following changes in the line status. At this time, the decision data D
D is given to the protocol control unit 14 as received data.

The echo cancellation LSI 10 is not particularly limited, but a cycle defined by a frequency of 80 KHz is set as a processing period (unit interval) for one sample data, and conditional branching such as transition state detection and state setting is performed in each interval. In addition to performing non-arithmetic processing such as flag processing and digital signal processing. The content of the digital signal processing is processing such as an echo canceller, a decision feedback equalizer, and a slicer described with reference to FIG. 7, and control of what kind of processing is performed in what kind of situation is performed in the transition state. It is realized by state transition control that is determined by conditional branching such as detection and state setting and flag processing. Digital signal processing is naturally performed by repeatedly executing arithmetic instructions, but state transition control is performed by non-arithmetic processing. In this embodiment, a non-calculation instruction for state transition control is executed in parallel with digital signal processing. For example, as shown in FIG. 8, in one unit interval, echo cancellation (EC) corresponding to the echo canceller 30 and decision feedback
For calculation processing such as decision feedback equalization (DFE) corresponding to the equalizer 31 and slice (SLC) corresponding to the slicer 32, and state transition control (STC) such as conditional branching and flag processing that does not use a data memory or arithmetic unit The non-calculation process is not performed in time series, and the non-calculation process is performed in parallel with echo cancellation (EC), for example. As a result, the number of operation cycles required for the processing amount to be processed in the digital signal processing unit 12 in one unit interval is reduced from m + n to m. The length of one unit interval is determined by the operating speed of the analog front-end unit 11, that is, the operating speed of the target system that it processes, bit precision, etc., and during that period, the digital signal processor 12 Since the number of operation cycles to be operated is reduced, the reduced operation cycle time is taken into account by the analog front end unit 11
Can be allotted to stop the operation of the digital signal processor 12 during the operation. According to this embodiment, the frequency of the operation reference clock signal of the digital signal processor 12 is lowered so that part of the extended cycle time of the digital signal processor 12 as shown in FIG. Allocate as operation stop time. Reducing the frequency of the operation reference clock signal of the digital signal processor 12 contributes to low power consumption and reduction of digital noise in the entire digital signal processor 12. Furthermore, this enables echo cancellation LS
It is possible to easily deal with the case where I is fed from the exchange or there is a limit to the power distribution that can be consumed by battery feeding. In FIG. 8, all state transition control (ST) is performed in parallel with the echo cancellation (EC) processing.
Although illustrated as performing C), the state transition control (STC) is distributed in parallel with the respective calculation processes such as echo cancellation (EC), decision feedback equalization (DFE), and slice (SLC). Thus, it is possible to parallelize the state transition control for the next arithmetic processing with the immediately preceding arithmetic processing.

FIG. 9 shows an embodiment of the instruction control block of the digital signal processor 12 for performing such parallel processing.

The instruction control block 40 has a micro ROM 41 as an example of a control memory, and the ROM 41 is described with a mixture of operation instructions such as adaptive filter processing for echo cancellation and non-operation instructions for state transition control. Own a micro program. Micro ROM 4
The access address of 1 is designated by the program counter PC. Two instruction registers IR1 and IR2 are provided to hold the microinstructions read from the micro ROM 41 according to the value of the program counter PC so that the arithmetic instructions and the non-instruction instructions can be executed in parallel. The instruction decoders IDEC for decoding micro instructions are also provided with two instruction decoders IDEC1 for operation instructions and instruction decoder IDEC2 for non-operation instructions. The selector SEL makes it possible to select a microinstruction to be supplied to the instruction decoder IDEC1 from either the instruction register IR1 or IR2. The repeat counter RC is a counting means for managing the number of times the instruction to be repeatedly executed is repeated. The instruction decoder IDEC2 has a logic dedicated for decoding and executing a non-operation instruction for state transition control, and the other instruction decoder IDEC1 has a logic for decoding and executing an operation instruction. ..
The control signal output from the instruction decoder IDEC1 controls the inside of the operation block 42 and the instruction control block 40. The other instruction decoder I
The control signal output from the DEC 2 controls the inside of the flag processing block 43 and the instruction control block 40 for state transition control. The flag processing block 43 is included in the event information register file 13.

In the normal instruction execution sequence, the value of the program counter PC is used as an address for the micro R.
The micro instruction read from the OM 41 is supplied to the instruction decoder IDEC1 via the instruction register IR1 and the selector SEL. The instruction decoder IDEC1 decodes the micro instruction and controls the operation block 42 and the like. At this time, the instruction decoder IDEC1 is controlled by the control signal ID2E.
2 is deactivated and its operation is prohibited.

The micro ROM 41 has a repeat instruction, which is not particularly limited, but code information for generating an internal state for repeatedly executing the operation instruction described next and the operation instruction. It has information for specifying the number of repetitions. When this repeat instruction is read from the micro ROM 41 to the instruction register IR1 and supplied to the instruction decoder IDEC1 via the selector SEL, the decoder IDEC1 decodes the instruction to generate the control signals SC, ID2E, IR2E, ES. A state different from that in the normal instruction execution sequence is set, and then the inside of the instruction control block 40 is set as follows so as to repeatedly execute the operation instructions described in the micro ROM 41.

The enable signal ES is output to the repeat counter RC so that the repeat counter RC is preset with the number of instruction repetitions held by the repeat instruction latched in the instruction register IR1. The repeat counter RC takes in the instruction repeat number from the instruction register IR1 when the enable signal ES is supplied. Further, in the next operation cycle, the micro instruction to be repeatedly executed is read from the micro ROM 41 and similarly the instruction decoder IDE
At this time, the instruction decoder IDEC1 decodes only the relevant instruction output from the instruction register IR1 and executes the control signal IR.
2E internally transfers to and holds the instruction register IR2. In the subsequent instruction execution cycle, the instruction decoder IDEC1
The control signal ID2E is inverted to the enable level to activate the other instruction decoder IDEC2, and the control signal SC switches the selector SEL to repeatedly supply the micro instruction stored in the instruction register IR2 to the instruction decoder IDEC1. To be executed repeatedly. During the repeated execution of such an arithmetic instruction, the repeat counter R
C decrements the preset value each time the instruction is executed, and when the count value is returned to zero, the count-up signal CNTU
P is output to the instruction decoder IDEC1.

During this time, the micro instruction read from the micro ROM 41 is supplied to the instruction decoder IDEC2 via the instruction register IR1. The microinstruction thus supplied is a non-arithmetic instruction for controlling the state transition, and controls the flag processing block 43 and the like to execute a conditional branch in parallel with the arithmetic processing using the arithmetic block 42. Execute state transition control such as flag processing. The number of instruction executions for state transition control is reduced with respect to the repeated processing of arithmetic instructions. Therefore, when the state transition control is completed, the instruction decoder IDEC2 stops the operation of the program counter PC and the output operation of the instruction register IR1 by the control signal PCW, and waits for the end of the repetitive arithmetic processing. The count value is incremented from the repeat counter RC by setting the calculated value to zero.
Is output, the instruction decoder IDEC1 recognizes the end of the repetitive arithmetic processing. The instruction decoder IDEC1 then controls the control signals SC and I.
Return D2E and IR2E to the state at the time of normal instruction execution sequence. The selector SEL is switched to the instruction register IR1 side by the control signal SC, and the instruction decoder IDEC2 receives the control signal ID2E.
Invert. As a result, the operation of the program counter PC is enabled so that the instruction decoder IDEC1 decodes the next microinstruction and the normal microinstruction can be executed.

The operation block 42 shown in FIG. 9 is used as an adaptive filter. Here, the operation block 42
Before describing in detail, the algorithm of the adaptive filter will be described first.

FIG. 12 shows an example of a transversal type adaptive filter algorithm. In FIG. 12, S is an input signal, and Z is not particularly limited, but the input signal S
The delay elements C0 to Cn, which sequentially hold the input signal S with a delay time corresponding to the sampling period of, are tap coefficients. The adaptive filter repeats the same processing for each tap in time series. The processing is to multiply the input signal S by the corresponding tap coefficient (MM) and add the value for all taps (TA). The output calculation process for obtaining the filter output Y and the tap coefficient update process for updating the tap coefficient according to the error signal ES are roughly classified. In the tap coefficient update process, the error signal ES is multiplied by the input signal S (M).
Then, the tap update coefficient or the convergence coefficient is given to that value (K) to obtain the update amount of the tap coefficient, and the previous tap coefficient is added to this update amount (A), and this is set as a new tap coefficient. It is a thing. The tap coefficient is stored in the data memory in correspondence with the address, and the tap coefficient read from the data memory is the multiplication M of the output calculation processing of the filter.
It is used for addition A for M and tap coefficient update processing.
The tap coefficient updated by the addition A will be written back to the same address in the data memory.

FIG. 13 shows an embodiment of the operation block 42 for forming the adaptive filter shown in FIG. In the figure, DRM is a data memory for holding the tap coefficients C0 to Cn shown in FIG. 12 in correspondence with addresses, and SRM is a symbol memory such as a shift register functioning as a delay element. Registers RS0, RS1, RB, ESR, RDLT in operation block 42, selector SEL, accumulator ACC, multiplier MULT
1, MULT2, arithmetic logic operation circuits ALU1, ALU
2 and the bus drivers BDRV and BDRV2 are controlled in operation by a control signal supplied from the instruction decoder IDEC1.

The operation block 42 is dedicated as an adaptive filter, and an output operation processing circuit 72 of the filter and an update operation processing circuit 73 are separately provided.

The output arithmetic processing circuit 72 of the filter is composed of an input register RB, a selector SEL, a multiplier MULT1, an output register RG, an arithmetic logic operation unit ALU1 and an accumulator ACC. Symbol memory S
The input signal read from RM is given to one input terminal (not shown) of multiplier MULT1 from one of registers RS0 and RS1 by selector SEL, and the tap coefficient read from data memory DRM is input register RB.
Is applied to the other input terminal (not shown) of the multiplier MULT1. The multiplier MULT1 multiplies these inputs (multiplication process MM in FIG. 12) and outputs the multiplication result to the output register R.
It is applied from G to one input terminal (not shown) of the arithmetic and logic unit ALU1. The arithmetic logic unit ALU1 inputs the addition value held in advance by the accumulator ACC from the other input terminal (not shown), and adds the output value of the register RG and the output value of the accumulator ACC (addition processing TA in FIG. 12). .. Then, the arithmetic logic unit ALU1 outputs the addition result to the accumulator ACC. The arithmetic logic unit ALU1 uses the value held in the accumulator ACC as the filter output Y when the outputs of all the taps for one sample signal are added to the bus driver B.
The data is output to the common internal data bus 71 via DRV1.

The tap coefficient update operation processing circuit 73 is composed of a register ESR, a multiplier MULT2, a shifter SHIFT, a register RDLT, an arithmetic logic operation unit ALU2, and a data memory DRM. An error signal is held in the register ESR, and this error signal and the register R
The input signal supplied from S0 is multiplied by the multiplier MULT2 (multiplication process M in FIG. 12), and the multiplication result is the shifter S.
The bits are shifted by a predetermined bit in the HIFT (update coefficient K adding process in FIG. 12) and held in the register RDLT. The arithmetic logic unit ALU2 adds the tap coefficient update amount held in the register RDLT and the tap coefficient supplied from the data memory DRM (addition processing A in FIG. 12). The updated tap coefficient is written back to the same address in the data memory DRM.

Since the arithmetic logic unit ALU2 and the data memory DRM rewrite the value obtained by adding the update amount to the tap coefficient read from the data memory DRM to the same address of the data memory DRM and sequentially hold it. The integrator circuit is constructed so that its function is clear. At this time, the data transfer path for giving the tap coefficient read from the data memory DRM to the arithmetic and logic unit ALU2 is constituted by the dedicated data bus 70. Further, the data memory DRM is operated in a so-called read-modify-write format in which read and write operations are performed in one machine cycle that defines the operation of the operation block 42 in FIG. The dedicated data bus 70 is not shared by other circuit modules, is locally arranged, and the length of the bus signal line is set to be the shortest, so that an undesired load component is extremely small and the arithmetic logic unit ALU2 is used. The tap coefficient can be transmitted to the data memory at high speed, and the data memory DRM can be read / modify / write without difficulty in timing. Therefore, the integration calculation for updating the tap coefficient can be reliably performed in one machine cycle per tap. Here, assuming that the number of signal lines forming the common internal data bus 71 is n and the number of signal lines forming the dedicated data bus 70 is n, the relationship of m <n is established.

The tap coefficient read from the data memory DRM is also supplied to the register RB through the common internal data bus 71 for the filter output operation. At this time, the dedicated data bus 70 is the common internal data bus. 71
If there is a risk that the transmission of the tap coefficient on the dedicated data bus 70 may be delayed by being directly connected to the bus, a bus that also functions as a buffer between the common internal data bus 71 and the dedicated internal data bus 70. It is advisable to arrange the driver BDRV2. Bus driver BDRV1, BDR
Each V2 is provided with the number (m) of signal lines forming the common internal data bus 71, but only one is shown for simplification of the drawing.

The result of the operation of the predetermined data in the operation block 42, that is, the signal indicating that the operation causes overflow or carry is supplied to the instruction decoder IDEC2 through the instruction decoder IDEC1 and the signal line SL. It

FIG. 14 shows an embodiment of the flag processing block 43 shown in FIG. For example,
Each of the flags 0 to m is composed of a flip-flop.
The instruction decoder IDEC2 forms the flag write address FWA by decoding the instruction supplied from the instruction register IR1.
It is supplied to the address decoder ADC. The address decoder ADC selects flags 0 to n + 1 according to the supplied flag write address FWA. The selected flags 0 to n + 1 correspond to the instruction decoder IDEC2.
"0" is written by the flag reset signal FR formed by decoding the instruction, or "1" is written by the flag set signal FS. Further, the instruction decoder IDEC2 decodes the operation result supplied from the operation block 42 to form the flag write address FWA, and supplies the flag write address FWA to the address decoder ADC. Address decoder ADC
Selects flags 0 to n + 1 according to the supplied flag write address FWA. Selected flags 0-n
For +1, "0" is written by the flag reset signal FR formed by the instruction decoder IDEC2 decoding the instruction, or "1" is written by the flag set signal FS. Flag n
+2 to m are the analog front end unit 11 or the digital signal processor 1
2 or protocol control unit 14
Signals A, B, C, X, Y from are set. The signals A, B, C, X, Y are, for example, echo cancellation LS
A signal indicating that the external device of I10 transfers data to the echo cancellation LSI 10 or a signal indicating the synchronization state of the signal received by the echo cancellation LSI 10. The selector SLT sets the flag 0 according to the flag read address FRA formed by decoding the instruction in the instruction decoder IDEC2.
The data stored in the predetermined flag of m to m is output to the instruction decoder IDEC2.

The above parallel processing will be described more specifically. This parallel processing is not particularly limited, but can be realized by the following instruction description, for example. RPT (REPEAT) OP (OPERATION) CALL SUB (subroutine call instruction) If Eir (Address No. i) = 1 Goto A If Eir (Address No. j) = 1 Goto B ↓ If Eir = No. Address. 1 Goto G A; Set Reg ← next state address, goto EXIT B; Set Reg ← next state address, goto EXIT ↓ G; Set Reg ← next state address, goto EXIT EXIT; RETURN WAIT (wait instruction)

The "RPT" is a repeat instruction, and also holds the number of times the operation instruction is repeated, the number of instructions to be repeated, a preset value of a pointer for generating an operand address required for executing the operation instruction, and the like.

The "OP" is an arithmetic instruction to be repeatedly executed by a repeat instruction, and is a single or plural instruction. In the case of a plurality of instructions, the instruction register IR2 holds the plurality of operation instructions in order and outputs the held instructions alternately and repeatedly. For example, when the operation instruction is adaptive filter processing for echo cancellation or the like, a single operation instruction or a plurality of operation instructions per tap according to the algorithm shown in FIG. 12 are described.

The "CALL SUB" is a subroutine call instruction for detecting the transition state and setting the state. The transition state detection and state setting processing is a subroutine because the processing performed according to the detected state is unique processing. In the subroutine, the value held in the register in the event information register file 13 designated by the value of the address (i, j, to x) given by the If statement has a logic 1 or a logic 0.
The transition state is detected by this, and the process branches to the process designated by the label (A, B, to G) of the If sentence.
The process specified by the label is a process of setting the address of the next state to be processed in the internal register of the digital signal processor. For example, the start address of an instruction to be executed in the next unit interval. The description order of the If sentence is according to the priority order to be processed by the state transition control. After executing the process specified by the label, the process returns from the subroutine.

The "WAIT" is a wait instruction,
The instruction is executed after returning from the subroutine. This wait instruction is an instruction for stopping the operation of the program counter PC and the output operation of the instruction register IR1 by the control signal PCW and waiting for the end of the repeated arithmetic processing. This wait state is a count-up CN output from the repeat counter RC.
It is released by setting TUP to the enable level (count value is zero).

FIG. 10 shows a timing chart of parallel processing by the operation instruction and the non-operation instruction according to the instruction description. In the normal instruction execution sequence, the control signal SL
C selects the output of the instruction register IR1, and the control signal IR2E sets the instruction register I.
Instruction fetching into R2 is prohibited. Also, the negated control signal PCW causes the program counter PC to
Also, the operation of the instruction register IR1 is permitted, and the instruction decoder IDEC2 is deactivated by the negated control signal ID2E.

The repeat instruction (RPT) is a micro R
When read from the OM 41 to the instruction register IR1, the instruction decoder IDEC1 decodes it and presets the repeat counter RC with the number of instruction repetitions n. In the next operation cycle, the operation instruction (OP) to be repeatedly executed is read from the micro ROM 41 and similarly the instruction decoder IDE
It is decoded by C1 and executed. At this time, the control signal I
By temporarily setting R2E to the high level, the instruction output from the instruction register IR1 is internally transferred to the instruction register IR2. Then, in the subsequent instruction execution cycle, the instruction decoder IDEC1 outputs the control signal ID2E.
To the enable level (high level) to activate the other instruction decoder IDEC2 and switch the selector SEL while the control signal SC is at the high level to switch the instruction register IR2.
The micro-instruction held by is repeatedly supplied to the instruction decoder IDEC1 to repeatedly execute the operation instruction. The repeat counter RC decrements the preset value n each time the instruction is executed during the repeated execution of the operation instruction.

During this time, a subroutine call instruction (CALL SU described later in the operation instruction OP is described.
B) is read from the micro ROM 41 and supplied to the instruction decoder IDEC2 via the instruction register IR1. In this manner, various subroutine instructions (SUB), which are non-operation instructions for state transition control, are executed in parallel with the arithmetic processing. When the execution of the subroutine is completed, a wait instruction (WAIT) is read from the micro ROM 41, and the instruction decoder IDEC2 decodes the instruction to set the control signal PCW to the high level, and the operation of the program counter PC and the output of the instruction register IR1. Stop the operation and wait for the end of the repeated calculation processing. Count-up CN output from repeat counter RC
When TUP is set to the enable level indicating that the count value of the repeat counter RC is zero, the instruction decoder IDEC1 recognizes this and the control signal S
C is set to low level, the selector SEL is switched to the instruction register IR1 side, and the control signal P
Set CW to low level. As a result, the operation of the program counter PC is enabled, the instruction decoder IDEC1 decodes the next microinstruction described after the wait instruction, and the normal microinstruction can be executed.

FIG. 11 shows another embodiment of the instruction control block of the digital signal processor. The instruction control block 44 includes a main memory 51 and a sub-memory 61, which are control memories in which memory spaces are separated from each other in the control system 60 for arithmetic instructions and the control system 50 for non-arithmetic instructions.
And a program counter PC unique to each control memory
3, PC4 is provided, and the control system 60 for the other arithmetic instruction is provided in accordance with the instruction execution state in the control system 50 for the non-arithmetic instruction.
The operation decoders IDEC3 and IDEC4 have the control logic for the parallel operation by synchronizing the operation of the program counter PC4 and executing the operation instruction and the non-operation instruction in parallel at a desired timing. The main memory 51 has a series of microprogram descriptions for detecting and setting the transition state and an instruction for detecting the external synchronization flag described at the end thereof as non-operation instructions. The sub memory 61 holds a microprogram for arithmetic processing such as adaptive filter processing. The instruction decoder IDEC3 has a comparison circuit COM. The comparison circuit COM has, for example, data set in the comparison circuit COM by a predetermined instruction to detect an external synchronization flag, and flag processing specified by the instruction. When a match is detected by comparing with the data stored in the external synchronization flag in the block 43,
The value of the program counter PC4 is reset. As a result, operation instructions are sequentially read from the sub memory 61, and decoded by the instruction decoder IDEC4 to cause the operation block to execute an operation. After executing the arithmetic operation, the arithmetic instruction control system 60 executes a wait instruction or the like to hold the value of the program counter PC4 and take a standby state. Instruction decoder I again
When the reset signal is supplied from the DEC 3 to the program counter PC 4, the arithmetic instruction control system 60 restarts the arithmetic processing. A non-calculation instruction relating to the detection of the sequential transition state and the setting of the transition state is read from the main memory 51 and executed. However, when a series of processing is completed, the instruction for detecting the external synchronization flag is continuously executed at the end thereof. When the external synchronization flag is detected by executing this instruction, the non-operation instruction control system 50 branches to the initial address and resets the program counter PC4 again. With such an architecture as well, non-arithmetic processing such as detection and setting of transition states and arithmetic processing can be performed in parallel, and the apparent number of operation cycles for executing a series of processing can be set similarly to the above embodiment. It can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the configuration of the analog circuit is not limited to the above embodiment, and the A / D converter is not limited to the oversampling type and may be the Nyquist sampling type. The converter may be of any type such as delta-em type, delta-sigma type and interpolation type. Further, the operation instruction is not limited to the digital signal processing operation such as the filter processing and may be an operation for continuous data transfer, and the non-operation instruction is a flag for detecting and setting the transition state. The processing is not limited to the system processing, and any processing that can be performed by using hardware that is not used to execute the operation instruction may be used. Further, although an example of the control storage has been described as a micro ROM in the above embodiment, a ROM having a micro program may be used, and an L memory for evaluation may be used.
A RAM may be used when considering SI.

In the above description, the invention made mainly by the present inventor is the field of application which is the background of the ISD.
The case where the present invention is applied to the echo cancel LSI for N has been described, but the present invention is not limited thereto.
An LSI exclusively used for processing such as voice compression, voice synthesis, and image enhancement, a digital signal processor generally used, and an analog circuit and a digital circuit should be included in the same semiconductor substrate. It can also be widely applied to such a one-chip type microcomputer.

According to the present invention, at least effective conditions can be prevented by preventing deterioration of the operation accuracy of the analog circuit due to noise generated by the operation of the digital circuit which shares the semiconductor substrate with the analog circuit. Can be executed in parallel and can be widely applied to valid conditions.

[0066]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the operation of the digital circuit is stopped during a predetermined operation of the analog circuits sharing the semiconductor substrate with each other, it is possible to prevent the deterioration of the operation accuracy of the analog circuit due to digital noise.

A / D conversion circuit and local D / A using a switched capacitor integrating circuit and a capacitor array
Like an analog circuit including a conversion circuit, when the information to be processed is sampled in a capacitor according to the operation timing of the switch, the operation of the digital circuit is stopped for a predetermined period including the sampling operation, so that the capacitor Since the level of the storage node is not affected by potential fluctuations due to digital noise that has passed through the junction capacitance and the like, and operates by accumulating information with a desired accuracy, it is possible to prevent deterioration of analog characteristics due to digital noise.

As a means for generating such timing, the operation reference clock signal is stopped so as to stop the change of the operation reference clock signal of the digital circuit during a predetermined period including the change timing of the clock signal for controlling the sampling switch. By adopting the clock signal generating means for forming, the control for stopping the operation of the digital circuit for a predetermined period including the sampling operation to the capacitor can be easily performed.

Since the operating speed of the analog circuit is uniquely or without any degree of freedom depending on the operating speed of the target system to be processed, bit precision, etc., the operating speed of the digital circuit is It is desirable for the digital circuit side to deal with the time or processing capacity allowance for stopping the operation. At this time, a digital circuit such as a digital signal processor may be provided with a non-operation in parallel with the execution of the operation instruction. By executing the arithmetic instruction, it is possible to reduce the number of machine cycles required to perform a predetermined process in the digital circuit.

Due to the above effects, it is possible to relatively easily obtain a time or capacity margin for stopping the operation of the digital circuit during the operation of the analog circuit in order to prevent the deterioration of the analog characteristics due to the digital noise. ..

Therefore, the digital / analog mixed L
If the data processing amount required for the entire digital circuit in SI is constant, if the processing capacity per operation cycle in a digital circuit such as a digital signal processing unit is improved, the digital circuit can be operated for a time corresponding to the amount of the capacity improvement. The operation can be stopped, and the deterioration of the analog characteristics due to digital noise can be prevented by adjusting the stop period to the operation timing that is most susceptible to the noise of the analog circuit. To be able to guarantee the characteristics or ability of.

Such measures on the digital circuit side are as follows.
Since it works so as not to increase the operating frequency of the digital circuit, it is also convenient to suppress the increase in power consumption and the increase in digital noise due to this.

The reduction of the number of machine cycles for the series of processing by parallelizing the arithmetic and non-arithmetic processing is not limited to the digital / analog mixed semiconductor integrated circuit, but is to improve the processing speed of a single data processing processor such as a digital signal processor. There is also an effect from the viewpoint.

A specific arithmetic instruction read from the control memory is repeatedly decoded and executed by the first instruction decoder while being held for a plurality of operation cycles, and at the same time, a non-arithmetic instruction is executed from the control memory. By reading and executing it while decoding it by the second instruction decoder, the arithmetic instruction and the non-arithmetic instruction are relatively easily executed in parallel even when the arithmetic instruction and the non-arithmetic instruction are held in a single control memory. Can be made

By controlling the state of the program counter of the other control system in accordance with the instruction execution state of one of the control system for arithmetic instructions and the control system for non-arithmetic instructions and operating both control systems in parallel, Even when the control system of the arithmetic instruction and the control system of the non-arithmetic instruction are controlled using their own control memories, the arithmetic instruction and the non-arithmetic instruction can be executed in parallel.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment for stopping the operation of a digital circuit when the analog circuit operates in the digital / analog mixed LSI according to the present invention.

FIG. 2 is a block diagram of an echo cancellation LSI according to another embodiment of the digital / analog mixed LSI according to the present invention.

FIG. 3 is a diagram illustrating the principle of an oversampling A / D converter.

FIG. 4 is a circuit diagram showing an example of an analog integration circuit and a local D / A converter included in the oversampling A / D converter.

5 is a waveform diagram of an operation clock signal of the circuit shown in FIG.

FIG. 6 is an example timing chart showing a relationship between respective operation clock signals of an analog circuit and a digital circuit.

7 is an echo cancellation LSI shown in FIG.
It is an example functional block diagram realized by.

FIG. 8 is an example explanatory diagram showing in principle a parallel execution state of an operation instruction and a non-operation instruction.

FIG. 9 is a block diagram of an embodiment of an instruction control block for executing an arithmetic instruction and a non-arithmetic instruction in parallel.

10 is a timing chart of an example of a control operation by the instruction control block shown in FIG.

FIG. 11 is a block diagram of yet another embodiment of an instruction control block for executing an arithmetic instruction and a non-arithmetic instruction in parallel.

FIG. 12 is an explanatory diagram of an example of an adaptive filter processing algorithm used for echo cancellation and the like.

FIG. 13 is a diagram showing an embodiment of a calculation block for forming an adaptive filter.

FIG. 14 is a diagram showing an embodiment of a flag processing block.

FIG. 15 is a diagram showing an embodiment of a timing generator.

[Explanation of symbols]

1 semiconductor substrate 2 analog circuit 3 digital circuit 4 switch 5 capacitor a analog circuit operation reference clock signal b digital circuit operation clock signal 11 analog front-end unit 12 digital signal processor 13 event information register file 16 Timing generator 17 Analog phase locked loop circuit 20 Local D / A converter 21 Analog integration circuit CI, CS, C, 2C, 4C, 8C Capacitors S1, S2, S3, S4, S5 switches S61, S62, S71, S72 switch S81, S82, S91, S92 switch φ1, φ2 Operation clock signal of analog front end unit φ11, φ12, φ13, φ14 Digital signal processor Operation reference clock signal 30 Echo canceller 40 Instruction control block 41 Micro ROM PC Program counter IR1, IR2 Instruction register IDEC1, IDEC2 Instruction decoder RC Repeat counter SEL selector 42 Operation block 43 Flag processing block 50 Non-operation instruction control system 51 Main Memory IR3 instruction register IDEC3 instruction decoder PC3 program counter 60 control system for arithmetic instruction 61 sub memory IR4 instruction register IDEC4 instruction decoder PC4 program counter

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[Procedure amendment]

[Submission date] June 17, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Paragraph number 0033

[Correction method] Change

[Correction content]

FIG. 7 shows the echo cancel LSI 10 described above.
An example of a functional block diagram in the case of operating the as an echo canceller is shown. In the figure, 30 is an echo canceller, 31 is a decision feedback equalizer for removing intersymbol interference of signals, both of which are realized by an adaptive filter. Reference numeral 32 is a slicer for slicing the input signal into, for example, four-valued levels, and outputs decision data DD composed of a 1-bit sign bit and 2-bit information bits.
Reference numeral 33 is an error signal detector that forms the error signal ES, and 34 is an auto threshold controller for generating a voltage (slice voltage) Vref between the four levels. The digital signal processor 12 will implement those functions according to its operating procedure.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Paragraph number 0036

[Correction method] Change

[Correction content]

The echo cancellation LSI 10 is not particularly limited, but a cycle defined by a frequency of 80 KHz is set as a processing period (unit interval) for one sample data, and conditional branching such as transition state detection and state setting is performed in each interval. In addition to performing non-arithmetic processing such as flag processing and digital signal processing. The content of the digital signal processing is processing such as an echo canceller, a decision feedback equalizer, and a slicer described with reference to FIG. 7, and control of what kind of processing is performed in what kind of situation is performed in the transition state. It is realized by state transition control that is determined by conditional branching such as detection and state setting and flag processing. Digital signal processing is naturally performed by repeatedly executing arithmetic instructions, but state transition control is performed by non-arithmetic processing. In this embodiment, a non-calculation instruction for state transition control is executed in parallel with digital signal processing. For example, as shown in FIG. 8, in one unit interval, echo cancellation (EC) corresponding to the echo canceller 30 and decision feedback
For calculation processing such as decision feedback equalization (DFE) corresponding to the equalizer 31 and slice (SLC) corresponding to the slicer 32, and state transition control (STC) such as conditional branching and flag processing that does not use a data memory or arithmetic unit The non-calculation process is not performed in time series, and the non-calculation process is performed in parallel with echo cancellation (EC), for example. As a result, the number of operation cycles required for the processing amount to be processed in the digital signal processor 12 in one unit interval is reduced from m + n to m. The length of one unit interval is determined by the operating speed of the analog front-end unit 11, that is, the operating speed of the target system that it processes, bit precision, etc., and during that period, the digital signal processor 12 By reducing the number of operating cycles to operate, the reduced operating cycle time,
It is possible to allocate a time for stopping the operation of the digital signal processor 12 when the analog front-end unit 11 is operated. According to this embodiment, the frequency of the operation reference clock signal of the digital signal processor 12 is lowered so that part of the extended cycle time of the digital signal processor 12 as shown in FIG. Allocate as operation stop time. Digital signal processor 12
Reducing the frequency of the operation reference clock signal of 1 also contributes to lower power consumption and digital noise in the entire digital signal processor 12. Further, this makes it possible to easily cope with the case where the echo cancel LSI is fed from the exchange or the power distribution that can be consumed is limited by the battery feeding. Although FIG. 8 illustrates that all state transition control (STC) is performed in parallel with the echo cancellation (EC) processing, echo cancellation (EC), decision feedback equalization (DFE) ,
It is also possible to disperse the state transition control (STC) in parallel with each arithmetic processing such as a slice (SLC) and parallelize the state transition control for the next arithmetic processing to the previous arithmetic processing. is there.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] Paragraph number 0037

[Correction method] Change

[Correction content]

FIG. 9 shows an embodiment of the instruction control block of the digital signal processor 12 for performing such parallel processing.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] Paragraph number 0050

[Correction method] Change

[Correction content]

The tap coefficient read from the data memory DRM is also supplied to the register RB through the common internal data bus 71 for the filter output operation. At this time, the dedicated data bus 70 is the common internal data bus. 71
If the transmission of the tap coefficient on the dedicated data bus 70 may be delayed by being directly connected to the bus driver, the bus driver may also function as a buffer between the common internal data bus 71 and the dedicated data bus 70. It is advisable to place BDRV2. Bus driver BDRV1, BDRV2
Although each of these is provided with the number (m) of signal lines forming the common internal data bus 71, only one is shown for simplification of the drawing.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] Paragraph number 0058

[Correction method] Change

[Correction content]

FIG. 10 shows a timing chart of parallel processing by the operation instruction and the non-operation instruction according to the instruction description. In the normal instruction execution sequence, the control signal SC
Selects the output of instruction register IR1,
The control signal IR2E is the instruction register IR2.
It is prohibited to import instructions into. Further, the negated control signal PCW allows the operations of the program counter PC and the instruction register IR1,
Further, the instruction decoder IDEC2 is deactivated by the negated control signal ID2E.

[Procedure correction 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Takami Sugino 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (10)

[Claims] 1. A semiconductor integrated circuit comprising an analog circuit and a digital circuit mixedly mounted on one semiconductor substrate, and means for generating a timing for stopping the operation of the digital circuit when the analog circuit performs a predetermined operation. 2. The semiconductor integrated circuit according to claim 1, wherein the analog circuit has a circuit for sampling information to be processed in a capacitor in accordance with an operation timing of a switch, and the predetermined operation of the analog circuit is the sampling operation. .. 3. The means for generating the timing is configured to stop the change of the operation reference clock signal of the digital circuit during a predetermined period including the change timing of the clock signal for controlling the switch for the sampling operation. 3. The semiconductor integrated circuit according to claim 2, which is a clock signal generating means for forming an operation reference clock signal. 4. The digital circuit is a digital signal processor, and comprises instruction control means for executing a non-arithmetic instruction in parallel with execution of the arithmetic instruction. Semiconductor integrated circuit. 5. The instruction control means has a control memory including an arithmetic instruction and a non-arithmetic instruction, and a specific memory read from the control memory in response to occurrence of a state in which a specific arithmetic instruction is to be repeatedly executed. Means for holding the operation instruction, the first instruction decoder for repeatedly decoding and executing the instruction held therein, and the control memory in parallel with the repeated execution of the specific operation instruction. 5. The semiconductor integrated circuit according to claim 4, further comprising: a second instruction decoder for decoding and executing a non-operation instruction read from the. 6. The control memory has a repeat instruction for generating a state in which a specific operation instruction is to be repeatedly executed, and the first instruction decoder decodes the repeat instruction to describe after the instruction. 6. The data processor according to claim 5, further comprising logic for generating an internal state in which the executed arithmetic instruction is repeatedly executed. 7. The instruction control means includes control memories which are arranged in a control system for arithmetic instructions and a control system for non-arithmetic instructions and which are separated from each other in a memory space, and a program counter unique to each control memory. According to the instruction execution state in either the control system of the non-computation instruction or the control system of the non-computation instruction, the operation of the program counter of the other control system is synchronized to execute the instructions in both control systems 5. The semiconductor integrated circuit according to claim 4, further comprising: a control unit that operates in parallel at desired timing. 8. The semiconductor integrated circuit according to claim 5, wherein the arithmetic instruction is a single instruction or a plurality of instructions to be repeatedly executed in an adaptive filter process for realizing an echo canceller. .. 9. A data processor having a control memory including an arithmetic instruction and a non-arithmetic instruction, and executing an instruction read from the control memory, in which a specific arithmetic instruction should be repeatedly executed. Correspondingly, means for holding a specific operation instruction read from the control memory, a first instruction decoder for repeatedly decoding and executing the instruction held therein, and repetition of the specific operation instruction A second instruction decoder for decoding and executing a non-computation instruction read from the control memory in parallel with the physical execution of the data processing processor. 10. A control memory, which is arranged in each of a control system for an arithmetic instruction and a control system for a non-arithmetic instruction, and has a memory space separated from each other, a program counter unique to each control memory, and the non-arithmetic instruction. Controlling means for controlling a program counter in the control system for the arithmetic instruction so that the control system for the arithmetic instruction operates in parallel with the control system for the non-arithmetic instruction in accordance with a specific instruction execution state in the control system. Data processing processor.